[llvm] 58d59f4 - [RISCV] Consider truncate semantics in performINSERT_VECTOR_ELTCombine (#228243)

[via llvm-commits]

Author: Alex Bradbury
Date: 2026-10-02T12:02:43Z
New Revision: 58d59f460cd740c50f66f782a87fa2a29f52ff25

URL: https://github.com/llvm/llvm-project/commit/58d59f460cd740c50f66f782a87fa2a29f52ff25
DIFF: https://github.com/llvm/llvm-project/commit/58d59f460cd740c50f66f782a87fa2a29f52ff25.diff

LOG: [RISCV] Consider truncate semantics in performINSERT_VECTOR_ELTCombine (#228243)

This fixes a miscompile in performINSERT_VECTOR_ELTCombine dating back
to when it was added (#72675), but only just showing up through testing
when a recent unrelated change triggered vectorisation for a function
that trips it within Clang, leading to broken builds on some of the
two-stage RVV buildbots.

After type legalization the scalar binop can be wider than the vector
element type, with the insert implicitly truncating it. That isn't
equivalent for shifts and a similar bug was found and fixed in a
neighbouring combine in #81168. This patch just applies the same fix
(with the same comment even), avoiding the transform if the scalar type
doesn't match the element type.

I used an LLM to root cause the issue and produce the test case.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 13669fa56766de..f3119ad66f0c78 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -23698,6 +23698,10 @@ static SDValue performINSERT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
       return SDValue();
     if (!isa<ConstantSDNode>(InValRHS) && !isa<ConstantFPSDNode>(InValRHS))
       return SDValue();
+    // This INSERT_VECTOR_ELT involves an implicit truncation, and sinking
+    // truncates through binops is non-trivial.
+    if (InVal.getValueType() != VT.getVectorElementType())
+      return SDValue();
     // FIXME: Return failure if the RHS type doesn't match the LHS. Shifts may
     // have 
diff erent LHS and RHS types.
     if (InVec.getOperand(0).getValueType() != InVec.getOperand(1).getValueType())

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
index a1ade4139fe516..0fb5ea38098a94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
@@ -624,3 +624,37 @@ entry:
   %3 = insertelement <2 x i32> %2, i32 %1, i64 1
   ret <2 x i32> %3
 }
+
+; The scalar lshrs are performed on i32 and then implicitly truncated by the
+; insert_vector_elt, so they must not be combined into a vector lshr on the i8
+; elements, which would truncate before the shift instead of after it.
+define <8 x i8> @insert_elt_of_trunc_op(i32 %a) {
+; CHECK-LABEL: insert_elt_of_trunc_op:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vmv.v.x v9, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 2
+; CHECK-NEXT:    srli a1, a0, 8
+; CHECK-NEXT:    vsrl.vv v8, v9, v8
+; CHECK-NEXT:    vmv.s.x v9, a1
+; CHECK-NEXT:    srli a0, a0, 9
+; CHECK-NEXT:    vsetivli zero, 7, e8, mf2, tu, ma
+; CHECK-NEXT:    vslideup.vi v8, v9, 6
+; CHECK-NEXT:    vmv.s.x v9, a0
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v9, 7
+; CHECK-NEXT:    ret
+entry:
+  %b = trunc i32 %a to i8
+  %s8 = lshr i32 %a, 8
+  %s9 = lshr i32 %a, 9
+  %t8 = trunc i32 %s8 to i8
+  %t9 = trunc i32 %s9 to i8
+  %v0 = insertelement <8 x i8> poison, i8 %b, i64 0
+  %v1 = shufflevector <8 x i8> %v0, <8 x i8> poison, <8 x i32> zeroinitializer
+  %v2 = lshr <8 x i8> %v1, <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 poison, i8 poison>
+  %v3 = insertelement <8 x i8> %v2, i8 %t8, i64 6
+  %v4 = insertelement <8 x i8> %v3, i8 %t9, i64 7
+  ret <8 x i8> %v4
+}