[llvm] [AMDGPU] Skip IEEE/DX10Clamp inline compatibility check on targets without them (PR #228389)
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Fri Oct 2 03:44:17 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: sstipano
<details>
<summary>Changes</summary>
Targets without FeatureDX10ClampAndIEEEMode (e.g. gfx12) ignore the amdgpu-ieee and amdgpu-dx10-clamp attributes. Inlining could still be blocked there, because the default IEEE value depends on the calling convention.
---
Full diff: https://github.com/llvm/llvm-project/pull/228389.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (+7-4)
- (modified) llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll (+16-8)
- (modified) llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll (+12-6)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 9662be4530f78..05d91b3fbe743 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -1805,10 +1805,13 @@ bool GCNTTIImpl::areInlineCompatible(const Function *Caller,
// FIXME: dx10_clamp can just take the caller setting, but there seems to be
// no way to support merge for backend defined attributes.
- SIModeRegisterDefaults CallerMode(*Caller, *CallerST);
- SIModeRegisterDefaults CalleeMode(*Callee, *CalleeST);
- if (!CallerMode.isInlineCompatible(CalleeMode))
- return false;
+ // Targets without the DX10Clamp and IEEE mode bits ignore these attributes.
+ if (CallerST->hasFeature(AMDGPU::FeatureDX10ClampAndIEEEMode)) {
+ SIModeRegisterDefaults CallerMode(*Caller, *CallerST);
+ SIModeRegisterDefaults CalleeMode(*Callee, *CalleeST);
+ if (!CallerMode.isInlineCompatible(CalleeMode))
+ return false;
+ }
if (Callee->hasFnAttribute(Attribute::AlwaysInline) ||
Callee->hasFnAttribute(Attribute::InlineHint))
diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
index 47bbd6a00b878..f4f7a8f535e5d 100644
--- a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
+++ b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
@@ -1,4 +1,5 @@
-; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -S -passes=inline < %s | FileCheck %s
+; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -S -passes=inline < %s | FileCheck --check-prefixes=CHECK,MODE %s
+; RUN: opt -mtriple=amdgpu-amd-amdhsa -mcpu=gfx1200 -S -passes=inline < %s | FileCheck --check-prefixes=CHECK,NOMODE %s
define i32 @func_default() #0 {
ret i32 0
@@ -34,21 +35,24 @@ define i32 @dx10_clamp_enabled_call_dx10_clamp_enabled() #1 {
}
; CHECK-LABEL: @dx10_clamp_enabled_call_dx10_clamp_disabled(
-; CHECK-NEXT: call i32 @func_dx10_clamp_disabled()
+; MODE-NEXT: call i32 @func_dx10_clamp_disabled()
+; NOMODE-NEXT: ret i32 0
define i32 @dx10_clamp_enabled_call_dx10_clamp_disabled() #1 {
%call = call i32 @func_dx10_clamp_disabled()
ret i32 %call
}
; CHECK-LABEL: @dx10_clamp_disabled_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define i32 @dx10_clamp_disabled_call_default() #2 {
%call = call i32 @func_default()
ret i32 %call
}
; CHECK-LABEL: @dx10_clamp_disabled_call_dx10_clamp_enabled(
-; CHECK-NEXT: call i32 @func_dx10_clamp_enabled()
+; MODE-NEXT: call i32 @func_dx10_clamp_enabled()
+; NOMODE-NEXT: ret i32 0
define i32 @dx10_clamp_disabled_call_dx10_clamp_enabled() #2 {
%call = call i32 @func_dx10_clamp_enabled()
ret i32 %call
@@ -63,7 +67,8 @@ define i32 @dx10_clamp_disabled_call_dx10_clamp_disabled() #2 {
; Shader calling a compute function
; CHECK-LABEL: @amdgpu_ps_default_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_default_call_default() #0 {
%call = call i32 @func_default()
ret i32 %call
@@ -72,14 +77,16 @@ define amdgpu_ps i32 @amdgpu_ps_default_call_default() #0 {
; Shader with dx10_clamp enabled calling a compute function. Default
; also implies ieee_mode, so this isn't inlinable.
; CHECK-LABEL: @amdgpu_ps_dx10_clamp_enabled_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_dx10_clamp_enabled_call_default() #1 {
%call = call i32 @func_default()
ret i32 %call
}
; CHECK-LABEL: @amdgpu_ps_dx10_clamp_disabled_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_dx10_clamp_disabled_call_default() #2 {
%call = call i32 @func_default()
ret i32 %call
@@ -93,7 +100,8 @@ define amdgpu_ps i32 @amdgpu_ps_dx10_clamp_enabled_ieee_call_default() #3 {
}
; CHECK-LABEL: @amdgpu_ps_dx10_clamp_disabled_ieee_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_dx10_clamp_disabled_ieee_call_default() #4 {
%call = call i32 @func_default()
ret i32 %call
diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
index ecdfe2ade862e..7a99839e89763 100644
--- a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
+++ b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
@@ -1,4 +1,5 @@
-; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -S -passes=inline < %s | FileCheck %s
+; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -S -passes=inline < %s | FileCheck --check-prefixes=CHECK,MODE %s
+; RUN: opt -mtriple=amdgpu-amd-amdhsa -mcpu=gfx1200 -S -passes=inline < %s | FileCheck --check-prefixes=CHECK,NOMODE %s
define i32 @func_default() #0 {
ret i32 0
@@ -34,21 +35,24 @@ define i32 @ieee_enabled_call_ieee_enabled() #1 {
}
; CHECK-LABEL: @ieee_enabled_call_ieee_disabled(
-; CHECK-NEXT: call i32 @func_ieee_disabled()
+; MODE-NEXT: call i32 @func_ieee_disabled()
+; NOMODE-NEXT: ret i32 0
define i32 @ieee_enabled_call_ieee_disabled() #1 {
%call = call i32 @func_ieee_disabled()
ret i32 %call
}
; CHECK-LABEL: @ieee_disabled_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define i32 @ieee_disabled_call_default() #2 {
%call = call i32 @func_default()
ret i32 %call
}
; CHECK-LABEL: @ieee_disabled_call_ieee_enabled(
-; CHECK-NEXT: call i32 @func_ieee_enabled()
+; MODE-NEXT: call i32 @func_ieee_enabled()
+; NOMODE-NEXT: ret i32 0
define i32 @ieee_disabled_call_ieee_enabled() #2 {
%call = call i32 @func_ieee_enabled()
ret i32 %call
@@ -63,7 +67,8 @@ define i32 @ieee_disabled_call_ieee_disabled() #2 {
; Shader calling a compute function
; CHECK-LABEL: @amdgpu_ps_default_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_default_call_default() #0 {
%call = call i32 @func_default()
ret i32 %call
@@ -78,7 +83,8 @@ define amdgpu_ps i32 @amdgpu_ps_ieee_enabled_call_default() #1 {
}
; CHECK-LABEL: @amdgpu_ps_ieee_disabled_call_default(
-; CHECK-NEXT: call i32 @func_default()
+; MODE-NEXT: call i32 @func_default()
+; NOMODE-NEXT: ret i32 0
define amdgpu_ps i32 @amdgpu_ps_ieee_disabled_call_default() #2 {
%call = call i32 @func_default()
ret i32 %call
``````````
</details>
https://github.com/llvm/llvm-project/pull/228389
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