[llvm] [Analysis][NFC] Add SVE load/store tests for non-power-of-2 vectors (PR #228387)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-analysis

Author: David Sherwood (david-arm)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/228387.diff


1 Files Affected:

- (modified) llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll (+67) 


``````````diff
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll b/llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
index b52fddaf8e776..8a89024c7e7a3 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
@@ -236,3 +236,70 @@ define void @scalable_ext_loads() {
   ret void
 }
 
+define void @non_power_of_2_scalable_loads() {
+; CHECK-LABEL: 'non_power_of_2_scalable_loads'
+; CHECK-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %res.nxv5i8 = load <vscale x 5 x i8>, ptr undef, align 8
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %res.nxv17i8 = load <vscale x 17 x i8>, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %res.nxv5i16 = load <vscale x 5 x i16>, ptr undef, align 16
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %res.nxv9i16 = load <vscale x 9 x i16>, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %res.nxv3i32 = load <vscale x 3 x i32>, ptr undef, align 16
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %res.nxv5i32 = load <vscale x 5 x i32>, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:5 SizeLat:2 for: %res.nxv3i64 = load <vscale x 3 x i64>, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:4 CodeSize:4 Lat:7 SizeLat:4 for: %res.nxv7i64 = load <vscale x 7 x i64>, ptr undef, align 64
+; CHECK-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; A510-LABEL: 'non_power_of_2_scalable_loads'
+; A510-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %res.nxv5i8 = load <vscale x 5 x i8>, ptr undef, align 8
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:3 SizeLat:2 for: %res.nxv17i8 = load <vscale x 17 x i8>, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %res.nxv5i16 = load <vscale x 5 x i16>, ptr undef, align 16
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:3 SizeLat:2 for: %res.nxv9i16 = load <vscale x 9 x i16>, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %res.nxv3i32 = load <vscale x 3 x i32>, ptr undef, align 16
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:3 SizeLat:2 for: %res.nxv5i32 = load <vscale x 5 x i32>, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:3 SizeLat:2 for: %res.nxv3i64 = load <vscale x 3 x i64>, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of 4 for: %res.nxv7i64 = load <vscale x 7 x i64>, ptr undef, align 64
+; A510-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+  %res.nxv5i8 = load <vscale x 5 x i8>, ptr undef
+  %res.nxv17i8 = load <vscale x 17 x i8>, ptr undef
+  %res.nxv5i16 = load <vscale x 5 x i16>, ptr undef
+  %res.nxv9i16 = load <vscale x 9 x i16>, ptr undef
+  %res.nxv3i32 = load <vscale x 3 x i32>, ptr undef
+  %res.nxv5i32 = load <vscale x 5 x i32>, ptr undef
+  %res.nxv3i64 = load <vscale x 3 x i64>, ptr undef
+  %res.nxv7i64 = load <vscale x 7 x i64>, ptr undef
+  ret void
+}
+
+define void @non_power_of_2_scalable_stores() {
+; CHECK-LABEL: 'non_power_of_2_scalable_stores'
+; CHECK-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 5 x i8> undef, ptr undef, align 8
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 17 x i8> undef, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 5 x i16> undef, ptr undef, align 16
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 9 x i16> undef, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 3 x i32> undef, ptr undef, align 16
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 5 x i32> undef, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 3 x i64> undef, ptr undef, align 32
+; CHECK-NEXT:  Cost Model: Found costs of RThru:4 CodeSize:4 Lat:1 SizeLat:4 for: store <vscale x 7 x i64> undef, ptr undef, align 64
+; CHECK-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; A510-LABEL: 'non_power_of_2_scalable_stores'
+; A510-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 5 x i8> undef, ptr undef, align 8
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 17 x i8> undef, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 5 x i16> undef, ptr undef, align 16
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 9 x i16> undef, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of 1 for: store <vscale x 3 x i32> undef, ptr undef, align 16
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 5 x i32> undef, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <vscale x 3 x i64> undef, ptr undef, align 32
+; A510-NEXT:  Cost Model: Found costs of RThru:4 CodeSize:4 Lat:1 SizeLat:4 for: store <vscale x 7 x i64> undef, ptr undef, align 64
+; A510-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+  store <vscale x 5 x i8> undef, ptr undef
+  store <vscale x 17 x i8> undef, ptr undef
+  store <vscale x 5 x i16> undef, ptr undef
+  store <vscale x 9 x i16> undef, ptr undef
+  store <vscale x 3 x i32> undef, ptr undef
+  store <vscale x 5 x i32> undef, ptr undef
+  store <vscale x 3 x i64> undef, ptr undef
+  store <vscale x 7 x i64> undef, ptr undef
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/228387