[llvm] 04dadc0 - [RISCV][MC] Restrict mips.ldp / mips.sdp to RV64 only (#227043)

[via llvm-commits]

Author: Zeyi Xu
Date: 2026-10-02T10:07:28Z
New Revision: 04dadc0275c8f781cbf4158299911a6fc822a28b

URL: https://github.com/llvm/llvm-project/commit/04dadc0275c8f781cbf4158299911a6fc822a28b
DIFF: https://github.com/llvm/llvm-project/commit/04dadc0275c8f781cbf4158299911a6fc822a28b.diff

LOG: [RISCV][MC] Restrict mips.ldp / mips.sdp to RV64 only (#227043)

The [P8700-F programmer’s
guide](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=11)
describes an RV64GCZbaZbb processor. Its
[`mips.ldp`](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=355)
writes two 64-bit values to two integer registers, while
[`mips.sdp`](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=364)
takes a 64-bit value from each of two integer registers.

Based on these info, this commit restricts their assembly and
disassembly to RV64.

AI Usage: Amp (GPT 6 Sol) was used to help with tests.

Co-authored-by: Amp <amp at ampcode.com>

Added: 
    llvm/test/MC/Disassembler/RISCV/xmipslsp.txt

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
    llvm/test/MC/RISCV/xmips-invalid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
index 5c2703bd03681..8c950f32366fc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -181,6 +181,7 @@ let mayLoad = 1, mayStore = 0 in {
 def MIPS_LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
                          "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
                Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
+let append Predicates = [IsRV64] in
 def MIPS_LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),
                          "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
                Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
@@ -190,6 +191,7 @@ let mayLoad = 0, mayStore = 1 in {
 def MIPS_SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),
                          "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
                Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;
+let append Predicates = [IsRV64] in
 def MIPS_SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),
                          "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
                Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;

diff  --git a/llvm/test/MC/Disassembler/RISCV/xmipslsp.txt b/llvm/test/MC/Disassembler/RISCV/xmipslsp.txt
new file mode 100644
index 0000000000000..ee53038db1f56
--- /dev/null
+++ b/llvm/test/MC/Disassembler/RISCV/xmipslsp.txt
@@ -0,0 +1,19 @@
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+xmipslsp < %s 2> %t.err \
+# RUN:   | FileCheck %s --check-prefix=CHECK
+# RUN: FileCheck %s --check-prefix=RV32 < %t.err
+# RUN: llvm-mc -disassemble -triple=riscv64 -mattr=+xmipslsp < %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
+
+[0x8b,0x50,0x31,0x91]
+# CHECK: mips.swp s3, s2, 0(sp)
+
+[0x8b,0x44,0x81,0x90]
+# RV32: warning: invalid instruction encoding
+# RV64: mips.ldp s1, s2, 8(sp)
+
+[0x0b,0x45,0x56,0x59]
+# CHECK: mips.lwp a0, a1, 20(a2)
+
+[0x0b,0xd8,0x5b,0xb1]
+# RV32: warning: invalid instruction encoding
+# RV64: mips.sdp s5, s6, 16(s7)

diff  --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
index bc72188865241..de1331c3db070 100644
--- a/llvm/test/MC/RISCV/xmips-invalid.s
+++ b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,5 +1,7 @@
 # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
 # RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s 2>&1 \
+# RUN:   | FileCheck %s -check-prefix=RV32
 
 mips.pause 10
 # CHECK: error: unexpected extra operand for instruction
@@ -42,3 +44,9 @@ mips.swp x18, x19, 8(x2)
 
 mips.sdp 0x10, x3, 12(x4)
 # CHECK: error: register must be a GPR
+
+mips.ldp s1, s2, 8(sp)
+# RV32: :[[@LINE-1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+
+mips.sdp s5, s6, 16(s7)
+# RV32: :[[@LINE-1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}