[llvm] ce4bf0f - [X86] Use integer VT for second argument of X86ISD::VPERMILPV in combineConcatVectorOps. (#228257)

[via llvm-commits]

Author: Craig Topper
Date: 2026-10-02T07:33:45Z
New Revision: ce4bf0febce9ae3d039aa8a229f71b52c35ee9b4

URL: https://github.com/llvm/llvm-project/commit/ce4bf0febce9ae3d039aa8a229f71b52c35ee9b4
DIFF: https://github.com/llvm/llvm-project/commit/ce4bf0febce9ae3d039aa8a229f71b52c35ee9b4.diff

LOG: [X86] Use integer VT for second argument of X86ISD::VPERMILPV in combineConcatVectorOps. (#228257)

Found by adding SDTCisInt support to verifySDNode

Assisted-by: Claude

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7817c86155e5b..81af171fdbeb3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61504,12 +61504,13 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
     case X86ISD::VPERMILPV:
       if (!IsSplat && (VT.is256BitVector() ||
                        (VT.is512BitVector() && Subtarget.useAVX512Regs()))) {
+        MVT IntVT = VT.changeVectorElementTypeToInteger();
         SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
-        SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
+        SDValue Concat1 = CombineSubOperand(IntVT, Ops, 1);
         if (Concat0 || Concat1)
-          return DAG.getNode(Opcode, DL, VT,
-                             Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
-                             Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1));
+          return DAG.getNode(
+              Opcode, DL, VT, Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
+              Concat1 ? Concat1 : ConcatSubOperand(IntVT, Ops, 1));
       }
       break;
     case X86ISD::PSHUFB: