[llvm] CodeGen: Remove TRI arguments from TargetInstrInfo hooks (PR #228164)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 00:33:14 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/228164
>From b568be8b19bdd28db49a8790649dc9c759fad7fe Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 1 Oct 2026 18:36:37 +0200
Subject: [PATCH 1/2] CodeGen: Remove TRI arguments from TargetInstrInfo hooks
TRI can now always directly be referenced from TargetInstrInfo
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 33 +++++-------
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 +-
llvm/lib/CodeGen/BreakFalseDeps.cpp | 8 +--
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp | 2 +-
llvm/lib/CodeGen/ImplicitNullChecks.cpp | 4 +-
llvm/lib/CodeGen/MIRPrinter.cpp | 2 +-
llvm/lib/CodeGen/MachinePipeliner.cpp | 15 ++----
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
llvm/lib/CodeGen/MachineSink.cpp | 2 +-
llvm/lib/CodeGen/ModuloSchedule.cpp | 3 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 20 +++----
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 12 ++---
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 7 ++-
.../AArch64/AArch64StorePairSuppress.cpp | 5 +-
.../lib/Target/AMDGPU/SIInsertHardClauses.cpp | 3 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 11 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 +-
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 2 +-
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 34 ++++++------
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 15 +++---
.../Target/Hexagon/HexagonGenMemAbsolute.cpp | 4 +-
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 3 +-
llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 3 +-
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 6 +--
llvm/lib/Target/Lanai/LanaiInstrInfo.h | 3 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 5 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 3 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 14 ++---
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 11 ++--
llvm/lib/Target/X86/X86InstrInfo.cpp | 53 +++++++++----------
llvm/lib/Target/X86/X86InstrInfo.h | 22 ++++----
.../Target/RISCV/RISCVInstrInfoTest.cpp | 10 ++--
32 files changed, 140 insertions(+), 184 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 0f36bece2c12b..61c534b8f2a42 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1301,7 +1301,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// This function defines the logic to lower COPY instruction to
/// target specific instruction(s).
- void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const;
+ void lowerCopy(MachineInstr *MI) const;
/// Return true when there is potentially a faster code sequence
/// for an instruction chain ending in \p Root. All potential patterns are
@@ -1597,8 +1597,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// abstraction that supports negative offsets.
bool getMemOperandWithOffset(const MachineInstr &MI,
const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable,
- const TargetRegisterInfo *TRI) const;
+ bool &OffsetIsScalable) const;
/// Get zero or more base operands and the byte offset of an instruction that
/// reads/writes memory. Note that there may be zero base operands if the
@@ -1611,8 +1610,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// abstraction that supports negative offsets.
virtual bool getMemOperandsWithOffsetWidth(
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
return false;
}
@@ -1630,8 +1628,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// struct ExtAddrMode which contains all relevant information to make up the
/// address.
virtual std::optional<ExtAddrMode>
- getAddrModeFromMemoryOp(const MachineInstr &MemI,
- const TargetRegisterInfo *TRI) const {
+ getAddrModeFromMemoryOp(const MachineInstr &MemI) const {
return std::nullopt;
}
@@ -1661,8 +1658,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// function can return true even if becomes zero. Specifically cases such as
/// NullValueReg = shl NullValueReg, 63.
virtual bool preservesZeroValueInReg(const MachineInstr *MI,
- const Register NullValueReg,
- const TargetRegisterInfo *TRI) const {
+ const Register NullValueReg) const {
return false;
}
@@ -1729,9 +1725,9 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
}
// Returns a MIRPrinter comment for this machine operand.
- virtual std::string
- createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
- unsigned OpIdx, const TargetRegisterInfo *TRI) const;
+ virtual std::string createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const;
/// Returns true if the instruction is a
/// terminator instruction that has not been predicated.
@@ -2038,9 +2034,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// 3. Calling breakPartialRegDependency() with the same arguments. This
/// allows the target to insert a dependency breaking instruction.
///
- virtual unsigned
- getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI,
+ unsigned OpNum) const {
// The default implementation returns 0 for no partial register dependency.
return 0;
}
@@ -2059,8 +2054,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// This hook works similarly to getPartialRegUpdateClearance, except that it
/// does not take an operand index. Instead sets \p OpNum to the index of the
/// unused register.
- virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ virtual unsigned getUndefRegClearance(const MachineInstr &MI,
+ unsigned OpNum) const {
// The default implementation returns 0 for no undef register dependency.
return 0;
}
@@ -2082,8 +2077,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// An <imp-kill> operand should be added to MI if an instruction was
/// inserted. This ties the instructions together in the post-ra scheduler.
///
- virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {}
+ virtual void breakPartialRegDependency(MachineInstr &MI,
+ unsigned OpNum) const {}
/// Create machine specific model for scheduling.
virtual DFAPacketizer *
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index ffa7f29c550f4..0beb8b959f68d 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -1014,9 +1014,7 @@ void DwarfDebug::constructCallSiteEntryDIEs(const DISubprogram &SP,
if (PhysRegCalleeOperand) {
bool Scalable = false;
const MachineOperand *BaseOp = nullptr;
- const TargetRegisterInfo &TRI =
- *Asm->MF->getSubtarget().getRegisterInfo();
- if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, Scalable, &TRI)) {
+ if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, Scalable)) {
if (BaseOp && BaseOp->isReg() && !Scalable)
CallTarget = MachineLocation(BaseOp->getReg(), /*Indirect*/ true);
}
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 180ebc18db06c..c9e71eb3f8fbc 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -213,7 +213,7 @@ void BreakFalseDeps::processDefs(MachineInstr *MI) {
if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef())
continue;
- unsigned Pref = TII->getUndefRegClearance(*MI, i, TRI);
+ unsigned Pref = TII->getUndefRegClearance(*MI, i);
if (Pref) {
bool HadTrueDependency = pickBestRegisterForUndef(MI, i, Pref);
// We don't need to bother trying to break a dependency if this
@@ -238,9 +238,9 @@ void BreakFalseDeps::processDefs(MachineInstr *MI) {
if (MO.isUse())
continue;
// Check clearance before partial register updates.
- unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
+ unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i);
if (Pref && shouldBreakDependence(MI, i, Pref)) {
- TII->breakPartialRegDependency(*MI, i, TRI);
+ TII->breakPartialRegDependency(*MI, i);
Changed = true;
}
}
@@ -270,7 +270,7 @@ void BreakFalseDeps::processUndefReads(MachineBasicBlock *MBB) {
if (UndefMI == &I) {
if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) {
- TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);
+ TII->breakPartialRegDependency(*UndefMI, OpIdx);
Changed = true;
}
diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
index 9c819beff55af..b2dcf31f15082 100644
--- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
+++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
@@ -146,7 +146,7 @@ bool ExpandPostRA::run(MachineFunction &MF) {
MadeChange |= LowerSubregToReg(&MI);
break;
case TargetOpcode::COPY:
- TII->lowerCopy(&MI, TRI);
+ TII->lowerCopy(&MI);
MadeChange = true;
break;
case TargetOpcode::DBG_VALUE:
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index a1e256bcd7b17..cde25e771daac 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -380,7 +380,7 @@ ImplicitNullChecksImpl::isSuitableMemoryOp(const MachineInstr &MI,
if (!MI.mayLoadOrStore() || MI.isPredicable())
return SR_Unsuitable;
- auto AM = TII->getAddrModeFromMemoryOp(MI, TRI);
+ auto AM = TII->getAddrModeFromMemoryOp(MI);
if (!AM || AM->Form != ExtAddrMode::Formula::Basic)
return SR_Unsuitable;
auto AddrMode = *AM;
@@ -700,7 +700,7 @@ bool ImplicitNullChecksImpl::analyzeBlockForNullChecks(
// If MI re-defines the PointerReg in a way that changes the value of
// PointerReg if it was null, then we cannot move further.
- if (!TII->preservesZeroValueInReg(&MI, PointerReg, TRI))
+ if (!TII->preservesZeroValueInReg(&MI, PointerReg))
return false;
InstsSeenSoFar.push_back(&MI);
}
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 7ac0c40dfd93f..def751e6df6bb 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -989,7 +989,7 @@ static void printMIOperand(raw_ostream &OS, MFPrintState &State,
const MachineRegisterInfo &MRI, bool PrintDef) {
LLT TypeToPrint = MI.getTypeToPrint(OpIdx, PrintedTypes, MRI);
const MachineOperand &Op = MI.getOperand(OpIdx);
- std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
+ std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
switch (Op.getType()) {
case MachineOperand::MO_Immediate:
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 8bf7b804ddc75..ecf9e7a29da06 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3033,9 +3033,6 @@ static bool findLoopIncrementValue(const MachineInstr &MI,
const TargetInstrInfo *TII =
LoopBB->getParent()->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI =
- LoopBB->getParent()->getSubtarget().getRegisterInfo();
-
MachineInstr *Phi = nullptr;
MachineInstr *Increment = nullptr;
@@ -3074,8 +3071,8 @@ static bool findLoopIncrementValue(const MachineInstr &MI,
const MachineOperand *BaseOp;
int64_t Offset;
bool OffsetIsScalable;
- if (TII->getMemOperandWithOffset(*Def, BaseOp, Offset, OffsetIsScalable,
- TRI)) {
+ if (TII->getMemOperandWithOffset(*Def, BaseOp, Offset,
+ OffsetIsScalable)) {
// Pre/post increment instruction
CurReg = BaseOp->getReg();
} else {
@@ -3102,11 +3099,10 @@ static bool findLoopIncrementValue(const MachineInstr &MI,
/// Return true if we can compute the amount the instruction changes
/// during each iteration. Set Delta to the amount of the change.
bool SwingSchedulerDAG::computeDelta(const MachineInstr &MI, int &Delta) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const MachineOperand *BaseOp;
int64_t Offset;
bool OffsetIsScalable;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable))
return false;
// FIXME: This algorithm assumes instructions have fixed-size offsets.
@@ -3247,11 +3243,10 @@ bool SwingSchedulerDAG::mayOverlapInLaterIter(
const MachineOperand *BaseOpB, *BaseOpO;
int64_t OffsetB, OffsetO;
bool OffsetBIsScalable, OffsetOIsScalable;
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!TII->getMemOperandWithOffset(*BaseMI, BaseOpB, OffsetB,
- OffsetBIsScalable, TRI) ||
+ OffsetBIsScalable) ||
!TII->getMemOperandWithOffset(*OtherMI, BaseOpO, OffsetO,
- OffsetOIsScalable, TRI))
+ OffsetOIsScalable))
return true;
if (OffsetBIsScalable || OffsetOIsScalable)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index facf741f12400..917b61f7e38f3 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2211,7 +2211,7 @@ void BaseMemOpClusterMutation::collectMemOpRecords(
bool OffsetIsScalable;
LocationSize Width = LocationSize::precise(0);
if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI)) {
+ OffsetIsScalable, Width)) {
if (!Width.hasValue())
continue;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index cbd2598a47210..87d8cb0932cad 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1540,7 +1540,7 @@ static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
const MachineOperand *BaseOp;
int64_t Offset;
bool OffsetIsScalable;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable))
return false;
if (!BaseOp->isReg())
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index a86ca6ff7e1e8..edae24742ec9f 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -933,11 +933,10 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
/// Return true if we can compute the amount the instruction changes
/// during each iteration. Set Delta to the amount of the change.
bool ModuloScheduleExpander::computeDelta(MachineInstr &MI, unsigned &Delta) {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const MachineOperand *BaseOp;
int64_t Offset;
bool OffsetIsScalable;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable))
return false;
// FIXME: This algorithm assumes instructions have fixed-size offsets.
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 92fc628e888e5..06aae2786127e 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -887,8 +887,7 @@ static void transferImplicitOperands(MachineInstr *MI,
}
}
-void TargetInstrInfo::lowerCopy(
- MachineInstr *MI, const TargetRegisterInfo * /*Remove me*/) const {
+void TargetInstrInfo::lowerCopy(MachineInstr *MI) const {
if (MI->allDefsAreDead()) {
MI->setDesc(get(TargetOpcode::KILL));
return;
@@ -1748,13 +1747,14 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
}
// Default implementation of getMemOperandWithOffset.
-bool TargetInstrInfo::getMemOperandWithOffset(
- const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable, const TargetRegisterInfo * /*RemoveMe*/) const {
+bool TargetInstrInfo::getMemOperandWithOffset(const MachineInstr &MI,
+ const MachineOperand *&BaseOp,
+ int64_t &Offset,
+ bool &OffsetIsScalable) const {
SmallVector<const MachineOperand *, 4> BaseOps;
LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
- Width, &TRI) ||
+ Width) ||
BaseOps.size() != 1)
return false;
BaseOp = BaseOps.front();
@@ -1916,7 +1916,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
return std::nullopt;
const MachineOperand *BaseOp;
- if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, &TRI))
+ if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable))
return std::nullopt;
// FIXME: Scalable offsets are not yet handled in the offset code below.
@@ -2053,9 +2053,9 @@ bool TargetInstrInfo::getInsertSubregInputs(
}
// Returns a MIRPrinter comment for this machine operand.
-std::string TargetInstrInfo::createMIROperandComment(
- const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo * /*RemoveMe*/) const {
+std::string TargetInstrInfo::createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const {
if (!MI.isInlineAsm())
return "";
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 885b27677f786..00ac9b0c687bf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3683,15 +3683,14 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
bool AArch64InstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
if (!LdSt.mayLoadOrStore())
return false;
const MachineOperand *BaseOp;
TypeSize WidthN(0, false);
if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable,
- WidthN, TRI))
+ WidthN, &RI))
return false;
// The maximum vscale is 16 under AArch64, return the maximal extent for the
// vector.
@@ -3701,12 +3700,11 @@ bool AArch64InstrInfo::getMemOperandsWithOffsetWidth(
}
std::optional<ExtAddrMode>
-AArch64InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
- const TargetRegisterInfo *TRI) const {
+AArch64InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI) const {
const MachineOperand *Base; // Filled with the base operand of MI.
int64_t Offset; // Filled with the offset of MI.
bool OffsetIsScalable;
- if (!getMemOperandWithOffset(MemI, Base, Offset, OffsetIsScalable, TRI))
+ if (!getMemOperandWithOffset(MemI, Base, Offset, OffsetIsScalable))
return std::nullopt;
if (!Base->isReg())
@@ -10716,7 +10714,7 @@ AArch64InstrInfo::getOutliningCandidateInfo(
// Does it allow us to offset the base operand and is the base the
// register SP?
- if (!getMemOperandWithOffset(MI, Base, Offset, OffsetIsScalable, &TRI) ||
+ if (!getMemOperandWithOffset(MI, Base, Offset, OffsetIsScalable) ||
!Base->isReg() || Base->getReg() != AArch64::SP)
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 6a8346395eea1..4654fce39b02e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -314,8 +314,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
static void suppressLdStPair(MachineInstr &MI);
std::optional<ExtAddrMode>
- getAddrModeFromMemoryOp(const MachineInstr &MemI,
- const TargetRegisterInfo *TRI) const override;
+ getAddrModeFromMemoryOp(const MachineInstr &MemI) const override;
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
const MachineInstr &AddrI,
@@ -326,8 +325,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ int64_t &Offset, bool &OffsetIsScalable,
+ LocationSize &Width) const override;
/// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
/// This is true for some SVE instructions like ldr/str that have a
diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
index dd775da97112d..f339390b7561a 100644
--- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
@@ -30,7 +30,6 @@ using namespace llvm;
namespace {
class AArch64StorePairSuppress : public MachineFunctionPass {
const AArch64InstrInfo *TII;
- const TargetRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
TargetSchedModel SchedModel;
MachineTraceMetrics *Traces;
@@ -134,7 +133,6 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
return false;
TII = ST.getInstrInfo();
- TRI = ST.getRegisterInfo();
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
Traces = &getAnalysis<MachineTraceMetricsWrapperPass>().getMTM();
@@ -160,8 +158,7 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
const MachineOperand *BaseOp;
int64_t Offset;
bool OffsetIsScalable;
- if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
- TRI) &&
+ if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable) &&
BaseOp->isReg()) {
Register BaseReg = BaseOp->getReg();
if (PrevBaseReg == BaseReg) {
diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
index b25403fb95b9f..7c33ed771a53a 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
@@ -220,7 +220,6 @@ class SIInsertHardClauses {
return false;
const SIInstrInfo *SII = ST->getInstrInfo();
- const TargetRegisterInfo *TRI = ST->getRegisterInfo();
bool Changed = false;
for (auto &MBB : MF) {
@@ -247,7 +246,7 @@ class SIInsertHardClauses {
SmallVector<const MachineOperand *, 4> BaseOps;
if (Type <= LAST_REAL_HARDCLAUSE_TYPE) {
if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2,
- Dummy3, TRI)) {
+ Dummy3)) {
// We failed to get the base operands, so we'll never clause this
// instruction with any other, so pretend it's illegal.
Type = HARDCLAUSE_ILLEGAL;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a69898061c1f9..1571b0f45eb58 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -501,8 +501,7 @@ static bool isStride64(unsigned Opc) {
bool SIInstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
if (!LdSt.mayLoadOrStore())
return false;
@@ -550,11 +549,11 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
unsigned EltSize;
if (LdSt.mayLoad())
- EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
+ EltSize = RI.getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
else {
assert(LdSt.mayStore());
int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
- EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
+ EltSize = RI.getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
}
if (isStride64(Opc))
@@ -4268,9 +4267,9 @@ bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
LocationSize Dummy1 = LocationSize::precise(0);
bool Offset0IsScalable, Offset1IsScalable;
if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
- Dummy0, &RI) ||
+ Dummy0) ||
!getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
- Dummy1, &RI))
+ Dummy1))
return false;
if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 12b0af0c94dc7..70b1f237f3c7e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -298,8 +298,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt,
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
- bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const final;
+ bool &OffsetIsScalable, LocationSize &Width) const final;
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
int64_t Offset1, bool OffsetIsScalable1,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index c802a301418e2..c96b39c81c5a6 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1903,7 +1903,7 @@ void SIScheduleDAGMI::schedule()
IsLowLatencySU[i] = 1;
bool OffsetIsScalable;
if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
- OffsetIsScalable, TRI))
+ OffsetIsScalable))
LowLatencyOffset[i] = OffLatReg;
} else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
IsHighLatencySU[i] = 1;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 404afe6a8c9a9..92e8c0e994e79 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -399,13 +399,13 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
}
-std::string ARMBaseInstrInfo::createMIROperandComment(
- const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const {
// First, let's see if there is a generic comment for this operand
std::string GenericComment =
- TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
+ TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx);
if (!GenericComment.empty())
return GenericComment;
@@ -5184,15 +5184,13 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
//
// FCONSTD can be used as a dependency-breaking instruction.
-unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
- const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(const MachineInstr &MI,
+ unsigned OpNum) const {
auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
if (!PartialUpdateClearance)
return 0;
- assert(TRI && "Need TRI instance");
-
+ const ARMBaseRegisterInfo &TRI = getRegisterInfo();
const MachineOperand &MO = MI.getOperand(OpNum);
if (MO.readsReg())
return 0;
@@ -5209,7 +5207,7 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
case ARM::VMOVv2i32:
case ARM::VMOVv2f32:
case ARM::VMOVv1i64:
- UseOp = MI.findRegisterUseOperandIdx(Reg, TRI, false);
+ UseOp = MI.findRegisterUseOperandIdx(Reg, &TRI, false);
break;
// Explicitly reads the dependency.
@@ -5233,8 +5231,8 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
} else if (ARM::SPRRegClass.contains(Reg)) {
// Physical register: MI must define the full D-reg.
MCRegister DReg =
- TRI->getMatchingSuperReg(Reg, ARM::ssub_0, &ARM::DPRRegClass);
- if (!DReg || !MI.definesRegister(DReg, TRI))
+ TRI.getMatchingSuperReg(Reg, ARM::ssub_0, &ARM::DPRRegClass);
+ if (!DReg || !MI.definesRegister(DReg, &TRI))
return 0;
}
@@ -5245,11 +5243,11 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
// Break a partial register dependency after getPartialRegUpdateClearance
// returned non-zero.
-void ARMBaseInstrInfo::breakPartialRegDependency(
- MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
+void ARMBaseInstrInfo::breakPartialRegDependency(MachineInstr &MI,
+ unsigned OpNum) const {
assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
- assert(TRI && "Need TRI instance");
+ const ARMBaseRegisterInfo &TRI = getRegisterInfo();
const MachineOperand &MO = MI.getOperand(OpNum);
Register Reg = MO.getReg();
assert(Reg.isPhysical() && "Can't break virtual register dependencies.");
@@ -5258,11 +5256,11 @@ void ARMBaseInstrInfo::breakPartialRegDependency(
// If MI defines an S-reg, find the corresponding D super-register.
if (ARM::SPRRegClass.contains(Reg)) {
DReg = ARM::D0 + (Reg - ARM::S0) / 2;
- assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
+ assert(TRI.isSuperRegister(Reg, DReg) && "Register enums broken");
}
assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
- assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
+ assert(MI.definesRegister(DReg, &TRI) && "MI doesn't clobber full D-reg");
// FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
// the full D-register by loading the same value to both lanes. The
@@ -5275,7 +5273,7 @@ void ARMBaseInstrInfo::breakPartialRegDependency(
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
.addImm(96)
.add(predOps(ARMCC::AL));
- MI.addRegisterKilled(DReg, TRI, true);
+ MI.addRegisterKilled(DReg, &TRI, true);
}
bool ARMBaseInstrInfo::hasNOP() const {
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index ed06343716a7f..9bf4e7cef6ddd 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -171,10 +171,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
bool isPredicated(const MachineInstr &MI) const override;
// MIR printer helper function to annotate Operands with a comment.
- std::string
- createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
- unsigned OpIdx,
- const TargetRegisterInfo *TRI) const override;
+ std::string createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const override;
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
int PIdx = MI.findFirstPredOperandIdx();
@@ -348,11 +347,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
getExecutionDomain(const MachineInstr &MI) const override;
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
- unsigned
- getPartialRegUpdateClearance(const MachineInstr &, unsigned,
- const TargetRegisterInfo *) const override;
- void breakPartialRegDependency(MachineInstr &, unsigned,
- const TargetRegisterInfo *TRI) const override;
+ unsigned getPartialRegUpdateClearance(const MachineInstr &,
+ unsigned) const override;
+ void breakPartialRegDependency(MachineInstr &, unsigned) const override;
/// Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned getNumLDMAddresses(const MachineInstr &MI) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp b/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
index 3fd34c6daad94..d635700c3f051 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
@@ -36,7 +36,6 @@ namespace {
class HexagonGenMemAbsolute : public MachineFunctionPass {
const HexagonInstrInfo *TII = nullptr;
MachineRegisterInfo *MRI = nullptr;
- const TargetRegisterInfo *TRI = nullptr;
public:
static char ID;
@@ -72,7 +71,6 @@ bool HexagonGenMemAbsolute::runOnMachineFunction(MachineFunction &Fn) {
TII = Fn.getSubtarget<HexagonSubtarget>().getInstrInfo();
MRI = &Fn.getRegInfo();
- TRI = Fn.getRegInfo().getTargetRegisterInfo();
MachineDominatorTree &MDT =
getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
@@ -121,7 +119,7 @@ bool HexagonGenMemAbsolute::runOnMachineFunction(MachineFunction &Fn) {
const MachineOperand *BaseOp = nullptr;
int64_t Offset;
bool Scalable;
- TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable, TRI);
+ TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable);
// Ensure BaseOp is non-null and register type.
if (!BaseOp || !BaseOp->isReg())
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 97f3d9aee87ee..e78bf6b726663 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -3115,8 +3115,7 @@ bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
/// Get the base register and byte offset of a load/store instr.
bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
OffsetIsScalable = false;
const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
if (!BaseOp || !BaseOp->isReg())
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 30b2c91d44442..5e5c93b2b4ccb 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -222,8 +222,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt,
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
- bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ bool &OffsetIsScalable, LocationSize &Width) const override;
/// Reverses the branch condition of the specified condition list,
/// returning false on success and true if it cannot be reversed.
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 18bddf9c2fc35..33773023f6664 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -778,8 +778,7 @@ bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
bool LanaiInstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
switch (LdSt.getOpcode()) {
default:
return false;
@@ -794,7 +793,8 @@ bool LanaiInstrInfo::getMemOperandsWithOffsetWidth(
case Lanai::LDBz_RI:
const MachineOperand *BaseOp;
OffsetIsScalable = false;
- if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
+ if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width,
+ &getRegisterInfo()))
return false;
BaseOps.push_back(BaseOp);
return true;
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index f9b9d91b5b6b7..2ac81edf49fad 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -73,8 +73,7 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt,
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
- bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ bool &OffsetIsScalable, LocationSize &Width) const override;
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
const MachineOperand *&BaseOp,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index bf7f3df6035d8..e8935ceae4fb3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2891,11 +2891,10 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const {
bool PPCInstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
const MachineOperand *BaseOp;
OffsetIsScalable = false;
- if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
+ if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, &RI))
return false;
BaseOps.push_back(BaseOp);
return true;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 542e0b0701506..d86cf04facaff 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -679,8 +679,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt,
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
- bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ bool &OffsetIsScalable, LocationSize &Width) const override;
/// Returns true if the two given memory operations should be scheduled
/// adjacent.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 68bad5972b935..293a2cc2dc7dc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3560,8 +3560,7 @@ bool RISCVInstrInfo::isLdStSafeToPair(const MachineInstr &LdSt,
bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
if (!LdSt.mayLoadOrStore())
return false;
@@ -3596,7 +3595,8 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
}
const MachineOperand *BaseOp;
OffsetIsScalable = false;
- if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
+ if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width,
+ &getRegisterInfo()))
return false;
BaseOps.push_back(BaseOp);
return true;
@@ -4143,12 +4143,12 @@ std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
}
// MIR printer helper function to annotate Operands with a comment.
-std::string RISCVInstrInfo::createMIROperandComment(
- const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+std::string RISCVInstrInfo::createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const {
// Print a generic comment for this operand if there is one.
std::string GenericComment =
- TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
+ TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx);
if (!GenericComment.empty())
return GenericComment;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 8e47b0e0aff0b..7cfb7f70521b5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -204,8 +204,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
bool getMemOperandsWithOffsetWidth(
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ int64_t &Offset, bool &OffsetIsScalable,
+ LocationSize &Width) const override;
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
int64_t Offset1, bool OffsetIsScalable1,
@@ -283,10 +283,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
LiveIntervals *LIS) const override;
// MIR printer helper function to annotate Operands with a comment.
- std::string
- createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
- unsigned OpIdx,
- const TargetRegisterInfo *TRI) const override;
+ std::string createMIROperandComment(const MachineInstr &MI,
+ const MachineOperand &Op,
+ unsigned OpIdx) const override;
/// Generate code to multiply the value in DestReg by Amt - handles all
/// the common optimizations for this idiom, and supports fallback for
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index db11719b86cbe..dcc627707d13c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4537,8 +4537,7 @@ static unsigned getLoadStoreRegOpcode(Register Reg,
}
std::optional<ExtAddrMode>
-X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
- const TargetRegisterInfo *TRI) const {
+X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI) const {
int MemRefBegin = X86II::getMemoryOperandIdx(MemI.getDesc());
if (MemRefBegin < 0)
return std::nullopt;
@@ -4562,7 +4561,7 @@ X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
- std::optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MI, nullptr);
+ std::optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MI);
if (!AMOrNone)
return true;
@@ -4628,10 +4627,9 @@ bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
return true;
}
-bool X86InstrInfo::preservesZeroValueInReg(
- const MachineInstr *MI, const Register NullValueReg,
- const TargetRegisterInfo *TRI) const {
- if (!MI->modifiesRegister(NullValueReg, TRI))
+bool X86InstrInfo::preservesZeroValueInReg(const MachineInstr *MI,
+ const Register NullValueReg) const {
+ if (!MI->modifiesRegister(NullValueReg, &RI))
return true;
switch (MI->getOpcode()) {
// Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
@@ -4648,7 +4646,7 @@ bool X86InstrInfo::preservesZeroValueInReg(
// null value.
case X86::MOV32rr:
return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
- return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
+ return RI.isSubRegisterEq(NullValueReg, MO.getReg());
});
default:
return false;
@@ -4658,8 +4656,7 @@ bool X86InstrInfo::preservesZeroValueInReg(
bool X86InstrInfo::getMemOperandsWithOffsetWidth(
const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
- int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const {
+ int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
int MemRefBegin = X86II::getMemoryOperandIdx(MemOp.getDesc());
if (MemRefBegin < 0)
return false;
@@ -6999,9 +6996,8 @@ static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
/// Inform the BreakFalseDeps pass how many idle
/// instructions we would like before a partial register update.
-unsigned X86InstrInfo::getPartialRegUpdateClearance(
- const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+unsigned X86InstrInfo::getPartialRegUpdateClearance(const MachineInstr &MI,
+ unsigned OpNum) const {
if (OpNum != 0)
return 0;
@@ -7030,7 +7026,7 @@ unsigned X86InstrInfo::getPartialRegUpdateClearance(
if (Reg.isVirtual())
ReadsReg = (MO.readsReg() || MI.readsVirtualRegister(Reg));
else
- ReadsReg = MI.readsRegister(Reg, TRI);
+ ReadsReg = MI.readsRegister(Reg, &RI);
if (ReadsReg != HasNDDPartialWrite)
return 0;
@@ -7386,9 +7382,8 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
///
/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
/// high bits that are passed-through are not live.
-unsigned
-X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+unsigned X86InstrInfo::getUndefRegClearance(const MachineInstr &MI,
+ unsigned OpNum) const {
const MachineOperand &MO = MI.getOperand(OpNum);
if (MO.getReg().isPhysical() && hasUndefRegUpdate(MI.getOpcode(), OpNum))
return UndefRegClearance;
@@ -7396,11 +7391,11 @@ X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
return 0;
}
-void X86InstrInfo::breakPartialRegDependency(
- MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
+void X86InstrInfo::breakPartialRegDependency(MachineInstr &MI,
+ unsigned OpNum) const {
Register Reg = MI.getOperand(OpNum).getReg();
// If MI kills this register, the false dependence is already broken.
- if (MI.killsRegister(Reg, TRI))
+ if (MI.killsRegister(Reg, &RI))
return;
if (X86::VR128RegClass.contains(Reg)) {
@@ -7410,16 +7405,16 @@ void X86InstrInfo::breakPartialRegDependency(
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if (X86::VR256RegClass.contains(Reg)) {
// Use vxorps to clear the full ymm register.
// It wants to read and write the xmm sub-register.
- Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
+ Register XReg = RI.getSubReg(Reg, X86::sub_xmm);
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
.addReg(XReg, RegState::Undef)
.addReg(XReg, RegState::Undef)
.addReg(Reg, RegState::ImplicitDefine);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if (X86::VR128XRegClass.contains(Reg)) {
// Only handle VLX targets.
if (!Subtarget.hasVLX())
@@ -7428,7 +7423,7 @@ void X86InstrInfo::breakPartialRegDependency(
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VPXORDZ128rr), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if (X86::VR256XRegClass.contains(Reg) ||
X86::VR512RegClass.contains(Reg)) {
// Only handle VLX targets.
@@ -7436,26 +7431,26 @@ void X86InstrInfo::breakPartialRegDependency(
return;
// Use vpxord to clear the full ymm/zmm register.
// It wants to read and write the xmm sub-register.
- Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
+ Register XReg = RI.getSubReg(Reg, X86::sub_xmm);
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VPXORDZ128rr), XReg)
.addReg(XReg, RegState::Undef)
.addReg(XReg, RegState::Undef)
.addReg(Reg, RegState::ImplicitDefine);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if (X86::GR64RegClass.contains(Reg)) {
// Using XOR32rr because it has shorter encoding and zeros up the upper bits
// as well.
- Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
+ Register XReg = RI.getSubReg(Reg, X86::sub_32bit);
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
.addReg(XReg, RegState::Undef)
.addReg(XReg, RegState::Undef)
.addReg(Reg, RegState::ImplicitDefine);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if (X86::GR32RegClass.contains(Reg)) {
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
- MI.addRegisterKilled(Reg, TRI, true);
+ MI.addRegisterKilled(Reg, &RI, true);
} else if ((X86::GR16RegClass.contains(Reg) ||
X86::GR8RegClass.contains(Reg)) &&
X86II::hasNewDataDest(MI.getDesc().TSFlags)) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index fe26940f85357..a01c4cbdb3223 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -444,21 +444,18 @@ class X86InstrInfo final : public X86GenInstrInfo {
int getJumpTableIndex(const MachineInstr &MI) const override;
std::optional<ExtAddrMode>
- getAddrModeFromMemoryOp(const MachineInstr &MemI,
- const TargetRegisterInfo *TRI) const override;
+ getAddrModeFromMemoryOp(const MachineInstr &MemI) const override;
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
int64_t &ImmVal) const override;
bool preservesZeroValueInReg(const MachineInstr *MI,
- const Register NullValueReg,
- const TargetRegisterInfo *TRI) const override;
+ const Register NullValueReg) const override;
bool getMemOperandsWithOffsetWidth(
const MachineInstr &LdSt,
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
- bool &OffsetIsScalable, LocationSize &Width,
- const TargetRegisterInfo *TRI) const override;
+ bool &OffsetIsScalable, LocationSize &Width) const override;
bool analyzeBranchPredicate(MachineBasicBlock &MBB,
TargetInstrInfo::MachineBranchPredicate &MBP,
bool AllowModify = false) const override;
@@ -584,13 +581,12 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
- unsigned
- getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const override;
- unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const override;
- void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
- const TargetRegisterInfo *TRI) const override;
+ unsigned getPartialRegUpdateClearance(const MachineInstr &MI,
+ unsigned OpNum) const override;
+ unsigned getUndefRegClearance(const MachineInstr &MI,
+ unsigned OpNum) const override;
+ void breakPartialRegDependency(MachineInstr &MI,
+ unsigned OpNum) const override;
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
unsigned OpNum,
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 3a70ceace00ec..4aa632ff0b900 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -224,7 +224,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addMemOperand(MMO)
.getInstr();
bool Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI);
+ OffsetIsScalable, Width);
ASSERT_TRUE(Res);
ASSERT_EQ(BaseOps.size(), 1u);
ASSERT_TRUE(BaseOps.front()->isReg());
@@ -242,7 +242,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addImm(36)
.addMemOperand(MMO);
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI);
+ OffsetIsScalable, Width);
ASSERT_TRUE(Res);
ASSERT_EQ(BaseOps.size(), 1u);
ASSERT_TRUE(BaseOps.front()->isReg());
@@ -258,7 +258,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addReg(RISCV::X3)
.addMemOperand(MMO);
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI);
+ OffsetIsScalable, Width);
ASSERT_FALSE(Res); // Vector loads/stored are not handled for now.
BaseOps.clear();
@@ -266,7 +266,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addReg(RISCV::X5)
.addImm(16);
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI);
+ OffsetIsScalable, Width);
BaseOps.clear();
MMO = MF->getMachineMemOperand(MachinePointerInfo(),
@@ -277,7 +277,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addImm(4)
.addMemOperand(MMO);
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
- OffsetIsScalable, Width, TRI);
+ OffsetIsScalable, Width);
ASSERT_TRUE(Res);
ASSERT_EQ(BaseOps.size(), 1u);
ASSERT_TRUE(BaseOps.front()->isFI());
>From 0d12d6e7e13a33be8194fe4d8d36de00f1e7aa59 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 1 Oct 2026 20:15:05 +0200
Subject: [PATCH 2/2] Fix unused variables
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 7 ++---
llvm/lib/CodeGen/MachineScheduler.cpp | 30 +++++++------------
.../Target/Hexagon/HexagonTargetMachine.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 8 ++---
.../Target/RISCV/RISCVInstrInfoTest.cpp | 1 -
5 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 5280a2376c34a..8720ddafc6a14 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1411,19 +1411,16 @@ class LLVM_ABI PostGenericScheduler : public GenericSchedulerBase {
/// reduce reordering due to store clustering.
LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
createLoadClusterDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI,
bool ReorderWhileClustering = false);
/// If ReorderWhileClustering is set to true, no attempt will be made to
/// reduce reordering due to store clustering.
LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
createStoreClusterDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI,
bool ReorderWhileClustering = false);
LLVM_ABI std::unique_ptr<ScheduleDAGMutation>
-createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI);
+createCopyConstrainDAGMutation(const TargetInstrInfo *TII);
/// Create the standard converging machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
@@ -1437,7 +1434,7 @@ ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
// FIXME: extend the mutation API to allow earlier mutations to instantiate
// data and pass it to later mutations. Have a single mutation that gathers
// the interesting nodes in one pass.
- DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+ DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII));
return DAG;
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 917b61f7e38f3..c570233311637 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2028,15 +2028,13 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
};
const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
bool IsLoad;
bool ReorderWhileClustering;
public:
- BaseMemOpClusterMutation(const TargetInstrInfo *tii,
- const TargetRegisterInfo *tri, bool IsLoad,
+ BaseMemOpClusterMutation(const TargetInstrInfo *tii, bool IsLoad,
bool ReorderWhileClustering)
- : TII(tii), TRI(tri), IsLoad(IsLoad),
+ : TII(tii), IsLoad(IsLoad),
ReorderWhileClustering(ReorderWhileClustering) {}
void apply(ScheduleDAGInstrs *DAGInstrs) override;
@@ -2052,36 +2050,31 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
class StoreClusterMutation : public BaseMemOpClusterMutation {
public:
- StoreClusterMutation(const TargetInstrInfo *tii,
- const TargetRegisterInfo *tri,
- bool ReorderWhileClustering)
- : BaseMemOpClusterMutation(tii, tri, false, ReorderWhileClustering) {}
+ StoreClusterMutation(const TargetInstrInfo *tii, bool ReorderWhileClustering)
+ : BaseMemOpClusterMutation(tii, false, ReorderWhileClustering) {}
};
class LoadClusterMutation : public BaseMemOpClusterMutation {
public:
- LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri,
- bool ReorderWhileClustering)
- : BaseMemOpClusterMutation(tii, tri, true, ReorderWhileClustering) {}
+ LoadClusterMutation(const TargetInstrInfo *tii, bool ReorderWhileClustering)
+ : BaseMemOpClusterMutation(tii, true, ReorderWhileClustering) {}
};
} // end anonymous namespace
std::unique_ptr<ScheduleDAGMutation>
llvm::createLoadClusterDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI,
bool ReorderWhileClustering) {
return EnableMemOpCluster ? std::make_unique<LoadClusterMutation>(
- TII, TRI, ReorderWhileClustering)
+ TII, ReorderWhileClustering)
: nullptr;
}
std::unique_ptr<ScheduleDAGMutation>
llvm::createStoreClusterDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI,
bool ReorderWhileClustering) {
return EnableMemOpCluster ? std::make_unique<StoreClusterMutation>(
- TII, TRI, ReorderWhileClustering)
+ TII, ReorderWhileClustering)
: nullptr;
}
@@ -2302,7 +2295,7 @@ class CopyConstrain : public ScheduleDAGMutation {
SlotIndex RegionEndIdx;
public:
- CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
+ CopyConstrain(const TargetInstrInfo *) {}
void apply(ScheduleDAGInstrs *DAGInstrs) override;
@@ -2313,9 +2306,8 @@ class CopyConstrain : public ScheduleDAGMutation {
} // end anonymous namespace
std::unique_ptr<ScheduleDAGMutation>
-llvm::createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
- const TargetRegisterInfo *TRI) {
- return std::make_unique<CopyConstrain>(TII, TRI);
+llvm::createCopyConstrainDAGMutation(const TargetInstrInfo *TII) {
+ return std::make_unique<CopyConstrain>(TII);
}
/// constrainLocalCopy handles two possibilities:
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 84e3390e4f5ae..42418227e7c13 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -188,7 +188,7 @@ static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
- DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+ DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII));
return DAG;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 685bb91583cf5..c8a5483d8dc26 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -290,11 +290,11 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
if (ST.enableMISchedLoadClustering())
DAG->addMutation(createLoadClusterDAGMutation(
- DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->TII, /*ReorderWhileClustering=*/true));
if (ST.enableMISchedStoreClustering())
DAG->addMutation(createStoreClusterDAGMutation(
- DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->TII, /*ReorderWhileClustering=*/true));
if (!DisableVectorMaskMutation && ST.hasVInstructions())
DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
@@ -314,11 +314,11 @@ RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
if (ST.enablePostMISchedLoadClustering())
DAG->addMutation(createLoadClusterDAGMutation(
- DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->TII, /*ReorderWhileClustering=*/true));
if (ST.enablePostMISchedStoreClustering())
DAG->addMutation(createStoreClusterDAGMutation(
- DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->TII, /*ReorderWhileClustering=*/true));
return DAG;
}
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 4aa632ff0b900..a220cf939a38c 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -208,7 +208,6 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
const RISCVInstrInfo *TII = ST->getInstrInfo();
- const TargetRegisterInfo *TRI = ST->getRegisterInfo();
DebugLoc DL;
SmallVector<const MachineOperand *> BaseOps;
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