[llvm] [AMDGPU] Remove unused prefix from branch relaxation test (PR #228344)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 00:06:52 PDT 2026
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/228344
This was added spuriously in #175644.
>From 95f8a82ad1eb1c60e2d2e8ee4efa73bbcbf16764 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 2 Oct 2026 08:05:42 +0100
Subject: [PATCH] [AMDGPU] Remove unused prefix from branch relaxation test
This was added spuriously in #175644.
---
.../AMDGPU/branch-relaxation-gfx1250.ll | 364 ------------------
1 file changed, 364 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
index 7043a7d05bac9..b472ab6b47518 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
@@ -77,29 +77,6 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr
; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
; GCN-ADD-PC64-NEXT: s_wait_storecnt 0x0
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_conditional_max_short_forward_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB0_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB0_2-.Lpost_addpc0
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc0:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB0_1: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB0_2: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb:
%cmp = icmp eq i32 %cnd, 0
br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
@@ -176,30 +153,6 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs
; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
; GCN-ADD-PC64-NEXT: s_wait_storecnt 0x0
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_conditional_min_long_forward_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB1_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB1_2-.Lpost_addpc1
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc1:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB1_1: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB1_2: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb0:
%cmp = icmp eq i32 %cnd, 0
br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
@@ -279,31 +232,6 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
; GCN-ADD-PC64-NEXT: s_wait_storecnt 0x0
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_conditional_min_long_forward_vcnd_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_eq_f32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB2_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB2_2-.Lpost_addpc2
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc2:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB2_1: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: ; 32 bytes
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB2_2: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb0:
%cmp = fcmp oeq float %cnd, 0.0
br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
@@ -394,37 +322,6 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GCN-ADD-PC64-NEXT: global_store_b32 v[0:1], v2, off scope:SCOPE_SYS
; GCN-ADD-PC64-NEXT: s_wait_storecnt 0x0
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: min_long_forward_vbranch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: global_load_b32 v2, v0, s[0:1] scale_offset scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_loadcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-ENABLE-ADD-PC64-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, exec_lo
-; GCN-ENABLE-ADD-PC64-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execnz .LBB3_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB3_2-.Lpost_addpc3
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc3:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB3_1: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: ; 32 bytes
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB3_2: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v[0:1], v2, off scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = zext i32 %tid to i64
@@ -497,26 +394,6 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
; GCN-ADD-PC64-NEXT: .Lpost_addpc4:
; GCN-ADD-PC64-NEXT: .LBB4_2: ; %bb3
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: long_backward_sbranch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB4_1: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_co_i32 s0, s0, 1
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s0, 10
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB4_2
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ; in Loop: Header=BB4_1 Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB4_1-.Lpost_addpc4
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc4:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB4_2: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb:
br label %bb2
@@ -636,45 +513,6 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
; GCN-ADD-PC64-NEXT: .LBB5_5: ; %bb3
; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_3-.Lpost_addpc5
; GCN-ADD-PC64-NEXT: .Lpost_addpc5:
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_unconditional_min_long_forward_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, -1
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB5_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.7: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_4-.Lpost_addpc6
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc6:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB5_1: ; %Flow
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccnz .LBB5_3
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB5_2: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v0, 17
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB5_3: ; %bb4
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 63
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB5_4: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execnz .LBB5_5
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.9: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_2-.Lpost_addpc7
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc7:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB5_5: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_3-.Lpost_addpc5
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc5:
bb0:
%tmp = icmp ne i32 %arg1, 0
br i1 %tmp, label %bb2, label %bb3
@@ -746,25 +584,6 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad
; GCN-ADD-PC64-NEXT: .Lpost_addpc8:
; GCN-ADD-PC64-NEXT: .LBB6_2: ; %DummyReturnBlock
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_unconditional_min_long_backward_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %entry
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 vcc_lo, exec_lo
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB6_1: ; %loop
-; GCN-ENABLE-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccz .LBB6_2
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.3: ; %loop
-; GCN-ENABLE-ADD-PC64-NEXT: ; in Loop: Header=BB6_1 Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB6_1-.Lpost_addpc8
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc8:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB6_2: ; %DummyReturnBlock
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
entry:
br label %loop
@@ -866,43 +685,6 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
; GCN-ADD-PC64-NEXT: v_nop_e64
; GCN-ADD-PC64-NEXT: ;;#ASMEND
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: expand_requires_expand:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb0
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_b32 vcc_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccnz .LBB7_2
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.1: ; %bb1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b32 s0, s[0:1], 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lg_u32 s0, 3
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB7_2: ; %Flow
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccz .LBB7_3
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.5: ; %Flow
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB7_4-.Lpost_addpc9
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc9:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB7_3: ; %bb2
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB7_4: ; %bb3
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb0:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%cmp0 = icmp slt i32 %cond0, 0
@@ -996,32 +778,6 @@ define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %
; GCN-ADD-PC64-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GCN-ADD-PC64-NEXT: s_sleep 5
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: uniform_inside_divergent:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %entry
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s3, exec_lo
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-ENABLE-ADD-PC64-NEXT: v_cmpx_gt_u32_e32 16, v0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execnz .LBB8_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.4: ; %entry
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB8_3-.Lpost_addpc10
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc10:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB8_1: ; %if
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lg_u32 s2, 0
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v0, s[0:1]
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc1 .LBB8_3
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.2: ; %if_uniform
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v1, 1
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB8_3: ; %endif
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_xcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_or_b32 exec_lo, exec_lo, s3
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 5
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%d_cmp = icmp ult i32 %tid, 16
@@ -1143,48 +899,6 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
; GCN-ADD-PC64-NEXT: .Lpost_addpc12:
; GCN-ADD-PC64-NEXT: .LBB9_5: ; %UnifiedReturnBlock
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: analyze_mask_branch:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %entry
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, exec_lo
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e64 v0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: v_cmpx_nlt_f32_e32 0, v0
-; GCN-ENABLE-ADD-PC64-NEXT: s_xor_b32 s0, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execz .LBB9_2
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.1: ; %ret
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v0, 7
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_storecnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB9_2: ; %Flow1
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_xcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execnz .LBB9_3
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.6: ; %Flow1
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB9_5-.Lpost_addpc11
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc11:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB9_3: ; %loop.preheader
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 vcc_lo, 0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB9_4: ; %loop
-; GCN-ENABLE-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccnz .LBB9_5
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.8: ; %loop
-; GCN-ENABLE-ADD-PC64-NEXT: ; in Loop: Header=BB9_4 Depth=1
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB9_4-.Lpost_addpc12
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc12:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB9_5: ; %UnifiedReturnBlock
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
entry:
%reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
%cmp0 = fcmp ogt float %reg, 0.000000e+00
@@ -1374,84 +1088,6 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GCN-ADD-PC64-NEXT: s_add_nc_u64 s[0:1], s[6:7], s[0:1]
; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[0:1]
; GCN-ADD-PC64-NEXT: s_endpgm
-; GCN-ENABLE-ADD-PC64-LABEL: long_branch_hang:
-; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s7, -1
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s6, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lg_u32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s8, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s3, 6
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_scc0 .LBB10_1
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.10: ; %bb
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_4-.Lpost_addpc14
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc14:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_1: ; %Flow
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccnz .LBB10_2
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.12: ; %Flow
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_5-.Lpost_addpc15
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc15:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_2: ; %Flow5
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccz .LBB10_3
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.14: ; %Flow5
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_6-.Lpost_addpc16
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc16:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_3: ; %bb14
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s1, 9
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s2, s3
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s1, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_or_b32 s0, s1, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_b32 s0, s6, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.8: ; %bb14
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_7-.Lpost_addpc13
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc13:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_4: ; %bb13
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMSTART
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: v_nop_e64
-; GCN-ENABLE-ADD-PC64-NEXT: ;;#ASMEND
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_mov_b32 s0, s8
-; GCN-ENABLE-ADD-PC64-NEXT: s_sleep 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_execz .LBB10_5
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.16: ; %bb13
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_2-.Lpost_addpc17
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc17:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_5: ; %bb9
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_lt_i32 s3, 11
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cmp_ge_i32 s2, s3
-; GCN-ENABLE-ADD-PC64-NEXT: s_cselect_b32 s7, -1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_b32 s0, s7, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
-; GCN-ENABLE-ADD-PC64-NEXT: s_cbranch_vccnz .LBB10_6
-; GCN-ENABLE-ADD-PC64-NEXT: ; %bb.18: ; %bb9
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_3-.Lpost_addpc18
-; GCN-ENABLE-ADD-PC64-NEXT: .Lpost_addpc18:
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_6:
-; GCN-ENABLE-ADD-PC64-NEXT: ; implicit-def: $vgpr0
-; GCN-ENABLE-ADD-PC64-NEXT: .LBB10_7: ; %bb19
-; GCN-ENABLE-ADD-PC64-NEXT: s_clause 0x1
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c
-; GCN-ENABLE-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GCN-ENABLE-ADD-PC64-NEXT: v_mov_b32_e32 v1, 0
-; GCN-ENABLE-ADD-PC64-NEXT: s_wait_kmcnt 0x0
-; GCN-ENABLE-ADD-PC64-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
-; GCN-ENABLE-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-ENABLE-ADD-PC64-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
-; GCN-ENABLE-ADD-PC64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GCN-ENABLE-ADD-PC64-NEXT: s_endpgm
bb:
%tmp = icmp slt i32 %arg2, 9
%tmp6 = icmp eq i32 %arg1, 0
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