[llvm] [RISCV] Optimize repeated-half i64 vector splats on RV32 (PR #228119)

[via llvm-commits]

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@@ -5212,6 +5212,17 @@ static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
     }
   }
 
+  // With identical nonconstant halves and undefined passthru, fill the whole
+  // register group at EEW=32. This defines every active i64 element regardless
+  // of VL, and may define additional elements that were undefined.
+  if (!isa<ConstantSDNode>(Lo) && Lo == Hi && Passthru.isUndef()) {
+    MVT InterVT = MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
+    SDValue MaxVL = DAG.getRegister(RISCV::X0, MVT::i32);
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tinfengyu wrote:

Yes. I updated the nonconstant case to use 2 * VL for small constant VLs (0–15), matching the existing constant case. Runtime and larger VLs continue to use VLMAX. I also updated the focused tests for the VL=1 and legalized VL=4 cases. Thanks!

https://github.com/llvm/llvm-project/pull/228119