[llvm] [RISCV] Eliminate redundant materializations after register comparison (PR #227673)
Alexander Richardson via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 21:58:57 PDT 2026
================
@@ -0,0 +1,338 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=riscv32 -mattr=+xqcili -run-pass=riscv-copyelim -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ define void @beq_reg_imm() { ret void }
+ define void @bne_reg_imm() { ret void }
+ define void @clobber_const() { ret void }
+ define void @clobber_target() { ret void }
+ define void @inequality_edge() { ret void }
+ define void @beq_x0_is_zero() { ret void }
+ define void @bne_x0_is_zero() { ret void }
+ define void @beq_reg_imm_swapped() { ret void }
+ define void @bne_reg_imm_swapped() { ret void }
+ declare void @callee()
+...
+---
+name: beq_reg_imm
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: beq_reg_imm
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: BEQ $x11, $x10, %bb.1
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: PseudoRET
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x10
+ $x11 = ADDI $x0, 7
+ BEQ $x11, killed $x10, %bb.1
+ PseudoBR %bb.2
+ bb.1:
+ successors: %bb.2
+ $x10 = ADDI $x0, 7
+ PseudoRET implicit $x10
+ bb.2:
+ PseudoRET
+...
+
+
+---
+name: bne_reg_imm
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: bne_reg_imm
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = QC_LI 9
+ ; CHECK-NEXT: BNE $x10, $x11, %bb.2
+ ; CHECK-NEXT: PseudoBR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: PseudoRET
+ bb.0:
+ successors: %bb.2, %bb.1
+ liveins: $x10
+ $x11 = QC_LI 9
+ BNE killed $x10, $x11, %bb.2
+ PseudoBR %bb.1
+ bb.1:
+ $x10 = ADDI $x0, 9
+ PseudoRET implicit $x10
+ bb.2:
+ PseudoRET
+...
+
+
+---
+name: clobber_const
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: clobber_const
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x11
+ ; CHECK-NEXT: BEQ $x8, $x11, %bb.1
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $x8 = ADDI $x0, 7
+ ; CHECK-NEXT: PseudoRET implicit $x8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x8
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x8
+ $x11 = ADDI $x0, 7
+ PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x11
+ BEQ $x8, $x11, %bb.1
+ PseudoBR %bb.2
+ bb.1:
+ $x8 = ADDI $x0, 7
+ PseudoRET implicit $x8
+ bb.2:
+ liveins: $x8
+ PseudoRET implicit $x8
+...
+
+
+---
+name: clobber_target
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: clobber_target
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: BEQ $x10, $x11, %bb.1
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x10 = ADDI $x10, 1
+ ; CHECK-NEXT: $x10 = ADDI $x0, 7
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x10
+ $x11 = ADDI $x0, 7
+ BEQ $x10, $x11, %bb.1
+ PseudoBR %bb.2
+ bb.1:
+ liveins: $x10
+ $x10 = ADDI $x10, 1
+ $x10 = ADDI $x0, 7
+ PseudoRET implicit $x10
+ bb.2:
+ liveins: $x10
+ PseudoRET implicit $x10
+...
+
+
+---
+name: inequality_edge
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: inequality_edge
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: BEQ $x10, $x11, %bb.2
+ ; CHECK-NEXT: PseudoBR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $x10 = ADDI $x0, 7
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.0:
+ successors: %bb.2, %bb.1
+ liveins: $x10
+ $x11 = ADDI $x0, 7
+ BEQ $x10, $x11, %bb.2
+ PseudoBR %bb.1
+ bb.1:
+ $x10 = ADDI $x0, 7
+ PseudoRET implicit $x10
+ bb.2:
+ liveins: $x10
+ PseudoRET implicit $x10
+...
+
+
+---
+name: beq_x0_is_zero
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: beq_x0_is_zero
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x0 = ADDI $x0, 7
+ ; CHECK-NEXT: BEQ $x0, $x10, %bb.1
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $x10 = ADDI $x0, 7
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: PseudoRET
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x10
+ $x0 = ADDI $x0, 7
+ BEQ $x0, $x10, %bb.1
+ PseudoBR %bb.2
+ bb.1:
+ $x10 = ADDI $x0, 7
+ PseudoRET implicit $x10
+ bb.2:
+ PseudoRET
+...
+
+# The formal ADDI definition cannot change x0's architectural zero value.
----------------
arichardson wrote:
This comment seems a bit pointless
https://github.com/llvm/llvm-project/pull/227673
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