[llvm] [AMDGPU][GISel] Match constrained shifts across regbank copies (PR #212097)
Anshil Gandhi via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 13:57:10 PDT 2026
https://github.com/gandhi56 updated https://github.com/llvm/llvm-project/pull/212097
>From d216563b2eb137fec23bdff3cec500806b867f02 Mon Sep 17 00:00:00 2001
From: Anshil Gandhi <Anshil.Gandhi at amd.com>
Date: Sun, 26 Jul 2026 02:23:50 -0500
Subject: [PATCH] [AMDGPU][GISel] Match constrained shifts across register bank
copies
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 10 +-
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 25 +-
.../test/CodeGen/AMDGPU/GlobalISel/add_shl.ll | 3 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 46 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 5297 ++++++++---------
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 5042 +++++++---------
.../inst-select-shift-amount-mask.mir | 316 +
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 48 +-
.../regbanklegalize-fadd-v2-fneg-lo.ll | 48 +
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll | 36 +-
llvm/test/CodeGen/AMDGPU/constrained-shift.ll | 22 +-
11 files changed, 5067 insertions(+), 5826 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 831f3e3e44816..38467a4e9a833 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -6653,16 +6653,18 @@ bool AMDGPUInstructionSelector::isUnneededShiftMask(const MachineInstr &MI,
unsigned ShAmtBits) const {
assert(MI.getOpcode() == TargetOpcode::G_AND);
- std::optional<APInt> RHS =
- getIConstantVRegVal(MI.getOperand(2).getReg(), *MRI);
+ // The mask constant is an SGPR G_CONSTANT copied to VGPR; the matcher looks
+ // through that COPY, so look through it here too.
+ std::optional<ValueAndVReg> RHS =
+ getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), *MRI);
if (!RHS)
return false;
- if (RHS->countr_one() >= ShAmtBits)
+ if (RHS->Value.countr_one() >= ShAmtBits)
return true;
const APInt &LHSKnownZeros = VT->getKnownZeroes(MI.getOperand(1).getReg());
- return (LHSKnownZeros | *RHS).countr_one() >= ShAmtBits;
+ return (LHSKnownZeros | RHS->Value).countr_one() >= ShAmtBits;
}
InstructionSelector::ComplexRendererFns
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 434ad35f73499..2bf7b34c9b422 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -295,40 +295,53 @@ def AMDGPUmul_i24_oneuse : HasOneUseBinOp<AMDGPUmul_i24>;
// Constrained shift PatFrags.
+// G_CONSTANT is assigned the SGPR bank, so a VGPR G_AND reads the mask through
+// a COPY. An SGPR G_AND feeding a VGPR shift likewise has a COPY on the amount.
+// GIIgnoreCopies looks through those copies; the pattern shape is unchanged.
+let GIIgnoreCopies = 1 in {
+
def csh_mask_16 : PatFrag<(ops node:$src0), (and node:$src0, imm),
- [{ return isUnneededShiftMask(N, 4); }]> {
+ [{ return isUnneededShiftMask(N, 4); }]>, GISelFlags {
let GISelPredicateCode = [{ return isUnneededShiftMask(MI, 4); }];
}
def csh_mask_32 : PatFrag<(ops node:$src0), (and node:$src0, imm),
- [{ return isUnneededShiftMask(N, 5); }]> {
+ [{ return isUnneededShiftMask(N, 5); }]>, GISelFlags {
let GISelPredicateCode = [{ return isUnneededShiftMask(MI, 5); }];
}
def csh_mask_64 : PatFrag<(ops node:$src0), (and node:$src0, imm),
- [{ return isUnneededShiftMask(N, 6); }]> {
+ [{ return isUnneededShiftMask(N, 6); }]>, GISelFlags {
let GISelPredicateCode = [{ return isUnneededShiftMask(MI, 6); }];
}
+} // End GIIgnoreCopies = 1
+
foreach width = [16, 32, 64] in {
defvar csh_mask = !cast<SDPatternOperator>("csh_mask_"#width);
def cshl_#width : PatFrags<(ops node:$src0, node:$src1),
- [(shl node:$src0, node:$src1), (shl node:$src0, (csh_mask node:$src1))]>;
+ [(shl node:$src0, node:$src1), (shl node:$src0, (csh_mask node:$src1))]>, GISelFlags {
+ let GIIgnoreCopies = 1;
+ }
defvar cshl = !cast<SDPatternOperator>("cshl_"#width);
def cshl_#width#_oneuse : HasOneUseBinOp<cshl>;
def clshl_rev_#width : PatFrag <(ops node:$src0, node:$src1),
(cshl $src1, $src0)>;
def csrl_#width : PatFrags<(ops node:$src0, node:$src1),
- [(srl node:$src0, node:$src1), (srl node:$src0, (csh_mask node:$src1))]>;
+ [(srl node:$src0, node:$src1), (srl node:$src0, (csh_mask node:$src1))]>, GISelFlags {
+ let GIIgnoreCopies = 1;
+ }
defvar csrl = !cast<SDPatternOperator>("csrl_"#width);
def csrl_#width#_oneuse : HasOneUseBinOp<csrl>;
def clshr_rev_#width : PatFrag <(ops node:$src0, node:$src1),
(csrl $src1, $src0)>;
def csra_#width : PatFrags<(ops node:$src0, node:$src1),
- [(sra node:$src0, node:$src1), (sra node:$src0, (csh_mask node:$src1))]>;
+ [(sra node:$src0, node:$src1), (sra node:$src0, (csh_mask node:$src1))]>, GISelFlags {
+ let GIIgnoreCopies = 1;
+ }
defvar csra = !cast<SDPatternOperator>("csra_"#width);
def csra_#width#_oneuse : HasOneUseBinOp<csra>;
def cashr_rev_#width : PatFrag <(ops node:$src0, node:$src1),
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
index 749b7681811de..04c55a72af7cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
@@ -45,8 +45,7 @@ define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
;
; GFX10-LABEL: add_shl_vgpr_c:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_i32 s2, s2, s3
-; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s2
+; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0
; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = shl i32 %x, %c
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 2b6e3b5b692db..32e9923d6f857 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -10,7 +10,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_ashr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -18,19 +17,18 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX8-LABEL: v_ashr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ashr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -38,7 +36,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX11-TRUE16-LABEL: v_ashr_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -46,7 +43,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX11-FAKE16-LABEL: v_ashr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -152,7 +148,6 @@ define i24 @v_ashr_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_ashr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -160,7 +155,6 @@ define i24 @v_ashr_i24(i24 %value, i24 %amount) {
; GFX10PLUS-LABEL: v_ashr_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
@@ -617,7 +611,6 @@ define i16 @v_ashr_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_ashr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -731,7 +724,6 @@ define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) {
define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: ashr_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -768,7 +760,6 @@ define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: ashr_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -809,7 +800,6 @@ define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_bfe_i32 v3, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v1, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -939,7 +929,6 @@ define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_sext_i32_i16 s1, s0
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100010
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1
; GFX6-NEXT: v_ashr_i32_e32 v0, s1, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -977,7 +966,6 @@ define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s1, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1024,18 +1012,16 @@ define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6-LABEL: v_ashr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v2
-; GFX6-NEXT: v_bfe_i32 v5, v0, 0, 16
+; GFX6-NEXT: v_bfe_i32 v4, v0, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v4, v2, v4
; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v4, v4, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16
+; GFX6-NEXT: v_bfe_i32 v2, v1, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, v3, v2
; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 16, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v3, v1
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, v2, v5
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v4
@@ -1189,26 +1175,23 @@ define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-LABEL: v_ashr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v4
-; GFX6-NEXT: v_bfe_i32 v9, v0, 0, 16
+; GFX6-NEXT: v_bfe_i32 v8, v0, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v8, v4, v8
; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v8, v8, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX6-NEXT: v_bfe_i32 v9, v1, 0, 16
+; GFX6-NEXT: v_bfe_i32 v4, v1, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v4, v5, v4
; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v4, v4, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v5, v1
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; GFX6-NEXT: v_bfe_i32 v9, v2, 0, 16
+; GFX6-NEXT: v_bfe_i32 v5, v2, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, v6, v5
; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v5, v5, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v2, v6, v2
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v7
-; GFX6-NEXT: v_bfe_i32 v9, v3, 0, 16
+; GFX6-NEXT: v_bfe_i32 v6, v3, 0, 16
+; GFX6-NEXT: v_ashrrev_i32_e32 v6, v7, v6
; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
; GFX6-NEXT: v_bfe_i32 v3, v3, 16, 16
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -1216,7 +1199,6 @@ define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX6-NEXT: v_ashrrev_i32_e32 v6, v6, v9
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index b95b313b80742..28ec8b5cead2d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshl_i7:
@@ -78,6 +78,46 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-NEXT: s_mul_i32 s4, s3, -7
+; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s3, s3, s4
+; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_i32 s3, s3, -7
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s2, 7
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_add_i32 s4, s2, -7
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_cmp_ge_u32 s2, 7
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_add_i32 s4, s2, -7
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
+; GFX11-NEXT: s_sub_i32 s3, 6, s2
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_lshr_b32 s1, s1, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
@@ -102,16 +142,16 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_add_i32 s4, s2, -7
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
+; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_sub_i32 s3, 6, s2
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_and_b32 s2, s3, 0x7f
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
@@ -138,6 +178,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_cselect_b32 s2, s4, s2
; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
; GFX10-NEXT: s_sub_i32 s3, 6, s2
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
@@ -145,47 +186,6 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i7:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-NEXT: s_mul_i32 s4, s3, -7
-; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s4
-; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_i32 s3, s3, -7
-; GFX11-NEXT: s_add_i32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s2, 7
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_add_i32 s4, s2, -7
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_ge_u32 s2, 7
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_add_i32 s4, s2, -7
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX11-NEXT: s_sub_i32 s3, 6, s2
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX11-NEXT: s_lshl_b32 s0, s0, s2
-; GFX11-NEXT: s_lshr_b32 s1, s1, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
ret i7 %result
}
@@ -215,10 +215,8 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -247,13 +245,47 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX11-NEXT: v_and_b16 v0.h, 0x7f, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: s_mul_i32 s1, s0, -7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, -7, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u16 v1.l, 6, v2.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -283,7 +315,6 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -313,47 +344,6 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i7:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x7f, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-TRUE16-NEXT: s_mul_i32 s1, s0, -7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_hi_u32 v5, v2, s0
-; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_nc_u16 v1.l, 6, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0x7f, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7f, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i7:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -419,9 +409,21 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_and_b32 s3, s2, 7
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_and_b32 s3, s2, 7
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s2
@@ -429,29 +431,17 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_and_b32 s3, s2, 7
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
+; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_and_b32 s3, s2, 7
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 %amt)
ret i8 %result
}
@@ -481,6 +471,21 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-NEXT: v_xor_b16 v1.l, v2.l, -1
+; GFX11-NEXT: v_and_b16 v1.h, v2.l, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: v_and_b16 v1.l, v1.l, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -493,7 +498,6 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -506,23 +510,6 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX10-NEXT: v_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v1.l, v2.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v1.l, 7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -558,30 +545,30 @@ define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i8_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 4
; GFX9-NEXT: s_lshr_b32 s1, s1, 4
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 4
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 4
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i8_4:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_lshr_b32 s1, s1, 4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
ret i8 %result
}
@@ -604,6 +591,15 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i8_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -612,7 +608,6 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -621,17 +616,6 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 4, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i8_4:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i8_4:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -661,30 +645,30 @@ define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i8_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 5
+; GFX11-NEXT: s_lshr_b32 s1, s1, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 5
; GFX9-NEXT: s_lshr_b32 s1, s1, 3
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 5
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 3
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i8_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_lshr_b32 s1, s1, 3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
ret i8 %result
}
@@ -707,6 +691,15 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i8_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 5, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 3, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -715,7 +708,6 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -724,17 +716,6 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i8_5:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 5, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 3, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i8_5:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -797,10 +778,36 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_lshr_b32 s5, s2, 8
+; GFX11-NEXT: s_and_b32 s6, s2, 7
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, s6
+; GFX11-NEXT: s_and_b32 s6, s5, 7
+; GFX11-NEXT: s_lshr_b32 s4, s4, 1
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s5
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_lshl_b32 s3, s3, s6
+; GFX11-NEXT: s_lshr_b32 s4, s4, s5
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_or_b32 s2, s3, s4
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_and_b32 s1, s2, 0xff
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s4, s1, 8
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshr_b32 s5, s2, 8
; GFX9-NEXT: s_and_b32 s6, s2, 7
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
@@ -808,9 +815,10 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
+; GFX9-NEXT: s_and_b32 s2, s4, 0xff
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s1, s5, 7
-; GFX9-NEXT: s_and_b32 s2, s4, 0xff
+; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s1, s3, s1
; GFX9-NEXT: s_lshr_b32 s2, s2, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s5
@@ -821,15 +829,16 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
; GFX10-NEXT: s_lshr_b32 s5, s2, 8
-; GFX10-NEXT: s_and_b32 s6, s2, 7
; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_and_b32 s6, s2, 7
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_lshr_b32 s3, s0, 8
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s5, 7
; GFX10-NEXT: s_lshr_b32 s4, s4, 1
@@ -846,32 +855,6 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_v2i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s4, s1, 8
-; GFX11-NEXT: s_lshr_b32 s5, s2, 8
-; GFX11-NEXT: s_and_b32 s6, s2, 7
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-NEXT: s_and_b32 s6, s5, 7
-; GFX11-NEXT: s_lshr_b32 s4, s4, 1
-; GFX11-NEXT: s_and_not1_b32 s5, 7, s5
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
-; GFX11-NEXT: s_lshl_b32 s3, s3, s6
-; GFX11-NEXT: s_lshr_b32 s4, s4, s5
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_or_b32 s2, s3, s4
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_and_b32 s1, s2, 0xff
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%amt = bitcast i16 %amt.arg to <2 x i8>
@@ -931,6 +914,37 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v0
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: v_xor_b16 v2.h, v2.l, -1
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v3.l
+; GFX11-NEXT: v_xor_b16 v1.h, v4.l, -1
+; GFX11-NEXT: v_and_b16 v3.l, v4.l, 7
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
+; GFX11-NEXT: v_lshrrev_b16 v1.l, 1, v1.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: v_and_b16 v1.h, v1.h, 7
+; GFX11-NEXT: v_and_b16 v2.h, v2.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v3.l, v3.l, v5.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v0.h
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v2.h, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b16 v0.h, v3.l, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -956,7 +970,6 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -983,39 +996,6 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v2i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v0
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v2.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v1.h, v4.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v4.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, 1, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v1.h, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v2.h, 7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, v3.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v2.h, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_v2i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1151,6 +1131,55 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s5, s1, 8
+; GFX11-NEXT: s_and_b32 s8, s1, 0xff
+; GFX11-NEXT: s_lshr_b32 s6, s2, 8
+; GFX11-NEXT: s_lshr_b32 s8, s8, 1
+; GFX11-NEXT: s_and_not1_b32 s10, 7, s2
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_lshr_b32 s8, s8, s10
+; GFX11-NEXT: s_and_b32 s10, s6, 7
+; GFX11-NEXT: s_lshr_b32 s5, s5, 1
+; GFX11-NEXT: s_and_not1_b32 s6, 7, s6
+; GFX11-NEXT: s_lshl_b32 s3, s3, s10
+; GFX11-NEXT: s_lshr_b32 s5, s5, s6
+; GFX11-NEXT: s_and_b32 s9, s2, 7
+; GFX11-NEXT: s_or_b32 s3, s3, s5
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: s_lshr_b32 s7, s2, 24
+; GFX11-NEXT: s_lshl_b32 s9, s0, s9
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_lshr_b32 s4, s0, 24
+; GFX11-NEXT: s_or_b32 s6, s9, s8
+; GFX11-NEXT: s_and_b32 s8, s2, 7
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s5, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, s8
+; GFX11-NEXT: s_lshr_b32 s2, s5, s2
+; GFX11-NEXT: s_and_b32 s5, s7, 7
+; GFX11-NEXT: s_lshr_b32 s1, s1, 25
+; GFX11-NEXT: s_and_not1_b32 s7, 7, s7
+; GFX11-NEXT: s_lshl_b32 s4, s4, s5
+; GFX11-NEXT: s_lshr_b32 s1, s1, s7
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_and_b32 s2, s3, 0xff
+; GFX11-NEXT: s_or_b32 s1, s4, s1
+; GFX11-NEXT: s_and_b32 s3, s6, 0xff
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_or_b32 s0, s2, s0
+; GFX11-NEXT: s_lshl_b32 s1, s1, 24
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s11, s2, 7
@@ -1159,6 +1188,7 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshr_b32 s5, s0, 24
; GFX9-NEXT: s_lshl_b32 s0, s0, s11
; GFX9-NEXT: s_and_b32 s11, s1, 0xff
+; GFX9-NEXT: s_and_b32 s11, 0xffff, s11
; GFX9-NEXT: s_lshr_b32 s8, s2, 8
; GFX9-NEXT: s_lshr_b32 s9, s2, 16
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
@@ -1170,6 +1200,7 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_and_b32 s2, s8, 7
; GFX9-NEXT: s_lshl_b32 s2, s3, s2
; GFX9-NEXT: s_and_b32 s3, s6, 0xff
+; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshr_b32 s3, s3, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s8
; GFX9-NEXT: s_lshr_b32 s3, s3, s6
@@ -1178,6 +1209,7 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_and_b32 s3, s9, 7
; GFX9-NEXT: s_lshl_b32 s3, s4, s3
; GFX9-NEXT: s_and_b32 s4, s7, 0xff
+; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshr_b32 s4, s4, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s9
; GFX9-NEXT: s_lshr_b32 s4, s4, s6
@@ -1199,40 +1231,42 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshl_b32 s1, s1, 24
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v4i8:
; GFX10: ; %bb.0:
+; GFX10-NEXT: s_and_b32 s10, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
-; GFX10-NEXT: s_and_b32 s11, s1, 0xff
+; GFX10-NEXT: s_and_b32 s10, 0xffff, s10
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
; GFX10-NEXT: s_lshr_b32 s9, s2, 16
-; GFX10-NEXT: s_lshr_b32 s10, s2, 24
+; GFX10-NEXT: s_lshr_b32 s11, s2, 24
; GFX10-NEXT: s_and_b32 s12, s2, 7
-; GFX10-NEXT: s_lshr_b32 s11, s11, 1
+; GFX10-NEXT: s_lshr_b32 s10, s10, 1
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_lshr_b32 s2, s11, s2
-; GFX10-NEXT: s_and_b32 s11, s8, 7
-; GFX10-NEXT: s_lshr_b32 s6, s6, 1
-; GFX10-NEXT: s_andn2_b32 s8, 7, s8
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshr_b32 s5, s0, 24
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s12
-; GFX10-NEXT: s_lshl_b32 s3, s3, s11
-; GFX10-NEXT: s_lshr_b32 s6, s6, s8
+; GFX10-NEXT: s_lshr_b32 s2, s10, s2
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_or_b32 s2, s3, s6
-; GFX10-NEXT: s_and_b32 s3, s7, 0xff
+; GFX10-NEXT: s_and_b32 s2, 0xffff, s6
+; GFX10-NEXT: s_lshr_b32 s7, s1, 16
+; GFX10-NEXT: s_and_b32 s6, s8, 7
+; GFX10-NEXT: s_lshr_b32 s2, s2, 1
+; GFX10-NEXT: s_andn2_b32 s8, 7, s8
+; GFX10-NEXT: s_lshl_b32 s3, s3, s6
+; GFX10-NEXT: s_lshr_b32 s2, s2, s8
+; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: s_or_b32 s2, s3, s2
+; GFX10-NEXT: s_and_b32 s3, 0xffff, s6
; GFX10-NEXT: s_and_b32 s6, s9, 7
; GFX10-NEXT: s_lshr_b32 s3, s3, 1
; GFX10-NEXT: s_andn2_b32 s7, 7, s9
; GFX10-NEXT: s_lshl_b32 s4, s4, s6
; GFX10-NEXT: s_lshr_b32 s3, s3, s7
-; GFX10-NEXT: s_and_b32 s6, s10, 7
+; GFX10-NEXT: s_and_b32 s6, s11, 7
; GFX10-NEXT: s_lshr_b32 s1, s1, 25
-; GFX10-NEXT: s_andn2_b32 s7, 7, s10
+; GFX10-NEXT: s_andn2_b32 s7, 7, s11
; GFX10-NEXT: s_lshl_b32 s5, s5, s6
; GFX10-NEXT: s_lshr_b32 s1, s1, s7
; GFX10-NEXT: s_or_b32 s3, s4, s3
@@ -1248,106 +1282,6 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX10-NEXT: s_lshl_b32 s1, s1, 24
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshl_v4i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s1, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s2, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s8, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s10, 7, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s8, s10
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s6, 7
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s6, 7, s6
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, s10
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, s6
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s2, 7
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s3, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s2, 24
-; GFX11-TRUE16-NEXT: s_lshl_b32 s9, s0, s9
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 24
-; GFX11-TRUE16-NEXT: s_or_b32 s6, s9, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s2, 7
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 7, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s5, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s7, 7
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 25
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s7, 7, s7
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, s7
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s4, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: s_fshl_v4i8:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s1, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s11, s1, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s2, 24
-; GFX11-FAKE16-NEXT: s_and_b32 s12, s2, 7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s11, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s2, 7, s2
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s11, s2
-; GFX11-FAKE16-NEXT: s_and_b32 s11, s8, 7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s6, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s8, 7, s8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s0, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s0, 24
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s1, 16
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, s11
-; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s6, s8
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s6
-; GFX11-FAKE16-NEXT: s_and_b32 s3, s7, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s9, 7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s7, 7, s9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, s6
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s10, 7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, 25
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s7, 7, s10
-; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, s6
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, s7
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s5, s1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s3, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%amt = bitcast i32 %amt.arg to <4 x i8>
@@ -1454,6 +1388,58 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 24, v2
+; GFX11-NEXT: v_and_b16 v5.h, 0xff, v1.h
+; GFX11-NEXT: v_and_b16 v4.l, 0xff, v4.l
+; GFX11-NEXT: v_xor_b16 v4.h, v5.l, -1
+; GFX11-NEXT: v_and_b16 v5.l, v5.l, 7
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v0
+; GFX11-NEXT: v_and_b16 v3.l, v2.l, 7
+; GFX11-NEXT: v_lshrrev_b16 v4.l, 1, v4.l
+; GFX11-NEXT: v_and_b16 v4.h, v4.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v5.l, v5.l, v6.l
+; GFX11-NEXT: v_xor_b16 v6.l, v2.h, -1
+; GFX11-NEXT: v_and_b16 v3.h, 0xff, v1.l
+; GFX11-NEXT: v_xor_b16 v2.l, v2.l, -1
+; GFX11-NEXT: v_lshrrev_b16 v4.l, v4.h, v4.l
+; GFX11-NEXT: v_xor_b16 v4.h, v8.l, -1
+; GFX11-NEXT: v_and_b16 v2.h, v2.h, 7
+; GFX11-NEXT: v_lshrrev_b16 v5.h, 1, v5.h
+; GFX11-NEXT: v_and_b16 v6.l, v6.l, 7
+; GFX11-NEXT: v_and_b16 v6.h, v8.l, 7
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 25, v1
+; GFX11-NEXT: v_and_b16 v1.l, v4.h, 7
+; GFX11-NEXT: v_lshrrev_b16 v3.h, 1, v3.h
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
+; GFX11-NEXT: v_or_b16 v4.l, v5.l, v4.l
+; GFX11-NEXT: v_lshlrev_b16 v0.h, v2.h, v0.h
+; GFX11-NEXT: v_lshrrev_b16 v1.h, v6.l, v5.h
+; GFX11-NEXT: v_lshlrev_b16 v2.h, v6.h, v7.l
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v1.l, v8.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v3.l, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v2.l, v2.l, v3.h
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-NEXT: v_or_b16 v4.l, v0.h, v1.h
+; GFX11-NEXT: v_or_b16 v1.l, v2.h, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1502,7 +1488,6 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1554,60 +1539,6 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v4i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 24, v2
-; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v4.h, v5.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, v5.l, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v0
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v2.l, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.l, 1, v4.l
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, v4.h, 7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, v5.l, v6.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v6.l, v2.h, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v2.l, v2.l, -1
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.l, v4.h, v4.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v4.h, v8.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v2.h, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v5.h, 1, v5.h
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, v6.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v6.h, v8.l, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 25, v1
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v4.h, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.h, 1, v3.h
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 7
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v1.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v2.l, v3.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v0.h, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX11-TRUE16-NEXT: v_or3_b32 v0, v0, v2, v1
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_v4i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1672,74 +1603,77 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
}
define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) {
-; GFX6-LABEL: s_fshl_i24:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s3, v0
-; GFX6-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX6-NEXT: v_mul_hi_u32 v0, v0, s4
-; GFX6-NEXT: v_readfirstlane_b32 s4, v0
-; GFX6-NEXT: s_add_i32 s3, s3, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s3
-; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s3, v0
-; GFX6-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX6-NEXT: s_add_i32 s2, s2, s3
-; GFX6-NEXT: s_cmp_ge_u32 s2, 24
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_sub_i32 s4, s2, 24
-; GFX6-NEXT: s_cmp_lg_u32 s3, 0
-; GFX6-NEXT: s_cselect_b32 s2, s4, s2
-; GFX6-NEXT: s_cmp_ge_u32 s2, 24
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_sub_i32 s4, s2, 24
-; GFX6-NEXT: s_cmp_lg_u32 s3, 0
-; GFX6-NEXT: s_cselect_b32 s2, s4, s2
-; GFX6-NEXT: s_sub_i32 s3, 23, s2
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001
-; GFX6-NEXT: s_lshl_b32 s0, s0, s2
-; GFX6-NEXT: s_lshr_b32 s1, s1, s3
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i24:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4
-; GFX8-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8-NEXT: s_add_i32 s3, s3, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX8-NEXT: s_add_i32 s2, s2, s3
-; GFX8-NEXT: s_cmp_ge_u32 s2, 24
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_sub_i32 s4, s2, 24
-; GFX8-NEXT: s_cmp_lg_u32 s3, 0
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_cmp_ge_u32 s2, 24
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_sub_i32 s4, s2, 24
-; GFX8-NEXT: s_cmp_lg_u32 s3, 0
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_sub_i32 s3, 23, s2
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001
-; GFX8-NEXT: s_lshl_b32 s0, s0, s2
-; GFX8-NEXT: s_lshr_b32 s1, s1, s3
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i24:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: s_and_b32 s2, s2, 0xffffff
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s3, v0
+; GCN-NEXT: s_mul_i32 s4, s3, 0xffffffe8
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s4
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: s_add_i32 s3, s3, s4
+; GCN-NEXT: v_mov_b32_e32 v0, s3
+; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
+; GCN-NEXT: v_readfirstlane_b32 s3, v0
+; GCN-NEXT: s_mulk_i32 s3, 0xffe8
+; GCN-NEXT: s_add_i32 s2, s2, s3
+; GCN-NEXT: s_cmp_ge_u32 s2, 24
+; GCN-NEXT: s_cselect_b32 s3, 1, 0
+; GCN-NEXT: s_sub_i32 s4, s2, 24
+; GCN-NEXT: s_cmp_lg_u32 s3, 0
+; GCN-NEXT: s_cselect_b32 s2, s4, s2
+; GCN-NEXT: s_cmp_ge_u32 s2, 24
+; GCN-NEXT: s_cselect_b32 s3, 1, 0
+; GCN-NEXT: s_sub_i32 s4, s2, 24
+; GCN-NEXT: s_cmp_lg_u32 s3, 0
+; GCN-NEXT: s_cselect_b32 s2, s4, s2
+; GCN-NEXT: s_sub_i32 s3, 23, s2
+; GCN-NEXT: s_bfe_u32 s1, s1, 0x170001
+; GCN-NEXT: s_lshl_b32 s0, s0, s2
+; GCN-NEXT: s_lshr_b32 s1, s1, s3
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: s_and_b32 s2, s2, 0xffffff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-NEXT: s_mul_i32 s4, s3, 0xffffffe8
+; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s3, s3, s4
+; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mulk_i32 s3, 0xffe8
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x170001
+; GFX11-NEXT: s_sub_i32 s3, 23, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_lshr_b32 s1, s1, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -1770,7 +1704,6 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX9-NEXT: s_lshr_b32 s1, s1, s3
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -1801,44 +1734,6 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s4
-; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX11-NEXT: s_add_i32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_sub_i32 s4, s2, 24
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_sub_i32 s4, s2, 24
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_bfe_u32 s1, s1, 0x170001
-; GFX11-NEXT: s_sub_i32 s3, 23, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, s2
-; GFX11-NEXT: s_lshr_b32 s1, s1, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
ret i24 %result
}
@@ -1862,17 +1757,15 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -1894,20 +1787,51 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v4
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, 0xffffffe8, v5, v[2:3]
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, v3, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, v2, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1936,7 +1860,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1964,43 +1887,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 23
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
-; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, 0xffffffe8, v5, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v3
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, v2, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
ret i24 %result
}
@@ -2248,6 +2134,114 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s1, s2, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v2i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: s_lshr_b32 s6, s0, 8
+; GFX11-NEXT: s_and_b32 s8, s0, 0xff
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: s_and_b32 s10, s2, 0xff
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s9, s1, 8
+; GFX11-NEXT: s_or_b32 s6, s8, s6
+; GFX11-NEXT: s_lshr_b32 s8, s2, 8
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_and_b32 s8, s8, 0xff
+; GFX11-NEXT: s_lshr_b32 s7, s0, 24
+; GFX11-NEXT: s_lshl_b32 s8, s8, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: s_or_b32 s8, s10, s8
+; GFX11-NEXT: s_lshr_b32 s10, s4, 8
+; GFX11-NEXT: s_lshr_b32 s11, s3, 8
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_and_b32 s10, s10, 0xff
+; GFX11-NEXT: s_or_b32 s1, s7, s1
+; GFX11-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-NEXT: s_lshr_b32 s9, s2, 24
+; GFX11-NEXT: v_readfirstlane_b32 s13, v0
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_and_b32 s12, s4, 0xff
+; GFX11-NEXT: s_lshl_b32 s10, s10, 8
+; GFX11-NEXT: s_or_b32 s3, s9, s3
+; GFX11-NEXT: s_and_b32 s9, s11, 0xff
+; GFX11-NEXT: s_lshr_b32 s11, s4, 24
+; GFX11-NEXT: s_or_b32 s10, s12, s10
+; GFX11-NEXT: s_lshr_b32 s4, s4, 16
+; GFX11-NEXT: s_mul_i32 s12, s13, 0xffffffe8
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_mul_hi_u32 s12, s13, s12
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s10, s4
+; GFX11-NEXT: s_add_i32 s13, s13, s12
+; GFX11-NEXT: s_lshr_b32 s14, s5, 8
+; GFX11-NEXT: s_mul_hi_u32 s10, s4, s13
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_mulk_i32 s10, 0xffe8
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshl_b32 s5, s5, 8
+; GFX11-NEXT: s_add_i32 s4, s4, s10
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_or_b32 s5, s11, s5
+; GFX11-NEXT: s_and_b32 s10, s14, 0xff
+; GFX11-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s6, s0
+; GFX11-NEXT: s_cselect_b32 s11, 1, 0
+; GFX11-NEXT: s_sub_i32 s12, s4, 24
+; GFX11-NEXT: s_cmp_lg_u32 s11, 0
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s8, s2
+; GFX11-NEXT: s_cselect_b32 s4, s12, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s10
+; GFX11-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s9
+; GFX11-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-NEXT: s_sub_i32 s8, s4, 24
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s7
+; GFX11-NEXT: s_cselect_b32 s4, s8, s4
+; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_sub_i32 s6, 23, s4
+; GFX11-NEXT: s_lshl_b32 s0, s0, s4
+; GFX11-NEXT: s_mul_hi_u32 s4, s5, s13
+; GFX11-NEXT: s_lshr_b32 s2, s2, s6
+; GFX11-NEXT: s_mulk_i32 s4, 0xffe8
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_add_i32 s5, s5, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s5, 24
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s5
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_sub_i32 s5, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s2, s5, s2
+; GFX11-NEXT: s_lshr_b32 s3, s3, 1
+; GFX11-NEXT: s_sub_i32 s4, 23, s2
+; GFX11-NEXT: s_lshl_b32 s1, s1, s2
+; GFX11-NEXT: s_lshr_b32 s2, s3, s4
+; GFX11-NEXT: s_and_b32 s3, s0, 0xff
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_bfe_u32 s2, s0, 0x80008
+; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_and_b32 s3, s1, 0xff
+; GFX11-NEXT: s_or_b32 s0, s2, s0
+; GFX11-NEXT: s_lshl_b32 s2, s3, 24
+; GFX11-NEXT: s_bfe_u32 s3, s1, 0x80010
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s6, s0, 8
@@ -2256,16 +2250,18 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s8, s0, 24
; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
-; GFX9-NEXT: s_lshr_b32 s9, s1, 8
; GFX9-NEXT: s_or_b32 s0, s0, s6
; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: s_lshr_b32 s9, s1, 8
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: s_lshl_b32 s1, s1, 8
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_or_b32 s0, s0, s6
-; GFX9-NEXT: s_or_b32 s1, s8, s1
+; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: s_or_b32 s1, s8, s1
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
; GFX9-NEXT: s_or_b32 s1, s1, s6
@@ -2275,39 +2271,43 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s8, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
-; GFX9-NEXT: s_lshr_b32 s9, s3, 8
; GFX9-NEXT: s_or_b32 s2, s2, s6
; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s3, s3, 0xff
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: s_lshr_b32 s9, s3, 8
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: s_lshl_b32 s3, s3, 8
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: s_and_b32 s3, s3, 0xff
; GFX9-NEXT: s_or_b32 s2, s2, s6
-; GFX9-NEXT: s_or_b32 s3, s8, s3
+; GFX9-NEXT: s_lshl_b32 s3, s3, 8
; GFX9-NEXT: s_and_b32 s6, s9, 0xff
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_or_b32 s3, s8, s3
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s3, s3, s6
; GFX9-NEXT: s_lshr_b32 s6, s4, 8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s6, s6, 0xff
; GFX9-NEXT: s_lshr_b32 s7, s4, 16
; GFX9-NEXT: s_lshr_b32 s8, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: s_lshr_b32 s9, s5, 8
; GFX9-NEXT: s_or_b32 s4, s4, s6
; GFX9-NEXT: s_and_b32 s6, s7, 0xff
-; GFX9-NEXT: s_and_b32 s5, s5, 0xff
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: s_lshr_b32 s9, s5, 8
; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: s_lshl_b32 s5, s5, 8
+; GFX9-NEXT: s_and_b32 s5, s5, 0xff
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_or_b32 s4, s4, s6
-; GFX9-NEXT: s_or_b32 s5, s8, s5
+; GFX9-NEXT: s_lshl_b32 s5, s5, 8
; GFX9-NEXT: s_and_b32 s6, s9, 0xff
+; GFX9-NEXT: s_or_b32 s5, s8, s5
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
; GFX9-NEXT: s_or_b32 s5, s5, s6
@@ -2366,26 +2366,27 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_or_b32 s1, s2, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
-; GFX10-NEXT: s_lshr_b32 s9, s1, 8
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: s_lshr_b32 s9, s1, 8
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_lshl_b32 s6, s6, 16
-; GFX10-NEXT: s_or_b32 s1, s8, s1
+; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_and_b32 s7, s9, 0xff
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: s_or_b32 s1, s8, s1
+; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_lshr_b32 s6, s2, 8
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -2396,70 +2397,74 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_lshr_b32 s8, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: s_lshr_b32 s9, s3, 8
; GFX10-NEXT: s_or_b32 s2, s2, s6
; GFX10-NEXT: s_and_b32 s6, s7, 0xff
-; GFX10-NEXT: s_lshr_b32 s9, s3, 8
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
+; GFX10-NEXT: s_and_b32 s7, s9, 0xff
+; GFX10-NEXT: s_or_b32 s3, s8, s3
+; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_or_b32 s2, s2, s6
; GFX10-NEXT: s_lshr_b32 s6, s4, 8
-; GFX10-NEXT: s_or_b32 s3, s8, s3
-; GFX10-NEXT: s_and_b32 s7, s9, 0xff
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
-; GFX10-NEXT: s_and_b32 s8, s4, 0xff
-; GFX10-NEXT: s_lshl_b32 s6, s6, 8
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s3, s3, s7
; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_or_b32 s6, s8, s6
-; GFX10-NEXT: v_readfirstlane_b32 s8, v0
-; GFX10-NEXT: s_and_b32 s7, s7, 0xff
-; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX10-NEXT: s_lshl_b32 s7, s7, 16
+; GFX10-NEXT: s_lshr_b32 s8, s4, 24
+; GFX10-NEXT: s_and_b32 s4, s4, 0xff
+; GFX10-NEXT: s_lshl_b32 s6, s6, 8
; GFX10-NEXT: s_lshr_b32 s9, s5, 8
-; GFX10-NEXT: s_or_b32 s6, s6, s7
-; GFX10-NEXT: s_mul_i32 s7, s8, 0xffffffe8
+; GFX10-NEXT: s_or_b32 s4, s4, s6
+; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: v_readfirstlane_b32 s7, v0
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
-; GFX10-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX10-NEXT: s_lshr_b32 s4, s4, 24
-; GFX10-NEXT: s_add_i32 s8, s8, s7
+; GFX10-NEXT: s_or_b32 s4, s4, s6
+; GFX10-NEXT: s_mul_i32 s6, s7, 0xffffffe8
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_mul_hi_u32 s7, s6, s8
-; GFX10-NEXT: s_or_b32 s4, s4, s5
-; GFX10-NEXT: s_and_b32 s5, s9, 0xff
-; GFX10-NEXT: s_mulk_i32 s7, 0xffe8
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: s_lshl_b32 s5, s5, 16
-; GFX10-NEXT: s_add_i32 s6, s6, s7
-; GFX10-NEXT: s_or_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_ge_u32 s6, 24
-; GFX10-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-NEXT: s_sub_i32 s7, s6, 24
-; GFX10-NEXT: s_cmp_lg_u32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s5, s7, s6
-; GFX10-NEXT: s_cmp_ge_u32 s5, 24
+; GFX10-NEXT: s_mul_hi_u32 s6, s7, s6
+; GFX10-NEXT: s_or_b32 s5, s8, s5
+; GFX10-NEXT: s_add_i32 s7, s7, s6
+; GFX10-NEXT: s_and_b32 s8, s9, 0xff
+; GFX10-NEXT: s_mul_hi_u32 s6, s4, s7
+; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX10-NEXT: s_mulk_i32 s6, 0xffe8
+; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX10-NEXT: s_lshl_b32 s8, s8, 16
+; GFX10-NEXT: s_add_i32 s4, s4, s6
+; GFX10-NEXT: s_or_b32 s5, s5, s8
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_cselect_b32 s6, 1, 0
+; GFX10-NEXT: s_sub_i32 s8, s4, 24
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
+; GFX10-NEXT: s_cselect_b32 s4, s8, s4
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
; GFX10-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-NEXT: s_sub_i32 s7, s5, 24
+; GFX10-NEXT: s_sub_i32 s8, s4, 24
; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s5, s7, s5
+; GFX10-NEXT: s_cselect_b32 s4, s8, s4
; GFX10-NEXT: s_lshr_b32 s2, s2, 1
-; GFX10-NEXT: s_sub_i32 s6, 23, s5
-; GFX10-NEXT: s_lshl_b32 s0, s0, s5
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s8
+; GFX10-NEXT: s_sub_i32 s6, 23, s4
+; GFX10-NEXT: s_lshl_b32 s0, s0, s4
+; GFX10-NEXT: s_mul_hi_u32 s4, s5, s7
; GFX10-NEXT: s_lshr_b32 s2, s2, s6
-; GFX10-NEXT: s_mulk_i32 s5, 0xffe8
+; GFX10-NEXT: s_mulk_i32 s4, 0xffe8
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_add_i32 s5, s5, s4
+; GFX10-NEXT: s_cmp_ge_u32 s5, 24
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_sub_i32 s5, s4, 24
+; GFX10-NEXT: s_sub_i32 s4, s5, 24
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s2, s5, s4
+; GFX10-NEXT: s_cselect_b32 s2, s4, s5
; GFX10-NEXT: s_cmp_ge_u32 s2, 24
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_sub_i32 s5, s2, 24
@@ -2485,135 +2490,27 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_or_b32 s0, s0, s2
; GFX10-NEXT: s_or_b32 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshl_v2i24:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s0, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s2, 0xff
-; GFX11-TRUE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s1, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s6, s8, s6
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s2, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s8, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s0, 24
-; GFX11-TRUE16-NEXT: s_lshl_b32 s8, s8, 8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-TRUE16-NEXT: s_or_b32 s8, s10, s8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s4, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s3, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s10, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s7, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s9, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s2, 24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s4, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s10, s10, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s9, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s4, 24
-; GFX11-TRUE16-NEXT: s_or_b32 s10, s12, s10
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: s_mul_i32 s12, s13, 0xffffffe8
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s12, s13, s12
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, s12
-; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s5, 8
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s10, s4, s13
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-TRUE16-NEXT: s_mulk_i32 s10, 0xffe8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, s10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s5, s11, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s14, 0xff
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s6, s0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s12, s4, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s11, 0
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s8, s2
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s12, s4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s5, s10
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s9
-; GFX11-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s8, s4, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s7
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s8, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-TRUE16-NEXT: s_sub_i32 s6, 23, s4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s4
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s4, s5, s13
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, s6
-; GFX11-TRUE16-NEXT: s_mulk_i32 s4, 0xffe8
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s5, 24
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s4, s5, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s5, s2, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 1
-; GFX11-TRUE16-NEXT: s_sub_i32 s4, 23, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_bfe_u32 s2, s0, 0x80008
-; GFX11-TRUE16-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s3, 24
-; GFX11-TRUE16-NEXT: s_bfe_u32 s3, s1, 0x80010
-; GFX11-TRUE16-NEXT: s_bfe_u32 s1, s1, 0x80008
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s3
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshl_v2i24:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s0, 8
-; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s0, 16
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s1, 8
+; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s6
; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s1, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s8, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_or_b32 s1, s8, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s2, 8
; GFX11-FAKE16-NEXT: s_and_b32 s1, 0xffff, s1
@@ -2624,73 +2521,77 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 24
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s3, 8
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s6
; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s3, 8
; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s8, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s6
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s4, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s8, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s9, 0xff
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s4, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s7
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-FAKE16-NEXT: s_or_b32 s6, s8, s6
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s7, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s4, 24
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 8
; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s6, s6, s7
-; GFX11-FAKE16-NEXT: s_mul_i32 s7, s8, 0xffffffe8
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s6
+; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-FAKE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s4, 24
-; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, s7
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s6
+; GFX11-FAKE16-NEXT: s_mul_i32 s6, s7, 0xffffffe8
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s7, s6, s8
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
-; GFX11-FAKE16-NEXT: s_and_b32 s5, s9, 0xff
-; GFX11-FAKE16-NEXT: s_mulk_i32 s7, 0xffe8
-; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, s7
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s6, 24
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s7, s6, 24
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s7, s6
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s7, s6
+; GFX11-FAKE16-NEXT: s_or_b32 s5, s8, s5
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, s6
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s4, s7
+; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX11-FAKE16-NEXT: s_mulk_i32 s6, 0xffe8
+; GFX11-FAKE16-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s6
+; GFX11-FAKE16-NEXT: s_or_b32 s5, s5, s8
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s7, s5, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, s4, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s7, s5
+; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s8, s4
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-FAKE16-NEXT: s_sub_i32 s6, 23, s5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s5
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s5, s4, s8
+; GFX11-FAKE16-NEXT: s_sub_i32 s6, 23, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s4, s5, s7
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s6
-; GFX11-FAKE16-NEXT: s_mulk_i32 s5, 0xffe8
+; GFX11-FAKE16-NEXT: s_mulk_i32 s4, 0xffe8
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s5
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s5, s4, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s4, s5, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s5, s4
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s4, s5
; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s2, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-FAKE16-NEXT: s_sub_i32 s5, s2, 24
@@ -2752,13 +2653,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v6
-; GFX6-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX6-NEXT: v_mul_lo_u32 v4, v8, v7
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v6
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v4
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v7
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2766,11 +2665,9 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -2801,13 +2698,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v6
-; GFX8-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_lo_u32 v4, v8, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v6
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v2, v7
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2815,14 +2710,60 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: v_bfe_u32 v2, v2, 1, 23
+; GFX11-NEXT: v_bfe_u32 v3, v3, 1, 23
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s0, v6
+; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
+; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
+; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, v4, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, v5, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2866,7 +2807,6 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2909,86 +2849,33 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v4, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
+ ret <2 x i24> %result
+}
+
+define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
+; GCN-LABEL: s_fshl_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: s_not_b32 s1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 1
+; GCN-NEXT: s_lshr_b32 s0, s0, 1
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: v_fshl_v2i24:
+; GFX11-LABEL: s_fshl_i32:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX11-NEXT: v_bfe_u32 v3, v3, 1, 23
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX11-NEXT: v_readfirstlane_b32 s0, v6
-; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
-; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
-; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; GFX11-NEXT: v_lshl_or_b32 v1, v1, v5, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
- %result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
- ret <2 x i24> %result
-}
-
-define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
-; GFX6-LABEL: s_fshl_i32:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: s_not_b32 s1, s2
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: s_not_b32 s1, s2
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
-;
+; GFX11-NEXT: s_not_b32 s2, s2
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
@@ -2999,7 +2886,6 @@ define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 1
@@ -3008,19 +2894,6 @@ define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshl_i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s2, s2
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshl_i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
@@ -3036,77 +2909,59 @@ define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
}
define amdgpu_ps i32 @s_fshl_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
-; GFX6-LABEL: s_fshl_i32_5:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 27
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i32_5:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 27
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i32_5:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 27
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i32_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 27
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i32_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 27
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i32_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 27
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i32_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 27
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5)
ret i32 %result
}
define amdgpu_ps i32 @s_fshl_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
-; GFX6-LABEL: s_fshl_i32_8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 24
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i32_8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 24
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i32_8:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 24
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i32_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i32_8:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 24
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i32_8:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 24
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i32_8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8)
ret i32 %result
}
@@ -3121,16 +2976,15 @@ define i32 @v_fshl_i32(i32 %lhs, i32 %rhs, i32 %amt) {
; GCN-NEXT: v_alignbit_b32 v0, v0, v1, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_fshl_i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v0, v1, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX11-LABEL: v_fshl_i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v1, v0, v1, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_not_b32_e32 v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-LABEL: v_fshl_i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3177,24 +3031,23 @@ define i32 @v_fshl_i32_8(i32 %lhs, i32 %rhs) {
}
define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
-; GFX6-LABEL: v_fshl_i32_ssv:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v1, s0, v1, 1
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
-; GFX6-NEXT: v_not_b32_e32 v0, v0
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v1, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshl_i32_ssv:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v1, s0, v1, 1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_not_b32_e32 v0, v0
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v1, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshl_i32_ssv:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 1
+; GCN-NEXT: s_lshr_b32 s0, s0, 1
+; GCN-NEXT: v_not_b32_e32 v0, v0
+; GCN-NEXT: v_alignbit_b32 v0, s0, v1, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i32_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v1, s0, s1, 1
+; GFX11-NEXT: v_not_b32_e32 v0, v0
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v1, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i32_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, s1
@@ -3203,7 +3056,6 @@ define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt)
; GFX9-NEXT: v_not_b32_e32 v0, v0
; GFX9-NEXT: v_alignbit_b32 v0, s0, v1, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i32_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v1, s0, s1, 1
@@ -3211,16 +3063,6 @@ define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt)
; GFX10-NEXT: s_lshr_b32 s0, s0, 1
; GFX10-NEXT: v_alignbit_b32 v0, s0, v1, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i32_ssv:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, s0, s1, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v1, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i32_ssv:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, s0, s1, 1
@@ -3235,24 +3077,24 @@ define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt)
}
define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt) {
-; GFX6-LABEL: v_fshl_i32_svs:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_not_b32 s1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshl_i32_svs:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshl_i32_svs:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_not_b32 s1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 1
+; GCN-NEXT: s_lshr_b32 s0, s0, 1
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i32_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_not_b32 s1, s1
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, 1
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i32_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_not_b32 s1, s1
@@ -3261,7 +3103,6 @@ define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i32_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, 1
@@ -3269,17 +3110,6 @@ define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
; GFX10-NEXT: s_not_b32 s1, s1
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i32_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s1, s1
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i32_svs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, 1
@@ -3294,26 +3124,25 @@ define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
}
define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
-; GFX6-LABEL: v_fshl_i32_vss:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: s_not_b32 s1, s2
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshl_i32_vss:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: s_not_b32 s1, s2
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshl_i32_vss:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: s_not_b32 s1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 1
+; GCN-NEXT: s_lshr_b32 s0, s0, 1
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i32_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_not_b32 s2, s2
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i32_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
@@ -3323,7 +3152,6 @@ define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i32_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 1
@@ -3331,17 +3159,6 @@ define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg
; GFX10-NEXT: s_not_b32 s1, s2
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i32_vss:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s2, s2
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i32_vss:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
@@ -3356,32 +3173,32 @@ define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg
}
define <2 x i32> @v_fshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
-; GFX6-LABEL: v_fshl_v2i32:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_alignbit_b32 v2, v0, v2, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_not_b32_e32 v4, v4
-; GFX6-NEXT: v_alignbit_b32 v0, v0, v2, v4
-; GFX6-NEXT: v_alignbit_b32 v2, v1, v3, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_not_b32_e32 v3, v5
-; GFX6-NEXT: v_alignbit_b32 v1, v1, v2, v3
-; GFX6-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_fshl_v2i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_alignbit_b32 v2, v0, v2, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_not_b32_e32 v4, v4
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v2, v4
-; GFX8-NEXT: v_alignbit_b32 v2, v1, v3, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_not_b32_e32 v3, v5
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, v3
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fshl_v2i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_alignbit_b32 v2, v0, v2, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GCN-NEXT: v_not_b32_e32 v4, v4
+; GCN-NEXT: v_alignbit_b32 v0, v0, v2, v4
+; GCN-NEXT: v_alignbit_b32 v2, v1, v3, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GCN-NEXT: v_not_b32_e32 v3, v5
+; GCN-NEXT: v_alignbit_b32 v1, v1, v2, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v2, v0, v2, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_not_b32_e32 v4, v4
+; GFX11-NEXT: v_alignbit_b32 v3, v1, v3, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_not_b32_e32 v5, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3394,7 +3211,6 @@ define <2 x i32> @v_fshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
; GFX9-NEXT: v_not_b32_e32 v3, v5
; GFX9-NEXT: v_alignbit_b32 v1, v1, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3407,21 +3223,6 @@ define <2 x i32> @v_fshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
; GFX10-NEXT: v_alignbit_b32 v0, v0, v2, v4
; GFX10-NEXT: v_alignbit_b32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v2i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v0, v2, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, v1, v3, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_v2i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3440,40 +3241,40 @@ define <2 x i32> @v_fshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
}
define <3 x i32> @v_fshl_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
-; GFX6-LABEL: v_fshl_v3i32:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_alignbit_b32 v3, v0, v3, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_not_b32_e32 v6, v6
-; GFX6-NEXT: v_alignbit_b32 v0, v0, v3, v6
-; GFX6-NEXT: v_alignbit_b32 v3, v1, v4, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_not_b32_e32 v4, v7
-; GFX6-NEXT: v_alignbit_b32 v1, v1, v3, v4
-; GFX6-NEXT: v_alignbit_b32 v3, v2, v5, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_not_b32_e32 v4, v8
-; GFX6-NEXT: v_alignbit_b32 v2, v2, v3, v4
-; GFX6-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_fshl_v3i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_alignbit_b32 v3, v0, v3, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_not_b32_e32 v6, v6
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, v6
-; GFX8-NEXT: v_alignbit_b32 v3, v1, v4, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_not_b32_e32 v4, v7
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v3, v4
-; GFX8-NEXT: v_alignbit_b32 v3, v2, v5, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_not_b32_e32 v4, v8
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v3, v4
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fshl_v3i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GCN-NEXT: v_not_b32_e32 v6, v6
+; GCN-NEXT: v_alignbit_b32 v0, v0, v3, v6
+; GCN-NEXT: v_alignbit_b32 v3, v1, v4, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GCN-NEXT: v_not_b32_e32 v4, v7
+; GCN-NEXT: v_alignbit_b32 v1, v1, v3, v4
+; GCN-NEXT: v_alignbit_b32 v3, v2, v5, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GCN-NEXT: v_not_b32_e32 v4, v8
+; GCN-NEXT: v_alignbit_b32 v2, v2, v3, v4
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v3i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v3, v0, v3, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_not_b32_e32 v6, v6
+; GFX11-NEXT: v_alignbit_b32 v4, v1, v4, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_not_b32_e32 v7, v7
+; GFX11-NEXT: v_alignbit_b32 v5, v2, v5, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_not_b32_e32 v8, v8
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3490,7 +3291,6 @@ define <3 x i32> @v_fshl_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
; GFX9-NEXT: v_not_b32_e32 v4, v8
; GFX9-NEXT: v_alignbit_b32 v2, v2, v3, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3507,25 +3307,6 @@ define <3 x i32> @v_fshl_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
; GFX10-NEXT: v_alignbit_b32 v1, v1, v4, v7
; GFX10-NEXT: v_alignbit_b32 v2, v2, v5, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v3i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, v0, v3, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v6
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v4, v1, v4, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v7
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v5, v2, v5, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v8
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_v3i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3548,48 +3329,48 @@ define <3 x i32> @v_fshl_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
}
define <4 x i32> @v_fshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
-; GFX6-LABEL: v_fshl_v4i32:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_alignbit_b32 v4, v0, v4, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_not_b32_e32 v8, v8
-; GFX6-NEXT: v_alignbit_b32 v0, v0, v4, v8
-; GFX6-NEXT: v_alignbit_b32 v4, v1, v5, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_not_b32_e32 v5, v9
-; GFX6-NEXT: v_alignbit_b32 v1, v1, v4, v5
-; GFX6-NEXT: v_alignbit_b32 v4, v2, v6, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_not_b32_e32 v5, v10
-; GFX6-NEXT: v_alignbit_b32 v2, v2, v4, v5
-; GFX6-NEXT: v_alignbit_b32 v4, v3, v7, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX6-NEXT: v_not_b32_e32 v5, v11
-; GFX6-NEXT: v_alignbit_b32 v3, v3, v4, v5
-; GFX6-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_fshl_v4i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_alignbit_b32 v4, v0, v4, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_not_b32_e32 v8, v8
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, v8
-; GFX8-NEXT: v_alignbit_b32 v4, v1, v5, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_not_b32_e32 v5, v9
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, v5
-; GFX8-NEXT: v_alignbit_b32 v4, v2, v6, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_not_b32_e32 v5, v10
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v4, v5
-; GFX8-NEXT: v_alignbit_b32 v4, v3, v7, 1
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX8-NEXT: v_not_b32_e32 v5, v11
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v4, v5
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fshl_v4i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GCN-NEXT: v_not_b32_e32 v8, v8
+; GCN-NEXT: v_alignbit_b32 v0, v0, v4, v8
+; GCN-NEXT: v_alignbit_b32 v4, v1, v5, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GCN-NEXT: v_not_b32_e32 v5, v9
+; GCN-NEXT: v_alignbit_b32 v1, v1, v4, v5
+; GCN-NEXT: v_alignbit_b32 v4, v2, v6, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GCN-NEXT: v_not_b32_e32 v5, v10
+; GCN-NEXT: v_alignbit_b32 v2, v2, v4, v5
+; GCN-NEXT: v_alignbit_b32 v4, v3, v7, 1
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 1, v3
+; GCN-NEXT: v_not_b32_e32 v5, v11
+; GCN-NEXT: v_alignbit_b32 v3, v3, v4, v5
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v4i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v4, v0, v4, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_not_b32_e32 v8, v8
+; GFX11-NEXT: v_alignbit_b32 v5, v1, v5, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_not_b32_e32 v9, v9
+; GFX11-NEXT: v_alignbit_b32 v6, v2, v6, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_not_b32_e32 v10, v10
+; GFX11-NEXT: v_alignbit_b32 v7, v3, v7, 1
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_not_b32_e32 v11, v11
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
+; GFX11-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3610,7 +3391,6 @@ define <4 x i32> @v_fshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
; GFX9-NEXT: v_not_b32_e32 v5, v11
; GFX9-NEXT: v_alignbit_b32 v3, v3, v4, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3631,29 +3411,6 @@ define <4 x i32> @v_fshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
; GFX10-NEXT: v_alignbit_b32 v2, v2, v6, v10
; GFX10-NEXT: v_alignbit_b32 v3, v3, v7, v11
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v4i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v4, v0, v4, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 1, v0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v8
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v5, v1, v5, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v9
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v6, v2, v6, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v10
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v7, v3, v7, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v11, v11
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_v4i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3701,6 +3458,17 @@ define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s3, s2, 15
+; GFX11-NEXT: s_and_not1_b32 s2, 15, s2
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3711,7 +3479,6 @@ define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3722,18 +3489,6 @@ define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_and_b32 s3, s2, 15
-; GFX11-NEXT: s_and_not1_b32 s2, 15, s2
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
ret i16 %result
}
@@ -3754,6 +3509,14 @@ define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i16_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_lshr_b32 s1, s1, 12
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i16_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3761,7 +3524,6 @@ define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: s_lshr_b32 s1, s1, 12
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i16_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3769,15 +3531,6 @@ define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX10-NEXT: s_lshr_b32 s1, s1, 12
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i16_4:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_lshr_b32 s1, s1, 12
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 4)
ret i16 %result
}
@@ -3798,22 +3551,6 @@ define amdgpu_ps i16 @s_fshl_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: s_fshl_i16_5:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX9-NEXT: s_lshl_b32 s0, s0, 5
-; GFX9-NEXT: s_lshr_b32 s1, s1, 11
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_fshl_i16_5:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: s_lshl_b32 s0, s0, 5
-; GFX10-NEXT: s_lshr_b32 s1, s1, 11
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: ; return to shader part epilog
-;
; GFX11-LABEL: s_fshl_i16_5:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3822,6 +3559,20 @@ define amdgpu_ps i16 @s_fshl_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: s_fshl_i16_5:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_lshl_b32 s0, s0, 5
+; GFX9-NEXT: s_lshr_b32 s1, s1, 11
+; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: ; return to shader part epilog
+; GFX10-LABEL: s_fshl_i16_5:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_lshl_b32 s0, s0, 5
+; GFX10-NEXT: s_lshr_b32 s1, s1, 11
+; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 5)
ret i16 %result
}
@@ -3842,15 +3593,23 @@ define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX8-LABEL: v_fshl_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b16 v0.h, v2.l, -1
+; GFX11-NEXT: v_lshrrev_b16 v1.l, 1, v1.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3862,7 +3621,6 @@ define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3874,21 +3632,6 @@ define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX10-NEXT: v_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 15
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, 1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 15
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3923,6 +3666,14 @@ define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i16_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 12, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i16_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3930,7 +3681,6 @@ define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, 12, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i16_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3938,16 +3688,6 @@ define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 12, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16_4:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 12, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i16_4:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3977,6 +3717,14 @@ define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i16_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 5, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 11, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i16_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3984,7 +3732,6 @@ define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, 11, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i16_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3992,16 +3739,6 @@ define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 11, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16_5:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 5, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 11, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshl_i16_5:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4028,16 +3765,25 @@ define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
;
; GFX8-LABEL: v_fshl_i16_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_and_b32_e32 v1, 15, v0
-; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0
; GFX8-NEXT: s_and_b32 s0, 0xffff, s1
-; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i16_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_xor_b16 v0.h, v0.l, -1
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.l, s0
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v0.h, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i16_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v1, 15, v0
@@ -4049,7 +3795,6 @@ define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i16_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -4061,22 +3806,6 @@ define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX10-NEXT: v_lshrrev_b16 v1, v1, s1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16_ssv:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v0.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 15
-; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i16_ssv:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -4110,13 +3839,24 @@ define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX8-LABEL: v_fshl_i16_svs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s2, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_xor_b32 s1, s1, -1
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 1, v0
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: v_lshrrev_b16_e32 v0, s1, v0
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i16_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshrrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: s_xor_b32 s2, s1, -1
+; GFX11-NEXT: s_and_b32 s1, s1, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_lshl_b32 s0, s0, s1
+; GFX11-NEXT: v_lshrrev_b16 v0.l, s2, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i16_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s2, s1, 15
@@ -4126,7 +3866,6 @@ define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX9-NEXT: v_lshrrev_b16_e32 v0, s1, v0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i16_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b16 v0, 1, v0
@@ -4136,19 +3875,6 @@ define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX10-NEXT: v_lshrrev_b16 v0, s2, v0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 15, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, s2, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i16_svs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, 1, v0
@@ -4179,14 +3905,24 @@ define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX8-LABEL: v_fshl_i16_vss:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX8-NEXT: s_and_b32 s2, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_andn2_b32 s2, 15, s1
; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, s2, v0
-; GFX8-NEXT: s_lshr_b32 s0, s0, s1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, s1, v0
+; GFX8-NEXT: s_lshr_b32 s0, s0, s2
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i16_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX11-NEXT: v_lshlrev_b16 v0.l, s1, v0.l
+; GFX11-NEXT: s_and_not1_b32 s2, 15, s1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshr_b32 s0, s0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, s0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i16_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
@@ -4197,7 +3933,6 @@ define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX9-NEXT: s_lshr_b32 s0, s0, s1
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i16_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s2, s1, 15
@@ -4208,20 +3943,6 @@ define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshl_i16_vss:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 15
-; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s1, 15, s1
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, s0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshl_i16_vss:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 15
@@ -4285,6 +4006,29 @@ define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v2i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s6, s1, 0xffff
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_and_b32 s3, s2, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s6, s6, 0x10001
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 0xf000f, s2
+; GFX11-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s3, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s6, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshl_b32 s3, s4, s5
+; GFX11-NEXT: s_and_b32 s4, s1, 0xffff
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_lshr_b32 s5, s2, 16
+; GFX11-NEXT: s_lshr_b32 s2, s4, s2
+; GFX11-NEXT: s_lshr_b32 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s3, s2, 0xf000f
@@ -4307,7 +4051,6 @@ define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s6, s1, 0xffff
@@ -4330,30 +4073,6 @@ define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_v2i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s6, s1, 0xffff
-; GFX11-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-NEXT: s_and_b32 s3, s2, 0xf000f
-; GFX11-NEXT: s_lshr_b32 s6, s6, 0x10001
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_not1_b32 s2, 0xf000f, s2
-; GFX11-NEXT: s_lshr_b32 s4, s0, 16
-; GFX11-NEXT: s_lshr_b32 s5, s3, 16
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s6, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshl_b32 s3, s4, s5
-; GFX11-NEXT: s_and_b32 s4, s1, 0xffff
-; GFX11-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-NEXT: s_lshr_b32 s5, s2, 16
-; GFX11-NEXT: s_lshr_b32 s2, s4, s2
-; GFX11-NEXT: s_lshr_b32 s1, s1, s5
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -4388,27 +4107,35 @@ define <2 x i16> @v_fshl_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX8-LABEL: v_fshl_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 15, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX8-NEXT: v_lshrrev_b16_e32 v5, 1, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, v3, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v5
-; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, 15
-; GFX8-NEXT: v_mov_b32_e32 v5, -1
-; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, v2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX8-NEXT: v_mov_b32_e32 v4, -1
+; GFX8-NEXT: v_xor_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 17, v1
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v4, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0xf000f, v2
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xf000f, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, v3, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4420,7 +4147,6 @@ define <2 x i16> @v_fshl_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4432,20 +4158,6 @@ define <2 x i16> @v_fshl_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_v2i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xf000f, v2
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xf000f, v3
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, v3, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
ret <2 x i16> %result
}
@@ -4480,6 +4192,14 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i16_4_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 0x80004, v0
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 0x8000c, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i16_4_8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4489,7 +4209,6 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i16_4_8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4497,15 +4216,6 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX10-NEXT: v_pk_lshrrev_b16 v1, 0x8000c, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_v2i16_4_8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 0x80004, v0
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, 0x8000c, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> <i16 4, i16 8>)
ret <2 x i16> %result
}
@@ -4537,29 +4247,41 @@ define amdgpu_ps float @v_fshl_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
;
; GFX8-LABEL: v_fshl_v2i16_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_and_b32_e32 v1, 15, v0
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_lshlrev_b16_e64 v2, v0, s0
; GFX8-NEXT: s_and_b32 s0, 0xffff, s1
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
; GFX8-NEXT: s_lshr_b32 s0, s0, 1
-; GFX8-NEXT: v_lshrrev_b16_e64 v2, v2, s0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_mov_b32_e32 v2, 15
-; GFX8-NEXT: v_mov_b32_e32 v3, -1
-; GFX8-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, -1
+; GFX8-NEXT: v_xor_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: s_lshr_b32 s0, s1, 17
-; GFX8-NEXT: v_lshlrev_b16_e64 v2, v2, s2
-; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, v2, s0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_v2i16_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX11-NEXT: s_and_b32 s2, s1, 0xffff
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xf000f, v0
+; GFX11-NEXT: s_lshr_b32 s2, s2, 0x10001
+; GFX11-NEXT: v_and_b32_e32 v1, 0xf000f, v1
+; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s1
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v0, s0
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_v2i16_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v1, 0xf000f, v0
@@ -4574,7 +4296,6 @@ define amdgpu_ps float @v_fshl_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_v2i16_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -4589,23 +4310,6 @@ define amdgpu_ps float @v_fshl_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v1, s1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_v2i16_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX11-NEXT: s_and_b32 s2, s1, 0xffff
-; GFX11-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-NEXT: v_and_b32_e32 v0, 0xf000f, v0
-; GFX11-NEXT: s_lshr_b32 s2, s2, 0x10001
-; GFX11-NEXT: v_and_b32_e32 v1, 0xf000f, v1
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v0, s0
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4638,14 +4342,14 @@ define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_and_b32 s4, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_xor_b32 s1, s1, -1
; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, s4
; GFX8-NEXT: v_lshrrev_b16_e32 v1, s1, v1
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
; GFX8-NEXT: s_and_b32 s0, s3, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s3
+; GFX8-NEXT: s_xor_b32 s1, s3, -1
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 17, v0
; GFX8-NEXT: s_lshl_b32 s0, s2, s0
; GFX8-NEXT: v_lshrrev_b16_e32 v0, s1, v0
@@ -4655,6 +4359,21 @@ define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_v2i16_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
+; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s4, s2, 16
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, s1, v0
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_lshl_b32 s1, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_v2i16_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s2, s1, 0xf000f
@@ -4668,7 +4387,6 @@ define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s1, v0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_v2i16_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_pk_lshrrev_b16 v0, 1, v0 op_sel_hi:[0,1]
@@ -4682,22 +4400,6 @@ define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_v2i16_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_pk_lshrrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
-; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
-; GFX11-NEXT: s_lshr_b32 s3, s0, 16
-; GFX11-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-NEXT: v_pk_lshrrev_b16 v0, s1, v0
-; GFX11-NEXT: s_lshl_b32 s0, s0, s2
-; GFX11-NEXT: s_lshl_b32 s1, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4728,30 +4430,47 @@ define amdgpu_ps float @v_fshl_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
;
; GFX8-LABEL: v_fshl_v2i16_vss:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s3, s1, 15
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, s3, v0
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s0
; GFX8-NEXT: s_lshr_b32 s2, s1, 16
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
-; GFX8-NEXT: s_lshr_b32 s1, s3, s1
+; GFX8-NEXT: s_andn2_b32 s3, 15, s1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, s1, v0
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s0
+; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: s_lshr_b32 s1, s1, s3
; GFX8-NEXT: v_or_b32_e32 v1, s1, v1
-; GFX8-NEXT: s_and_b32 s1, s2, 15
-; GFX8-NEXT: s_andn2_b32 s2, 15, s2
-; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_andn2_b32 s1, 15, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_lshr_b32 s0, s0, 17
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: s_lshr_b32 s0, s0, s2
+; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: v_fshl_v2i16_vss:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s2, s1, 0xf000f
-; GFX9-NEXT: v_pk_lshlrev_b16 v0, s2, v0
+; GFX11-LABEL: v_fshl_v2i16_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s3, s0, 0xffff
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s3, 0x10001
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
+; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s3, s0
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, s2, v0
+; GFX11-NEXT: s_and_b32 s2, s0, 0xffff
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11-NEXT: s_lshr_b32 s1, s2, s1
+; GFX11-NEXT: s_lshr_b32 s0, s0, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s1, s0
+; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: v_fshl_v2i16_vss:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_and_b32 s2, s1, 0xf000f
+; GFX9-NEXT: v_pk_lshlrev_b16 v0, s2, v0
; GFX9-NEXT: s_and_b32 s2, s0, 0xffff
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_lshr_b32 s2, s2, 0x10001
@@ -4766,7 +4485,6 @@ define amdgpu_ps float @v_fshl_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_v2i16_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s3, s0, 0xffff
@@ -4785,26 +4503,6 @@ define amdgpu_ps float @v_fshl_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_v2i16_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s3, s0, 0xffff
-; GFX11-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s3, 0x10001
-; GFX11-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
-; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s3, s0
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, s2, v0
-; GFX11-NEXT: s_and_b32 s2, s0, 0xffff
-; GFX11-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s1, 16
-; GFX11-NEXT: s_lshr_b32 s1, s2, s1
-; GFX11-NEXT: s_lshr_b32 s0, s0, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4873,6 +4571,47 @@ define amdgpu_ps i48 @s_fshl_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v3i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s9, s2, 0xffff
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_and_b32 s6, s4, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s9, s9, 0x10001
+; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
+; GFX11-NEXT: s_lshr_b32 s7, s0, 16
+; GFX11-NEXT: s_lshr_b32 s8, s6, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s9, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, s6
+; GFX11-NEXT: s_lshl_b32 s6, s7, s8
+; GFX11-NEXT: s_and_b32 s7, s2, 0xffff
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshr_b32 s8, s4, 16
+; GFX11-NEXT: s_lshr_b32 s4, s7, s4
+; GFX11-NEXT: s_lshr_b32 s2, s2, s8
+; GFX11-NEXT: s_and_b32 s8, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s4, s2
+; GFX11-NEXT: s_and_b32 s4, s5, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s8, s8, 0x10001
+; GFX11-NEXT: s_lshr_b32 s3, s3, 1
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
+; GFX11-NEXT: s_and_not1_b32 s5, 0xf000f, s5
+; GFX11-NEXT: s_lshr_b32 s6, s1, 16
+; GFX11-NEXT: s_lshr_b32 s7, s4, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s8, s3
+; GFX11-NEXT: s_lshl_b32 s1, s1, s4
+; GFX11-NEXT: s_lshl_b32 s4, s6, s7
+; GFX11-NEXT: s_and_b32 s6, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_lshr_b32 s7, s5, 16
+; GFX11-NEXT: s_lshr_b32 s5, s6, s5
+; GFX11-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v3i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s6, s4, 0xf000f
@@ -4919,7 +4658,6 @@ define amdgpu_ps i48 @s_fshl_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX9-NEXT: s_or_b32 s0, s0, s2
; GFX9-NEXT: s_and_b32 s1, s1, 0xffff
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v3i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s9, s2, 0xffff
@@ -4966,49 +4704,6 @@ define amdgpu_ps i48 @s_fshl_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX10-NEXT: s_or_b32 s0, s0, s3
; GFX10-NEXT: s_and_b32 s1, s1, 0xffff
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshl_v3i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s2, 0xffff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s4, 0xf000f
-; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s9, 0x10001
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s4, 0xf000f, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s6, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s9, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s7, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s2, 0xffff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s7, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s3, 0xffff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, 0xf000f
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s8, 0x10001
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 1
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s5, 0xf000f, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s6, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s3, 0xffff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s5, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s6, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s3
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshl_v3i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_and_b32 s9, s2, 0xffff
@@ -5098,28 +4793,21 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX8-LABEL: v_fshl_v3i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 15, v4
-; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v4
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v7, v8
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX8-NEXT: v_mov_b32_e32 v7, 15
-; GFX8-NEXT: v_mov_b32_e32 v8, -1
-; GFX8-NEXT: v_and_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, v4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, v6, v8
+; GFX8-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX8-NEXT: v_mov_b32_e32 v7, -1
+; GFX8-NEXT: v_xor_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 17, v2
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v4, v2
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v7, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v5
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, v2, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v4, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v5
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v5, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v2, v3
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
@@ -5127,6 +4815,26 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v3i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_pk_lshrrev_b16 v3, v7, v3
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v3i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5143,13 +4851,8 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, 1, v3 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
-; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
-; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v3i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5164,59 +4867,10 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
-; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshl_v3i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v7, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: v_fshl_v3i16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v6, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
@@ -5307,6 +4961,47 @@ define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v4i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s9, s2, 0xffff
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_and_b32 s6, s4, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s9, s9, 0x10001
+; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
+; GFX11-NEXT: s_lshr_b32 s7, s0, 16
+; GFX11-NEXT: s_lshr_b32 s8, s6, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s9, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, s6
+; GFX11-NEXT: s_lshl_b32 s6, s7, s8
+; GFX11-NEXT: s_and_b32 s7, s2, 0xffff
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshr_b32 s8, s4, 16
+; GFX11-NEXT: s_lshr_b32 s4, s7, s4
+; GFX11-NEXT: s_lshr_b32 s2, s2, s8
+; GFX11-NEXT: s_and_b32 s8, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s4, s2
+; GFX11-NEXT: s_and_b32 s4, s5, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s8, s8, 0x10001
+; GFX11-NEXT: s_lshr_b32 s3, s3, 1
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
+; GFX11-NEXT: s_and_not1_b32 s5, 0xf000f, s5
+; GFX11-NEXT: s_lshr_b32 s6, s1, 16
+; GFX11-NEXT: s_lshr_b32 s7, s4, 16
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s8, s3
+; GFX11-NEXT: s_lshl_b32 s1, s1, s4
+; GFX11-NEXT: s_lshl_b32 s4, s6, s7
+; GFX11-NEXT: s_and_b32 s6, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_lshr_b32 s7, s5, 16
+; GFX11-NEXT: s_lshr_b32 s5, s6, s5
+; GFX11-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s6, s4, 0xf000f
@@ -5348,7 +5043,6 @@ define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s2
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s9, s2, 0xffff
@@ -5390,48 +5084,6 @@ define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX10-NEXT: s_or_b32 s0, s0, s2
; GFX10-NEXT: s_or_b32 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_v4i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s9, s2, 0xffff
-; GFX11-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-NEXT: s_and_b32 s6, s4, 0xf000f
-; GFX11-NEXT: s_lshr_b32 s9, s9, 0x10001
-; GFX11-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
-; GFX11-NEXT: s_lshr_b32 s7, s0, 16
-; GFX11-NEXT: s_lshr_b32 s8, s6, 16
-; GFX11-NEXT: s_pack_ll_b32_b16 s2, s9, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-NEXT: s_lshl_b32 s6, s7, s8
-; GFX11-NEXT: s_and_b32 s7, s2, 0xffff
-; GFX11-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-NEXT: s_lshr_b32 s8, s4, 16
-; GFX11-NEXT: s_lshr_b32 s4, s7, s4
-; GFX11-NEXT: s_lshr_b32 s2, s2, s8
-; GFX11-NEXT: s_and_b32 s8, s3, 0xffff
-; GFX11-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX11-NEXT: s_and_b32 s4, s5, 0xf000f
-; GFX11-NEXT: s_lshr_b32 s8, s8, 0x10001
-; GFX11-NEXT: s_lshr_b32 s3, s3, 1
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX11-NEXT: s_and_not1_b32 s5, 0xf000f, s5
-; GFX11-NEXT: s_lshr_b32 s6, s1, 16
-; GFX11-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX11-NEXT: s_lshl_b32 s1, s1, s4
-; GFX11-NEXT: s_lshl_b32 s4, s6, s7
-; GFX11-NEXT: s_and_b32 s6, s3, 0xffff
-; GFX11-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-NEXT: s_lshr_b32 s7, s5, 16
-; GFX11-NEXT: s_lshr_b32 s5, s6, s5
-; GFX11-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: s_or_b32 s1, s1, s3
-; GFX11-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
%cast.result = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast.result
@@ -5488,35 +5140,26 @@ define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-LABEL: v_fshl_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 15, v4
-; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v4
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v7, v8
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX8-NEXT: v_mov_b32_e32 v7, 15
-; GFX8-NEXT: v_mov_b32_e32 v9, -1
-; GFX8-NEXT: v_and_b32_sdwa v8, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, v4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, v6, v8
+; GFX8-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX8-NEXT: v_mov_b32_e32 v7, -1
+; GFX8-NEXT: v_xor_b32_sdwa v8, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 17, v2
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v4, v2
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v8, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v5
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v3
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, v2, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v8
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_and_b32_sdwa v4, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v5, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v5, 15, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, v5, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v2, v8
+; GFX8-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_xor_b32_sdwa v4, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 17, v3
-; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, v5, v3
+; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, v4, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -5526,6 +5169,26 @@ define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v4i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_pk_lshrrev_b16 v3, v7, v3
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5544,7 +5207,6 @@ define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5563,51 +5225,30 @@ define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_v4i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v5, v1
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, v7, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
%cast.result = bitcast <4 x i16> %result to <4 x half>
ret <4 x half> %cast.result
}
define amdgpu_ps i64 @s_fshl_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt) {
-; GFX6-LABEL: s_fshl_i64:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_not_b32 s4, s4
-; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i64:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_not_b32 s4, s4
-; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: s_not_b32 s4, s4
+; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_not_b32 s5, s4
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
@@ -5616,7 +5257,6 @@ define amdgpu_ps i64 @s_fshl_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt)
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
@@ -5625,16 +5265,6 @@ define amdgpu_ps i64 @s_fshl_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt)
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_not_b32 s5, s4
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
ret i64 %result
}
@@ -5700,9 +5330,8 @@ define i64 @v_fshl_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: v_and_b32_e32 v5, 63, v4
-; GFX6-NEXT: v_bfi_b32 v4, v4, 0, 63
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v5
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
+; GFX6-NEXT: v_not_b32_e32 v4, v4
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
@@ -5712,14 +5341,25 @@ define i64 @v_fshl_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: v_and_b32_e32 v5, 63, v4
-; GFX8-NEXT: v_bfi_b32 v4, v4, 0, 63
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX8-NEXT: v_not_b32_e32 v4, v4
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: v_not_b32_e32 v5, v4
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5731,7 +5371,6 @@ define i64 @v_fshl_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5743,20 +5382,6 @@ define i64 @v_fshl_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_and_b32_e32 v5, 63, v4
-; GFX11-NEXT: v_bfi_b32 v4, v4, 0, 63
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
ret i64 %result
}
@@ -5778,6 +5403,14 @@ define i64 @v_fshl_i64_5(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i64_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 5, v[0:1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 27, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i64_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5785,7 +5418,6 @@ define i64 @v_fshl_i64_5(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 27, v3
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i64_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5793,15 +5425,6 @@ define i64 @v_fshl_i64_5(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 27, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i64_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 5, v[0:1]
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 27, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
ret i64 %result
}
@@ -5842,6 +5465,14 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i64_48:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v4, v0
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i64_48:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5849,7 +5480,6 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i64_48:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5857,15 +5487,6 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i64_48:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v4, v0
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 48)
ret i64 %result
}
@@ -5873,10 +5494,9 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
define amdgpu_ps <2 x float> @v_fshl_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64 %amt) {
; GFX6-LABEL: v_fshl_i64_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v1, 63, v0
-; GFX6-NEXT: v_lshl_b64 v[1:2], s[0:1], v1
+; GFX6-NEXT: v_lshl_b64 v[1:2], s[0:1], v0
; GFX6-NEXT: s_lshr_b64 s[0:1], s[2:3], 1
-; GFX6-NEXT: v_bfi_b32 v0, v0, 0, 63
+; GFX6-NEXT: v_not_b32_e32 v0, v0
; GFX6-NEXT: v_lshr_b64 v[3:4], s[0:1], v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v3
; GFX6-NEXT: v_or_b32_e32 v1, v2, v4
@@ -5884,15 +5504,25 @@ define amdgpu_ps <2 x float> @v_fshl_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
;
; GFX8-LABEL: v_fshl_i64_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_and_b32_e32 v1, 63, v0
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v1, s[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[1:2], v0, s[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[2:3], 1
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, 63
+; GFX8-NEXT: v_not_b32_e32 v0, v0
; GFX8-NEXT: v_lshrrev_b64 v[3:4], v0, s[0:1]
; GFX8-NEXT: v_or_b32_e32 v0, v1, v3
; GFX8-NEXT: v_or_b32_e32 v1, v2, v4
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i64_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_not_b32_e32 v2, v0
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, s[2:3]
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i64_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v1, 63, v0
@@ -5903,7 +5533,6 @@ define amdgpu_ps <2 x float> @v_fshl_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX9-NEXT: v_or_b32_e32 v0, v1, v3
; GFX9-NEXT: v_or_b32_e32 v1, v2, v4
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i64_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_b32_e32 v1, 63, v0
@@ -5914,19 +5543,6 @@ define amdgpu_ps <2 x float> @v_fshl_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i64_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v1, 63, v0
-; GFX11-NEXT: v_bfi_b32 v2, v0, 0, 63
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v1, s[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -5937,7 +5553,7 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX6-NEXT: s_andn2_b32 s2, 63, s2
+; GFX6-NEXT: s_not_b32 s2, s2
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
@@ -5949,7 +5565,7 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX8-NEXT: s_andn2_b32 s2, 63, s2
+; GFX8-NEXT: s_not_b32 s2, s2
; GFX8-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
@@ -5957,6 +5573,18 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i64_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: s_not_b32 s3, s2
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], s3, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i64_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
@@ -5968,7 +5596,6 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i64_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
@@ -5980,19 +5607,6 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-NEXT: v_or_b32_e32 v1, v3, v1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i64_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: s_and_not1_b32 s3, 63, s2
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], s3, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -6001,10 +5615,9 @@ define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg %amt) {
; GFX6-LABEL: v_fshl_i64_vss:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s3, s2, 63
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s2
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_not_b32 s2, s2
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
@@ -6014,10 +5627,9 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
;
; GFX8-LABEL: v_fshl_i64_vss:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s3, s2, 63
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], s2, v[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_not_b32 s2, s2
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
@@ -6025,6 +5637,18 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i64_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_not_b32 s3, s2
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], s2, v[0:1]
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i64_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s3, s2, 63
@@ -6037,7 +5661,6 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i64_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
@@ -6050,53 +5673,39 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i64_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_not_b32 s3, s2
-; GFX11-NEXT: s_and_b32 s2, s2, 63
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], s2, v[0:1]
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x i64> @s_fshl_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs, <2 x i64> inreg %amt) {
-; GFX6-LABEL: s_fshl_v2i64:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX6-NEXT: s_not_b32 s8, s8
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
-; GFX6-NEXT: s_not_b32 s6, s10
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_v2i64:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX8-NEXT: s_not_b32 s8, s8
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
-; GFX8-NEXT: s_not_b32 s6, s10
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_v2i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
+; GCN-NEXT: s_not_b32 s8, s8
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
+; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GCN-NEXT: s_not_b32 s6, s10
+; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
+; GFX11-NEXT: s_not_b32 s9, s8
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT: s_not_b32 s8, s10
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s8
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
@@ -6110,7 +5719,6 @@ define amdgpu_ps <2 x i64> @s_fshl_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
@@ -6124,20 +5732,6 @@ define amdgpu_ps <2 x i64> @s_fshl_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_v2i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX11-NEXT: s_not_b32 s9, s8
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
-; GFX11-NEXT: s_not_b32 s8, s10
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s8
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
ret <2 x i64> %result
}
@@ -6147,15 +5741,13 @@ define <2 x i64> @v_fshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], 1
-; GFX6-NEXT: v_and_b32_e32 v9, 63, v8
-; GFX6-NEXT: v_bfi_b32 v8, v8, 0, 63
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v9
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
+; GFX6-NEXT: v_not_b32_e32 v8, v8
; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v8
; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_and_b32_e32 v4, 63, v10
-; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v4
-; GFX6-NEXT: v_bfi_b32 v4, v10, 0, 63
+; GFX6-NEXT: v_not_b32_e32 v4, v10
+; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v10
; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
@@ -6166,21 +5758,38 @@ define <2 x i64> @v_fshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX8-NEXT: v_and_b32_e32 v9, 63, v8
-; GFX8-NEXT: v_bfi_b32 v8, v8, 0, 63
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX8-NEXT: v_not_b32_e32 v8, v8
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_and_b32_e32 v4, 63, v10
-; GFX8-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
-; GFX8-NEXT: v_bfi_b32 v4, v10, 0, 63
+; GFX8-NEXT: v_not_b32_e32 v4, v10
+; GFX8-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[6:7], v4, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v3, v3, v7
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
+; GFX11-NEXT: v_not_b32_e32 v9, v8
+; GFX11-NEXT: v_not_b32_e32 v11, v10
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v9, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[6:7], v11, v[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6199,7 +5808,6 @@ define <2 x i64> @v_fshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX9-NEXT: v_or_b32_e32 v2, v2, v6
; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6218,151 +5826,127 @@ define <2 x i64> @v_fshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_v2i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
-; GFX11-NEXT: v_and_b32_e32 v9, 63, v8
-; GFX11-NEXT: v_bfi_b32 v8, v8, 0, 63
-; GFX11-NEXT: v_and_b32_e32 v11, 63, v10
-; GFX11-NEXT: v_bfi_b32 v10, v10, 0, 63
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
-; GFX11-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
ret <2 x i64> %result
}
define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
-; GFX6-LABEL: s_fshl_i128:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX6-NEXT: s_sub_i32 s11, s9, 64
-; GFX6-NEXT: s_sub_i32 s14, 64, s9
-; GFX6-NEXT: s_cmp_lt_u32 s9, 64
-; GFX6-NEXT: s_cselect_b32 s18, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s9, 0
-; GFX6-NEXT: s_cselect_b32 s9, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[14:15], s[0:1], s14
-; GFX6-NEXT: s_lshl_b64 s[16:17], s[2:3], s8
-; GFX6-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
-; GFX6-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
-; GFX6-NEXT: s_cmp_lg_u32 s18, 0
-; GFX6-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
-; GFX6-NEXT: s_cmp_lg_u32 s9, 0
-; GFX6-NEXT: s_mov_b32 s10, 0
-; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
-; GFX6-NEXT: s_lshl_b32 s11, s6, 31
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
-; GFX6-NEXT: s_andn2_b32 s6, 0x7f, s8
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
-; GFX6-NEXT: s_not_b32 s9, s8
-; GFX6-NEXT: s_sub_i32 s14, s6, 64
-; GFX6-NEXT: s_sub_i32 s10, 64, s6
-; GFX6-NEXT: s_cmp_lt_u32 s6, 64
-; GFX6-NEXT: s_cselect_b32 s15, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s6, 0
-; GFX6-NEXT: s_cselect_b32 s16, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], s9
-; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], s9
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
-; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s14
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX6-NEXT: s_cmp_lg_u32 s16, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i128:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX8-NEXT: s_sub_i32 s11, s9, 64
-; GFX8-NEXT: s_sub_i32 s14, 64, s9
-; GFX8-NEXT: s_cmp_lt_u32 s9, 64
-; GFX8-NEXT: s_cselect_b32 s18, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s9, 0
-; GFX8-NEXT: s_cselect_b32 s9, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[14:15], s[0:1], s14
-; GFX8-NEXT: s_lshl_b64 s[16:17], s[2:3], s8
-; GFX8-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
-; GFX8-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
-; GFX8-NEXT: s_cmp_lg_u32 s18, 0
-; GFX8-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
-; GFX8-NEXT: s_cmp_lg_u32 s9, 0
-; GFX8-NEXT: s_mov_b32 s10, 0
-; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
-; GFX8-NEXT: s_lshl_b32 s11, s6, 31
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
-; GFX8-NEXT: s_andn2_b32 s6, 0x7f, s8
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
-; GFX8-NEXT: s_not_b32 s9, s8
-; GFX8-NEXT: s_sub_i32 s14, s6, 64
-; GFX8-NEXT: s_sub_i32 s10, 64, s6
-; GFX8-NEXT: s_cmp_lt_u32 s6, 64
-; GFX8-NEXT: s_cselect_b32 s15, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s6, 0
-; GFX8-NEXT: s_cselect_b32 s16, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[6:7], s[4:5], s9
-; GFX8-NEXT: s_lshr_b64 s[8:9], s[0:1], s9
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
-; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s14
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX8-NEXT: s_cmp_lg_u32 s16, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
-; GFX8-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i128:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_and_b32 s9, s8, 0x7f
+; GCN-NEXT: s_sub_i32 s11, s9, 64
+; GCN-NEXT: s_sub_i32 s14, 64, s9
+; GCN-NEXT: s_cmp_lt_u32 s9, 64
+; GCN-NEXT: s_cselect_b32 s18, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s9, 0
+; GCN-NEXT: s_cselect_b32 s9, 1, 0
+; GCN-NEXT: s_lshr_b64 s[14:15], s[0:1], s14
+; GCN-NEXT: s_lshl_b64 s[16:17], s[2:3], s8
+; GCN-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
+; GCN-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
+; GCN-NEXT: s_cmp_lg_u32 s18, 0
+; GCN-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
+; GCN-NEXT: s_cmp_lg_u32 s9, 0
+; GCN-NEXT: s_mov_b32 s10, 0
+; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GCN-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
+; GCN-NEXT: s_lshl_b32 s11, s6, 31
+; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GCN-NEXT: s_andn2_b32 s6, 0x7f, s8
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; GCN-NEXT: s_not_b32 s9, s8
+; GCN-NEXT: s_sub_i32 s14, s6, 64
+; GCN-NEXT: s_sub_i32 s10, 64, s6
+; GCN-NEXT: s_cmp_lt_u32 s6, 64
+; GCN-NEXT: s_cselect_b32 s15, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s6, 0
+; GCN-NEXT: s_cselect_b32 s16, 1, 0
+; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s9
+; GCN-NEXT: s_lshr_b64 s[8:9], s[0:1], s9
+; GCN-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
+; GCN-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s14
+; GCN-NEXT: s_cmp_lg_u32 s15, 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GCN-NEXT: s_cmp_lg_u32 s16, 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
+; GCN-NEXT: s_cmp_lg_u32 s15, 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
+; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: s_fshl_i128:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX9-NEXT: s_sub_i32 s11, s9, 64
-; GFX9-NEXT: s_sub_i32 s14, 64, s9
-; GFX9-NEXT: s_cmp_lt_u32 s9, 64
-; GFX9-NEXT: s_cselect_b32 s18, 1, 0
-; GFX9-NEXT: s_cmp_eq_u32 s9, 0
-; GFX9-NEXT: s_cselect_b32 s9, 1, 0
-; GFX9-NEXT: s_lshr_b64 s[14:15], s[0:1], s14
-; GFX9-NEXT: s_lshl_b64 s[16:17], s[2:3], s8
-; GFX9-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
-; GFX9-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
-; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
-; GFX9-NEXT: s_cmp_lg_u32 s18, 0
-; GFX9-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
-; GFX9-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
-; GFX9-NEXT: s_cmp_lg_u32 s9, 0
-; GFX9-NEXT: s_mov_b32 s10, 0
-; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
-; GFX9-NEXT: s_lshl_b32 s11, s6, 31
-; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GFX11-LABEL: s_fshl_i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s9, s8, 0x7f
+; GFX11-NEXT: s_mov_b32 s10, 0
+; GFX11-NEXT: s_sub_i32 s11, s9, 64
+; GFX11-NEXT: s_sub_i32 s12, 64, s9
+; GFX11-NEXT: s_cmp_lt_u32 s9, 64
+; GFX11-NEXT: s_cselect_b32 s18, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s9, 0
+; GFX11-NEXT: s_cselect_b32 s9, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[12:13], s[0:1], s12
+; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], s8
+; GFX11-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
+; GFX11-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
+; GFX11-NEXT: s_cmp_lg_u32 s18, 0
+; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s9, 0
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
+; GFX11-NEXT: s_lshl_b32 s11, s6, 31
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
+; GFX11-NEXT: s_and_not1_b32 s6, 0x7f, s8
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; GFX11-NEXT: s_not_b32 s10, s8
+; GFX11-NEXT: s_sub_i32 s12, s6, 64
+; GFX11-NEXT: s_sub_i32 s8, 64, s6
+; GFX11-NEXT: s_cmp_lt_u32 s6, 64
+; GFX11-NEXT: s_cselect_b32 s13, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s6, 0
+; GFX11-NEXT: s_cselect_b32 s16, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s10
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[4:5], s10
+; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX11-NEXT: s_cmp_lg_u32 s16, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[10:11], 0
+; GFX11-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: s_fshl_i128:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_and_b32 s9, s8, 0x7f
+; GFX9-NEXT: s_sub_i32 s11, s9, 64
+; GFX9-NEXT: s_sub_i32 s14, 64, s9
+; GFX9-NEXT: s_cmp_lt_u32 s9, 64
+; GFX9-NEXT: s_cselect_b32 s18, 1, 0
+; GFX9-NEXT: s_cmp_eq_u32 s9, 0
+; GFX9-NEXT: s_cselect_b32 s9, 1, 0
+; GFX9-NEXT: s_lshr_b64 s[14:15], s[0:1], s14
+; GFX9-NEXT: s_lshl_b64 s[16:17], s[2:3], s8
+; GFX9-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
+; GFX9-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
+; GFX9-NEXT: s_cmp_lg_u32 s18, 0
+; GFX9-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
+; GFX9-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
+; GFX9-NEXT: s_cmp_lg_u32 s9, 0
+; GFX9-NEXT: s_mov_b32 s10, 0
+; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
+; GFX9-NEXT: s_lshl_b32 s11, s6, 31
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX9-NEXT: s_andn2_b32 s6, 0x7f, s8
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
; GFX9-NEXT: s_not_b32 s9, s8
@@ -6386,7 +5970,6 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX9-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s9, s8, 0x7f
@@ -6433,53 +6016,6 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX10-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX11-NEXT: s_mov_b32 s10, 0
-; GFX11-NEXT: s_sub_i32 s11, s9, 64
-; GFX11-NEXT: s_sub_i32 s12, 64, s9
-; GFX11-NEXT: s_cmp_lt_u32 s9, 64
-; GFX11-NEXT: s_cselect_b32 s18, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s9, 0
-; GFX11-NEXT: s_cselect_b32 s9, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[12:13], s[0:1], s12
-; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], s8
-; GFX11-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
-; GFX11-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s11
-; GFX11-NEXT: s_cmp_lg_u32 s18, 0
-; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s9, 0
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
-; GFX11-NEXT: s_lshl_b32 s11, s6, 31
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
-; GFX11-NEXT: s_and_not1_b32 s6, 0x7f, s8
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
-; GFX11-NEXT: s_not_b32 s10, s8
-; GFX11-NEXT: s_sub_i32 s12, s6, 64
-; GFX11-NEXT: s_sub_i32 s8, 64, s6
-; GFX11-NEXT: s_cmp_lt_u32 s6, 64
-; GFX11-NEXT: s_cselect_b32 s13, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 0
-; GFX11-NEXT: s_cselect_b32 s16, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s10
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
-; GFX11-NEXT: s_lshr_b64 s[10:11], s[4:5], s10
-; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
-; GFX11-NEXT: s_cmp_lg_u32 s16, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[10:11], 0
-; GFX11-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
}
@@ -6488,35 +6024,35 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-LABEL: v_fshl_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v16, 0x7f, v8
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 64, v16
-; GFX6-NEXT: v_add_i32_e32 v18, vcc, 0xffffffc0, v16
+; GFX6-NEXT: v_and_b32_e32 v15, 0x7f, v8
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 64, v15
+; GFX6-NEXT: v_add_i32_e32 v17, vcc, 0xffffffc0, v15
; GFX6-NEXT: v_lshr_b64 v[9:10], v[0:1], v9
-; GFX6-NEXT: v_lshl_b64 v[11:12], v[2:3], v16
-; GFX6-NEXT: v_lshl_b64 v[13:14], v[0:1], v16
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v18
+; GFX6-NEXT: v_lshl_b64 v[11:12], v[2:3], v8
+; GFX6-NEXT: v_lshl_b64 v[13:14], v[0:1], v8
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v17
; GFX6-NEXT: v_or_b32_e32 v9, v9, v11
; GFX6-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
; GFX6-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], 1
-; GFX6-NEXT: v_mov_b32_e32 v15, 0x7f
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 31, v6
+; GFX6-NEXT: v_not_b32_e32 v8, v8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshr_b64 v[2:3], v[6:7], 1
-; GFX6-NEXT: v_bfi_b32 v14, v8, 0, v15
-; GFX6-NEXT: v_not_b32_e32 v17, 63
+; GFX6-NEXT: v_and_b32_e32 v14, 0x7f, v8
+; GFX6-NEXT: v_not_b32_e32 v16, 63
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v14
-; GFX6-NEXT: v_add_i32_e32 v15, vcc, v14, v17
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], v14
+; GFX6-NEXT: v_add_i32_e32 v15, vcc, v14, v16
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], v8
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], v6
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], v14
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], v8
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v15
; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
@@ -6537,35 +6073,35 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-LABEL: v_fshl_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v16, 0x7f, v8
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 64, v16
-; GFX8-NEXT: v_add_u32_e32 v18, vcc, 0xffffffc0, v16
+; GFX8-NEXT: v_and_b32_e32 v15, 0x7f, v8
+; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 64, v15
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0xffffffc0, v15
; GFX8-NEXT: v_lshrrev_b64 v[9:10], v9, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[11:12], v16, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[13:14], v16, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v18, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[11:12], v8, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[13:14], v8, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v17, v[0:1]
; GFX8-NEXT: v_or_b32_e32 v9, v9, v11
; GFX8-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v12, 0, v14, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
; GFX8-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v15, 0x7f
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v6
+; GFX8-NEXT: v_not_b32_e32 v8, v8
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[6:7]
-; GFX8-NEXT: v_bfi_b32 v14, v8, 0, v15
-; GFX8-NEXT: v_not_b32_e32 v17, 63
+; GFX8-NEXT: v_and_b32_e32 v14, 0x7f, v8
+; GFX8-NEXT: v_not_b32_e32 v16, 63
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v14
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, v14, v17
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], v14, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v15, vcc, v14, v16
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], v8, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v14, v[2:3]
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v15, v[2:3]
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
@@ -6583,6 +6119,56 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_or_b32_e32 v3, v13, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v17, 0x7f, v8
+; GFX11-NEXT: v_not_b32_e32 v18, v8
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[9:10], v8, v[2:3]
+; GFX11-NEXT: v_lshlrev_b64 v[13:14], v8, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v11, 64, v17
+; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v18
+; GFX11-NEXT: v_add_nc_u32_e32 v15, 0xffffffc0, v17
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 31, v5
+; GFX11-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
+; GFX11-NEXT: v_lshrrev_b64 v[11:12], v11, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v19
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v17
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v19
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v17
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v9
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v18, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[15:16], v16, v[6:7]
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v10
+; GFX11-NEXT: v_add_nc_u32_e32 v20, 0xffffffc0, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v0, v11, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v0, v8, v15
+; GFX11-NEXT: v_or_b32_e32 v8, v9, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v12, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], v20, v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v21, v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, v3, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v0, s1
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v18, v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v11, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, v4, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v0, v13, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v7, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6629,7 +6215,6 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
; GFX9-NEXT: v_or_b32_e32 v3, v13, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6675,55 +6260,6 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v17, 0x7f, v8
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
-; GFX11-NEXT: v_lshrrev_b64 v[9:10], 1, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v11, 64, v17
-; GFX11-NEXT: v_lshlrev_b64 v[7:8], v17, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v15, 0xffffffc0, v17
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 31, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v18
-; GFX11-NEXT: v_lshrrev_b64 v[11:12], v11, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[13:14], v17, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v17
-; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v18
-; GFX11-NEXT: v_lshlrev_b64 v[15:16], v16, v[9:10]
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v7
-; GFX11-NEXT: v_lshrrev_b64 v[6:7], v18, v[4:5]
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v18
-; GFX11-NEXT: v_cndmask_b32_e32 v20, v0, v11, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[11:12], v19, v[9:10]
-; GFX11-NEXT: v_or_b32_e32 v0, v6, v15
-; GFX11-NEXT: v_or_b32_e32 v6, v7, v16
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v8, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v11, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v18, v[9:10]
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, v6, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v9, 0, v14, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v20, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v13, v4
-; GFX11-NEXT: v_or_b32_e32 v1, v9, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
}
@@ -6731,41 +6267,41 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshl_i128_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v8, 0x7f, v0
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 64, v8
+; GFX6-NEXT: v_and_b32_e32 v7, 0x7f, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 64, v7
; GFX6-NEXT: v_lshr_b64 v[1:2], s[0:1], v1
-; GFX6-NEXT: v_lshl_b64 v[3:4], s[2:3], v8
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0xffffffc0, v8
-; GFX6-NEXT: v_lshl_b64 v[5:6], s[0:1], v8
+; GFX6-NEXT: v_lshl_b64 v[3:4], s[2:3], v0
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, 0xffffffc0, v7
+; GFX6-NEXT: v_lshl_b64 v[5:6], s[0:1], v0
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
; GFX6-NEXT: v_or_b32_e32 v4, v2, v4
-; GFX6-NEXT: v_lshl_b64 v[1:2], s[0:1], v10
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x7f
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
-; GFX6-NEXT: s_mov_b32 s8, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v6, vcc
+; GFX6-NEXT: v_lshl_b64 v[1:2], s[0:1], v9
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT: v_mov_b32_e32 v3, s2
; GFX6-NEXT: v_mov_b32_e32 v4, s3
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v12, v2, v4, vcc
+; GFX6-NEXT: v_not_b32_e32 v2, v0
+; GFX6-NEXT: s_mov_b32 s8, 0
+; GFX6-NEXT: v_mov_b32_e32 v3, s2
; GFX6-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX6-NEXT: s_lshl_b32 s9, s6, 31
-; GFX6-NEXT: v_bfi_b32 v13, v0, 0, v7
-; GFX6-NEXT: v_cndmask_b32_e32 v8, v1, v3, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v12, v2, v4, vcc
+; GFX6-NEXT: v_and_b32_e32 v13, 0x7f, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v11, v1, v3, vcc
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[2:3], s[6:7], 1
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 64, v13
-; GFX6-NEXT: v_not_b32_e32 v9, 63
-; GFX6-NEXT: v_lshr_b64 v[2:3], s[0:1], v13
+; GFX6-NEXT: v_not_b32_e32 v8, 63
+; GFX6-NEXT: v_lshr_b64 v[0:1], s[2:3], v2
+; GFX6-NEXT: v_lshr_b64 v[2:3], s[0:1], v2
; GFX6-NEXT: v_lshl_b64 v[4:5], s[2:3], v4
-; GFX6-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GFX6-NEXT: v_or_b32_e32 v4, v2, v4
; GFX6-NEXT: v_or_b32_e32 v5, v3, v5
-; GFX6-NEXT: v_lshr_b64 v[2:3], s[2:3], v9
-; GFX6-NEXT: v_lshr_b64 v[0:1], s[2:3], v13
+; GFX6-NEXT: v_lshr_b64 v[2:3], s[2:3], v8
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; GFX6-NEXT: v_mov_b32_e32 v7, s1
; GFX6-NEXT: v_mov_b32_e32 v6, s0
@@ -6776,49 +6312,49 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX6-NEXT: v_or_b32_e32 v0, v10, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v11, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v8, v4
+; GFX6-NEXT: v_or_b32_e32 v0, v9, v2
+; GFX6-NEXT: v_or_b32_e32 v1, v10, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v11, v4
; GFX6-NEXT: v_or_b32_e32 v3, v12, v5
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_fshl_i128_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_and_b32_e32 v8, 0x7f, v0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 64, v8
+; GFX8-NEXT: v_and_b32_e32 v7, 0x7f, v0
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 64, v7
; GFX8-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[3:4], v8, s[2:3]
-; GFX8-NEXT: v_add_u32_e32 v10, vcc, 0xffffffc0, v8
-; GFX8-NEXT: v_lshlrev_b64 v[5:6], v8, s[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[3:4], v0, s[2:3]
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0xffffffc0, v7
+; GFX8-NEXT: v_lshlrev_b64 v[5:6], v0, s[0:1]
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
; GFX8-NEXT: v_or_b32_e32 v4, v2, v4
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v10, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x7f
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
-; GFX8-NEXT: s_mov_b32 s8, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v6, vcc
+; GFX8-NEXT: v_lshlrev_b64 v[1:2], v9, s[0:1]
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mov_b32_e32 v4, s3
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v2, v4, vcc
+; GFX8-NEXT: v_not_b32_e32 v2, v0
+; GFX8-NEXT: s_mov_b32 s8, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX8-NEXT: s_lshl_b32 s9, s6, 31
-; GFX8-NEXT: v_bfi_b32 v13, v0, 0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v1, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v12, v2, v4, vcc
+; GFX8-NEXT: v_and_b32_e32 v13, 0x7f, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v1, v3, vcc
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[2:3], s[6:7], 1
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 64, v13
-; GFX8-NEXT: v_not_b32_e32 v9, 63
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v13, s[0:1]
+; GFX8-NEXT: v_not_b32_e32 v8, 63
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, s[2:3]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[4:5], v4, s[2:3]
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, v13, v9
+; GFX8-NEXT: v_add_u32_e32 v8, vcc, v13, v8
; GFX8-NEXT: v_or_b32_e32 v4, v2, v4
; GFX8-NEXT: v_or_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v9, s[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], v13, s[2:3]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], v8, s[2:3]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
; GFX8-NEXT: v_mov_b32_e32 v7, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s0
@@ -6829,12 +6365,67 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX8-NEXT: v_or_b32_e32 v0, v10, v2
-; GFX8-NEXT: v_or_b32_e32 v1, v11, v3
-; GFX8-NEXT: v_or_b32_e32 v2, v8, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v9, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v10, v3
+; GFX8-NEXT: v_or_b32_e32 v2, v11, v4
; GFX8-NEXT: v_or_b32_e32 v3, v12, v5
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i128_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_mov_b32 s8, 0
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
+; GFX11-NEXT: s_lshl_b32 s9, s6, 31
+; GFX11-NEXT: v_not_b32_e32 v12, v0
+; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GFX11-NEXT: v_and_b32_e32 v11, 0x7f, v0
+; GFX11-NEXT: v_lshlrev_b64 v[1:2], v0, s[2:3]
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT: v_and_b32_e32 v13, 0x7f, v12
+; GFX11-NEXT: v_lshlrev_b64 v[5:6], v0, s[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v11
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v13
+; GFX11-NEXT: v_add_nc_u32_e32 v14, 0xffffffc0, v13
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
+; GFX11-NEXT: v_dual_cndmask_b32 v15, 0, v5 :: v_dual_cndmask_b32 v6, 0, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v1
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v12, s[4:5]
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v5, v0, v9
+; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_add_nc_u32 v7, 0xffffffc0, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v1, v10
+; GFX11-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 0, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[7:8], v7, s[0:1]
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v14, s[6:7]
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v5, s1
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v12, s[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s3, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v5, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v0, v15, v0
+; GFX11-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX11-NEXT: v_or_b32_e32 v3, v8, v3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i128_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v8, 0x7f, v0
@@ -6886,7 +6477,6 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX9-NEXT: v_or_b32_e32 v2, v8, v4
; GFX9-NEXT: v_or_b32_e32 v3, v11, v5
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i128_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_and_b32_e32 v11, 0x7f, v0
@@ -6935,60 +6525,6 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX10-NEXT: v_or_b32_e32 v2, v7, v2
; GFX10-NEXT: v_or_b32_e32 v3, v8, v3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i128_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v11, 0x7f, v0
-; GFX11-NEXT: v_bfi_b32 v12, v0, 0, 0x7f
-; GFX11-NEXT: s_mov_b32 s8, 0
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX11-NEXT: s_lshl_b32 s9, s6, 31
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v14, 0, v5 :: v_dual_add_nc_u32 v13, 0xffffffc0, v12
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, 64, v11
-; GFX11-NEXT: v_lshlrev_b64 v[1:2], v11, s[2:3]
-; GFX11-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[3:4], v3, s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v12, s[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[7:8], v7, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX11-NEXT: v_or_b32_e32 v5, v0, v9
-; GFX11-NEXT: v_mov_b32_e32 v0, s4
-; GFX11-NEXT: v_or_b32_e32 v9, v1, v10
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 0, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v5, s1
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], v12, s[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s3, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v4, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v5, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v14, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v3
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
@@ -7015,29 +6551,30 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: s_andn2_b32 s2, 0x7f, s4
+; GFX6-NEXT: s_andn2_b32 s3, 0x7f, s4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: s_sub_i32 s3, s2, 64
-; GFX6-NEXT: s_sub_i32 s4, 64, s2
+; GFX6-NEXT: s_not_b32 s2, s4
+; GFX6-NEXT: s_sub_i32 s4, s3, 64
+; GFX6-NEXT: s_sub_i32 s5, 64, s3
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX6-NEXT: s_cmp_lt_u32 s2, 64
-; GFX6-NEXT: s_cselect_b32 s5, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s2, 0
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s2
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4
+; GFX6-NEXT: s_cmp_lt_u32 s3, 64
; GFX6-NEXT: s_cselect_b32 s8, 1, 0
+; GFX6-NEXT: s_cmp_eq_u32 s3, 0
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s2
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5
+; GFX6-NEXT: s_cselect_b32 s3, 1, 0
; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s2
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s3
-; GFX6-NEXT: s_cmp_lg_u32 s5, 0
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s4
+; GFX6-NEXT: s_cmp_lg_u32 s8, 0
; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s8, 0
+; GFX6-NEXT: s_cmp_lg_u32 s3, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s5, 0
+; GFX6-NEXT: s_cmp_lg_u32 s8, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7073,29 +6610,30 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: s_andn2_b32 s2, 0x7f, s4
+; GFX8-NEXT: s_andn2_b32 s3, 0x7f, s4
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: s_sub_i32 s3, s2, 64
-; GFX8-NEXT: s_sub_i32 s4, 64, s2
+; GFX8-NEXT: s_not_b32 s2, s4
+; GFX8-NEXT: s_sub_i32 s4, s3, 64
+; GFX8-NEXT: s_sub_i32 s5, 64, s3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: s_cmp_lt_u32 s2, 64
-; GFX8-NEXT: s_cselect_b32 s5, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s2, 0
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
+; GFX8-NEXT: s_cmp_lt_u32 s3, 64
; GFX8-NEXT: s_cselect_b32 s8, 1, 0
+; GFX8-NEXT: s_cmp_eq_u32 s3, 0
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
+; GFX8-NEXT: s_cselect_b32 s3, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[8:9], s2, v[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3]
-; GFX8-NEXT: s_cmp_lg_u32 s5, 0
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3]
+; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s8, 0
+; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s5, 0
+; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7111,6 +6649,61 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: v_or_b32_e32 v3, v3, v5
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i128_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s5, s4, 0x7f
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: s_sub_i32 s12, s5, 64
+; GFX11-NEXT: s_sub_i32 s6, 64, s5
+; GFX11-NEXT: s_cmp_lt_u32 s5, 64
+; GFX11-NEXT: s_cselect_b32 s13, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s5, 0
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 31, v1
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s4
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[0:1], s4
+; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s12
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX11-NEXT: s_and_not1_b32 s2, 0x7f, s4
+; GFX11-NEXT: s_not_b32 s3, s4
+; GFX11-NEXT: s_sub_i32 s5, 64, s2
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], s3, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
+; GFX11-NEXT: s_sub_i32 s4, s2, 64
+; GFX11-NEXT: s_cmp_lt_u32 s2, 64
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], s3, v[2:3]
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s2, 0
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3]
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i128_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s5, s4, 0x7f
@@ -7167,7 +6760,6 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i128_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s5, s4, 0x7f
@@ -7224,62 +6816,6 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i128_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s5, s4, 0x7f
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: s_sub_i32 s12, s5, 64
-; GFX11-NEXT: s_sub_i32 s6, 64, s5
-; GFX11-NEXT: s_cmp_lt_u32 s5, 64
-; GFX11-NEXT: s_cselect_b32 s13, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 31, v1
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s4
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[0:1], s4
-; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s12
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-NEXT: s_and_not1_b32 s2, 0x7f, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s4, 64, s2
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
-; GFX11-NEXT: s_sub_i32 s3, s2, 64
-; GFX11-NEXT: s_cmp_lt_u32 s2, 64
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], s2, v[2:3]
-; GFX11-NEXT: s_cselect_b32 s4, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 0
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3]
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
@@ -7294,10 +6830,10 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: s_cmp_lt_u32 s5, 64
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s5, 0
-; GFX6-NEXT: s_cselect_b32 s10, 1, 0
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s8
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5
-; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s5
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s4
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s7
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7306,7 +6842,7 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s10, 0
+; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
@@ -7354,10 +6890,10 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: s_cmp_lt_u32 s5, 64
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s5, 0
-; GFX8-NEXT: s_cselect_b32 s10, 1, 0
+; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[8:9], s5, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1]
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7366,7 +6902,7 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s10, 0
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: s_mov_b32 s6, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
@@ -7406,6 +6942,65 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshl_i128_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s5, s4, 0x7f
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
+; GFX11-NEXT: s_sub_i32 s6, 64, s5
+; GFX11-NEXT: s_sub_i32 s7, s5, 64
+; GFX11-NEXT: s_cmp_lt_u32 s5, 64
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s5, 0
+; GFX11-NEXT: s_mov_b32 s8, 0
+; GFX11-NEXT: s_cselect_b32 s9, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cselect_b32 s5, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s9, 0
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s6, exec_lo, 0
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_lshl_b32 s9, s2, 31
+; GFX11-NEXT: s_and_not1_b32 s7, 0x7f, s4
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_not_b32 s10, s4
+; GFX11-NEXT: s_sub_i32 s12, s7, 64
+; GFX11-NEXT: s_sub_i32 s8, 64, s7
+; GFX11-NEXT: s_cmp_lt_u32 s7, 64
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5
+; GFX11-NEXT: s_cselect_b32 s13, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s7, 0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
+; GFX11-NEXT: s_cselect_b32 s7, 1, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], s10
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
+; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
+; GFX11-NEXT: s_cmp_lg_u32 s7, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_or_b32_e32 v0, v6, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v1, v7, v1
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshl_i128_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s5, s4, 0x7f
@@ -7465,7 +7060,6 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v3, v5, v3
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshl_i128_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s5, s4, 0x7f
@@ -7525,92 +7119,31 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshl_i128_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s5, s4, 0x7f
-; GFX11-NEXT: s_mov_b32 s8, 0
-; GFX11-NEXT: s_sub_i32 s6, 64, s5
-; GFX11-NEXT: s_sub_i32 s7, s5, 64
-; GFX11-NEXT: s_cmp_lt_u32 s5, 64
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
-; GFX11-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
-; GFX11-NEXT: s_cselect_b32 s9, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], s5, v[0:1]
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cselect_b32 s5, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s9, 0
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1]
-; GFX11-NEXT: s_cselect_b32 s6, exec_lo, 0
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_lshl_b32 s9, s2, 31
-; GFX11-NEXT: s_and_not1_b32 s7, 0x7f, s4
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_not_b32 s10, s4
-; GFX11-NEXT: s_sub_i32 s12, s7, 64
-; GFX11-NEXT: s_sub_i32 s8, 64, s7
-; GFX11-NEXT: s_cmp_lt_u32 s7, 64
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5
-; GFX11-NEXT: s_cselect_b32 s13, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s7, 0
-; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
-; GFX11-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], s10
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
-; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
-; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s7, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX11-NEXT: v_or_b32_e32 v0, v6, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v7, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
}
define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
-; GFX6-LABEL: s_fshl_i128_65:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
-; GFX6-NEXT: s_lshr_b32 s4, s5, 31
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
-; GFX6-NEXT: s_or_b32 s0, s0, s4
-; GFX6-NEXT: s_lshr_b32 s4, s7, 31
-; GFX6-NEXT: s_or_b32 s2, s2, s4
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i128_65:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
-; GFX8-NEXT: s_lshr_b32 s4, s5, 31
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
-; GFX8-NEXT: s_or_b32 s0, s0, s4
-; GFX8-NEXT: s_lshr_b32 s4, s7, 31
-; GFX8-NEXT: s_or_b32 s2, s2, s4
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i128_65:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
+; GCN-NEXT: s_lshr_b32 s4, s5, 31
+; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
+; GCN-NEXT: s_or_b32 s0, s0, s4
+; GCN-NEXT: s_lshr_b32 s4, s7, 31
+; GCN-NEXT: s_or_b32 s2, s2, s4
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_i128_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
+; GFX11-NEXT: s_lshr_b32 s4, s5, 31
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
+; GFX11-NEXT: s_lshr_b32 s5, s7, 31
+; GFX11-NEXT: s_or_b32 s0, s0, s4
+; GFX11-NEXT: s_or_b32 s2, s2, s5
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
@@ -7620,7 +7153,6 @@ define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: s_lshr_b32 s4, s7, 31
; GFX9-NEXT: s_or_b32 s2, s2, s4
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_i128_65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
@@ -7630,16 +7162,6 @@ define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX10-NEXT: s_or_b32 s0, s0, s4
; GFX10-NEXT: s_or_b32 s2, s2, s5
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_i128_65:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
-; GFX11-NEXT: s_lshr_b32 s4, s5, 31
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
-; GFX11-NEXT: s_lshr_b32 s5, s7, 31
-; GFX11-NEXT: s_or_b32 s0, s0, s4
-; GFX11-NEXT: s_or_b32 s2, s2, s5
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
ret i128 %result
}
@@ -7667,6 +7189,17 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_i128_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 31, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -7677,7 +7210,6 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_i128_65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -7688,201 +7220,188 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_i128_65:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 31, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
ret i128 %result
}
define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
-; GFX6-LABEL: s_fshl_v2i128:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s17, s16, 0x7f
-; GFX6-NEXT: s_sub_i32 s19, s17, 64
-; GFX6-NEXT: s_sub_i32 s21, 64, s17
-; GFX6-NEXT: s_cmp_lt_u32 s17, 64
-; GFX6-NEXT: s_cselect_b32 s28, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s17, 0
-; GFX6-NEXT: s_cselect_b32 s17, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[24:25], s[0:1], s21
-; GFX6-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
-; GFX6-NEXT: s_lshl_b64 s[22:23], s[0:1], s16
-; GFX6-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s19
-; GFX6-NEXT: s_cmp_lg_u32 s28, 0
-; GFX6-NEXT: s_cselect_b64 s[22:23], s[22:23], 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
-; GFX6-NEXT: s_cmp_lg_u32 s17, 0
-; GFX6-NEXT: s_mov_b32 s18, 0
-; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
-; GFX6-NEXT: s_lshl_b32 s19, s10, 31
-; GFX6-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
-; GFX6-NEXT: s_andn2_b32 s10, 0x7f, s16
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
-; GFX6-NEXT: s_not_b32 s17, s16
-; GFX6-NEXT: s_sub_i32 s19, s10, 64
-; GFX6-NEXT: s_sub_i32 s21, 64, s10
-; GFX6-NEXT: s_cmp_lt_u32 s10, 64
-; GFX6-NEXT: s_cselect_b32 s26, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s10, 0
-; GFX6-NEXT: s_cselect_b32 s27, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[8:9], s17
-; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s17
-; GFX6-NEXT: s_lshl_b64 s[24:25], s[8:9], s21
-; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[24:25]
-; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], s19
-; GFX6-NEXT: s_cmp_lg_u32 s26, 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
-; GFX6-NEXT: s_cmp_lg_u32 s27, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
-; GFX6-NEXT: s_cmp_lg_u32 s26, 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX6-NEXT: s_and_b32 s8, s20, 0x7f
-; GFX6-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1]
-; GFX6-NEXT: s_sub_i32 s19, s8, 64
-; GFX6-NEXT: s_sub_i32 s10, 64, s8
-; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: s_cselect_b32 s21, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s8, 0
-; GFX6-NEXT: s_cselect_b32 s22, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s10
-; GFX6-NEXT: s_lshl_b64 s[16:17], s[6:7], s20
-; GFX6-NEXT: s_lshl_b64 s[8:9], s[4:5], s20
-; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s19
-; GFX6-NEXT: s_cmp_lg_u32 s21, 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
-; GFX6-NEXT: s_cmp_lg_u32 s22, 0
-; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
-; GFX6-NEXT: s_lshl_b32 s19, s14, 31
-; GFX6-NEXT: s_andn2_b32 s12, 0x7f, s20
-; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[18:19]
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
-; GFX6-NEXT: s_not_b32 s14, s20
-; GFX6-NEXT: s_sub_i32 s18, s12, 64
-; GFX6-NEXT: s_sub_i32 s16, 64, s12
-; GFX6-NEXT: s_cmp_lt_u32 s12, 64
-; GFX6-NEXT: s_cselect_b32 s19, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s12, 0
-; GFX6-NEXT: s_cselect_b32 s20, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[12:13], s[10:11], s14
-; GFX6-NEXT: s_lshr_b64 s[14:15], s[4:5], s14
-; GFX6-NEXT: s_lshl_b64 s[16:17], s[10:11], s16
-; GFX6-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s18
-; GFX6-NEXT: s_cmp_lg_u32 s19, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[14:15], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s20, 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s19, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
-; GFX6-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
-; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_v2i128:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s17, s16, 0x7f
-; GFX8-NEXT: s_sub_i32 s19, s17, 64
-; GFX8-NEXT: s_sub_i32 s21, 64, s17
-; GFX8-NEXT: s_cmp_lt_u32 s17, 64
-; GFX8-NEXT: s_cselect_b32 s28, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s17, 0
-; GFX8-NEXT: s_cselect_b32 s17, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[24:25], s[0:1], s21
-; GFX8-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
-; GFX8-NEXT: s_lshl_b64 s[22:23], s[0:1], s16
-; GFX8-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s19
-; GFX8-NEXT: s_cmp_lg_u32 s28, 0
-; GFX8-NEXT: s_cselect_b64 s[22:23], s[22:23], 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
-; GFX8-NEXT: s_cmp_lg_u32 s17, 0
-; GFX8-NEXT: s_mov_b32 s18, 0
-; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
-; GFX8-NEXT: s_lshl_b32 s19, s10, 31
-; GFX8-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
-; GFX8-NEXT: s_andn2_b32 s10, 0x7f, s16
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
-; GFX8-NEXT: s_not_b32 s17, s16
-; GFX8-NEXT: s_sub_i32 s19, s10, 64
-; GFX8-NEXT: s_sub_i32 s21, 64, s10
-; GFX8-NEXT: s_cmp_lt_u32 s10, 64
-; GFX8-NEXT: s_cselect_b32 s26, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s10, 0
-; GFX8-NEXT: s_cselect_b32 s27, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[8:9], s17
-; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s17
-; GFX8-NEXT: s_lshl_b64 s[24:25], s[8:9], s21
-; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[24:25]
-; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s19
-; GFX8-NEXT: s_cmp_lg_u32 s26, 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
-; GFX8-NEXT: s_cmp_lg_u32 s27, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
-; GFX8-NEXT: s_cmp_lg_u32 s26, 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX8-NEXT: s_and_b32 s8, s20, 0x7f
-; GFX8-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1]
-; GFX8-NEXT: s_sub_i32 s19, s8, 64
-; GFX8-NEXT: s_sub_i32 s10, 64, s8
-; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: s_cselect_b32 s21, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s8, 0
-; GFX8-NEXT: s_cselect_b32 s22, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s10
-; GFX8-NEXT: s_lshl_b64 s[16:17], s[6:7], s20
-; GFX8-NEXT: s_lshl_b64 s[8:9], s[4:5], s20
-; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s19
-; GFX8-NEXT: s_cmp_lg_u32 s21, 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
-; GFX8-NEXT: s_cmp_lg_u32 s22, 0
-; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
-; GFX8-NEXT: s_lshl_b32 s19, s14, 31
-; GFX8-NEXT: s_andn2_b32 s12, 0x7f, s20
-; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[18:19]
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
-; GFX8-NEXT: s_not_b32 s14, s20
-; GFX8-NEXT: s_sub_i32 s18, s12, 64
-; GFX8-NEXT: s_sub_i32 s16, 64, s12
-; GFX8-NEXT: s_cmp_lt_u32 s12, 64
-; GFX8-NEXT: s_cselect_b32 s19, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s12, 0
-; GFX8-NEXT: s_cselect_b32 s20, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[12:13], s[10:11], s14
-; GFX8-NEXT: s_lshr_b64 s[14:15], s[4:5], s14
-; GFX8-NEXT: s_lshl_b64 s[16:17], s[10:11], s16
-; GFX8-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s18
-; GFX8-NEXT: s_cmp_lg_u32 s19, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[14:15], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s20, 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s19, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
-; GFX8-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
-; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_v2i128:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_and_b32 s17, s16, 0x7f
+; GCN-NEXT: s_sub_i32 s19, s17, 64
+; GCN-NEXT: s_sub_i32 s21, 64, s17
+; GCN-NEXT: s_cmp_lt_u32 s17, 64
+; GCN-NEXT: s_cselect_b32 s28, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s17, 0
+; GCN-NEXT: s_cselect_b32 s17, 1, 0
+; GCN-NEXT: s_lshr_b64 s[24:25], s[0:1], s21
+; GCN-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
+; GCN-NEXT: s_lshl_b64 s[22:23], s[0:1], s16
+; GCN-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s19
+; GCN-NEXT: s_cmp_lg_u32 s28, 0
+; GCN-NEXT: s_cselect_b64 s[22:23], s[22:23], 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
+; GCN-NEXT: s_cmp_lg_u32 s17, 0
+; GCN-NEXT: s_mov_b32 s18, 0
+; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
+; GCN-NEXT: s_lshl_b32 s19, s10, 31
+; GCN-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
+; GCN-NEXT: s_andn2_b32 s10, 0x7f, s16
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
+; GCN-NEXT: s_not_b32 s17, s16
+; GCN-NEXT: s_sub_i32 s19, s10, 64
+; GCN-NEXT: s_sub_i32 s21, 64, s10
+; GCN-NEXT: s_cmp_lt_u32 s10, 64
+; GCN-NEXT: s_cselect_b32 s26, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s10, 0
+; GCN-NEXT: s_cselect_b32 s27, 1, 0
+; GCN-NEXT: s_lshr_b64 s[10:11], s[8:9], s17
+; GCN-NEXT: s_lshr_b64 s[16:17], s[0:1], s17
+; GCN-NEXT: s_lshl_b64 s[24:25], s[8:9], s21
+; GCN-NEXT: s_or_b64 s[16:17], s[16:17], s[24:25]
+; GCN-NEXT: s_lshr_b64 s[8:9], s[8:9], s19
+; GCN-NEXT: s_cmp_lg_u32 s26, 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
+; GCN-NEXT: s_cmp_lg_u32 s27, 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
+; GCN-NEXT: s_cmp_lg_u32 s26, 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GCN-NEXT: s_and_b32 s8, s20, 0x7f
+; GCN-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1]
+; GCN-NEXT: s_sub_i32 s19, s8, 64
+; GCN-NEXT: s_sub_i32 s10, 64, s8
+; GCN-NEXT: s_cmp_lt_u32 s8, 64
+; GCN-NEXT: s_cselect_b32 s21, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s8, 0
+; GCN-NEXT: s_cselect_b32 s22, 1, 0
+; GCN-NEXT: s_lshr_b64 s[10:11], s[4:5], s10
+; GCN-NEXT: s_lshl_b64 s[16:17], s[6:7], s20
+; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s20
+; GCN-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
+; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], s19
+; GCN-NEXT: s_cmp_lg_u32 s21, 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
+; GCN-NEXT: s_cmp_lg_u32 s22, 0
+; GCN-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
+; GCN-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
+; GCN-NEXT: s_lshl_b32 s19, s14, 31
+; GCN-NEXT: s_andn2_b32 s12, 0x7f, s20
+; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[18:19]
+; GCN-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
+; GCN-NEXT: s_not_b32 s14, s20
+; GCN-NEXT: s_sub_i32 s18, s12, 64
+; GCN-NEXT: s_sub_i32 s16, 64, s12
+; GCN-NEXT: s_cmp_lt_u32 s12, 64
+; GCN-NEXT: s_cselect_b32 s19, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s12, 0
+; GCN-NEXT: s_cselect_b32 s20, 1, 0
+; GCN-NEXT: s_lshr_b64 s[12:13], s[10:11], s14
+; GCN-NEXT: s_lshr_b64 s[14:15], s[4:5], s14
+; GCN-NEXT: s_lshl_b64 s[16:17], s[10:11], s16
+; GCN-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
+; GCN-NEXT: s_lshr_b64 s[10:11], s[10:11], s18
+; GCN-NEXT: s_cmp_lg_u32 s19, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[14:15], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s20, 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s19, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
+; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
+; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshl_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s17, s16, 0x7f
+; GFX11-NEXT: s_mov_b32 s18, 0
+; GFX11-NEXT: s_sub_i32 s19, s17, 64
+; GFX11-NEXT: s_sub_i32 s21, 64, s17
+; GFX11-NEXT: s_cmp_lt_u32 s17, 64
+; GFX11-NEXT: s_cselect_b32 s28, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s17, 0
+; GFX11-NEXT: s_cselect_b32 s17, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[22:23], s[0:1], s21
+; GFX11-NEXT: s_lshl_b64 s[24:25], s[2:3], s16
+; GFX11-NEXT: s_lshl_b64 s[26:27], s[0:1], s16
+; GFX11-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s19
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_cselect_b64 s[24:25], s[26:27], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s17, 0
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
+; GFX11-NEXT: s_lshl_b32 s19, s10, 31
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
+; GFX11-NEXT: s_and_not1_b32 s10, 0x7f, s16
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
+; GFX11-NEXT: s_not_b32 s19, s16
+; GFX11-NEXT: s_sub_i32 s21, s10, 64
+; GFX11-NEXT: s_sub_i32 s16, 64, s10
+; GFX11-NEXT: s_cmp_lt_u32 s10, 64
+; GFX11-NEXT: s_cselect_b32 s26, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s10, 0
+; GFX11-NEXT: s_cselect_b32 s27, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s19
+; GFX11-NEXT: s_lshl_b64 s[16:17], s[8:9], s16
+; GFX11-NEXT: s_lshr_b64 s[22:23], s[8:9], s19
+; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s21
+; GFX11-NEXT: s_cmp_lg_u32 s26, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
+; GFX11-NEXT: s_cmp_lg_u32 s27, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
+; GFX11-NEXT: s_cmp_lg_u32 s26, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[22:23], 0
+; GFX11-NEXT: s_and_b32 s10, s20, 0x7f
+; GFX11-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GFX11-NEXT: s_sub_i32 s19, s10, 64
+; GFX11-NEXT: s_sub_i32 s8, 64, s10
+; GFX11-NEXT: s_cmp_lt_u32 s10, 64
+; GFX11-NEXT: s_cselect_b32 s21, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s10, 0
+; GFX11-NEXT: s_cselect_b32 s22, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s20
+; GFX11-NEXT: s_lshl_b64 s[16:17], s[4:5], s20
+; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s19
+; GFX11-NEXT: s_cmp_lg_u32 s21, 0
+; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GFX11-NEXT: s_cmp_lg_u32 s22, 0
+; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
+; GFX11-NEXT: s_lshl_b32 s19, s14, 31
+; GFX11-NEXT: s_and_not1_b32 s12, 0x7f, s20
+; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[18:19]
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
+; GFX11-NEXT: s_not_b32 s16, s20
+; GFX11-NEXT: s_sub_i32 s18, s12, 64
+; GFX11-NEXT: s_sub_i32 s14, 64, s12
+; GFX11-NEXT: s_cmp_lt_u32 s12, 64
+; GFX11-NEXT: s_cselect_b32 s19, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s12, 0
+; GFX11-NEXT: s_cselect_b32 s20, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[12:13], s[4:5], s16
+; GFX11-NEXT: s_lshl_b64 s[14:15], s[8:9], s14
+; GFX11-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
+; GFX11-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s18
+; GFX11-NEXT: s_cmp_lg_u32 s19, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
+; GFX11-NEXT: s_cmp_lg_u32 s20, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
+; GFX11-NEXT: s_cmp_lg_u32 s19, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
+; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshl_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s17, s16, 0x7f
@@ -7971,7 +7490,6 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshl_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s17, s16, 0x7f
@@ -8060,95 +7578,6 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX10-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshl_v2i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s17, s16, 0x7f
-; GFX11-NEXT: s_mov_b32 s18, 0
-; GFX11-NEXT: s_sub_i32 s19, s17, 64
-; GFX11-NEXT: s_sub_i32 s21, 64, s17
-; GFX11-NEXT: s_cmp_lt_u32 s17, 64
-; GFX11-NEXT: s_cselect_b32 s28, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s17, 0
-; GFX11-NEXT: s_cselect_b32 s17, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[22:23], s[0:1], s21
-; GFX11-NEXT: s_lshl_b64 s[24:25], s[2:3], s16
-; GFX11-NEXT: s_lshl_b64 s[26:27], s[0:1], s16
-; GFX11-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s19
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_cselect_b64 s[24:25], s[26:27], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s17, 0
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
-; GFX11-NEXT: s_lshl_b32 s19, s10, 31
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
-; GFX11-NEXT: s_and_not1_b32 s10, 0x7f, s16
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
-; GFX11-NEXT: s_not_b32 s19, s16
-; GFX11-NEXT: s_sub_i32 s21, s10, 64
-; GFX11-NEXT: s_sub_i32 s16, 64, s10
-; GFX11-NEXT: s_cmp_lt_u32 s10, 64
-; GFX11-NEXT: s_cselect_b32 s26, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s10, 0
-; GFX11-NEXT: s_cselect_b32 s27, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s19
-; GFX11-NEXT: s_lshl_b64 s[16:17], s[8:9], s16
-; GFX11-NEXT: s_lshr_b64 s[22:23], s[8:9], s19
-; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s21
-; GFX11-NEXT: s_cmp_lg_u32 s26, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
-; GFX11-NEXT: s_cmp_lg_u32 s27, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
-; GFX11-NEXT: s_cmp_lg_u32 s26, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[22:23], 0
-; GFX11-NEXT: s_and_b32 s10, s20, 0x7f
-; GFX11-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX11-NEXT: s_sub_i32 s19, s10, 64
-; GFX11-NEXT: s_sub_i32 s8, 64, s10
-; GFX11-NEXT: s_cmp_lt_u32 s10, 64
-; GFX11-NEXT: s_cselect_b32 s21, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s10, 0
-; GFX11-NEXT: s_cselect_b32 s22, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s20
-; GFX11-NEXT: s_lshl_b64 s[16:17], s[4:5], s20
-; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s19
-; GFX11-NEXT: s_cmp_lg_u32 s21, 0
-; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX11-NEXT: s_cmp_lg_u32 s22, 0
-; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
-; GFX11-NEXT: s_lshl_b32 s19, s14, 31
-; GFX11-NEXT: s_and_not1_b32 s12, 0x7f, s20
-; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[18:19]
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
-; GFX11-NEXT: s_not_b32 s16, s20
-; GFX11-NEXT: s_sub_i32 s18, s12, 64
-; GFX11-NEXT: s_sub_i32 s14, 64, s12
-; GFX11-NEXT: s_cmp_lt_u32 s12, 64
-; GFX11-NEXT: s_cselect_b32 s19, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s12, 0
-; GFX11-NEXT: s_cselect_b32 s20, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[12:13], s[4:5], s16
-; GFX11-NEXT: s_lshl_b64 s[14:15], s[8:9], s14
-; GFX11-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
-; GFX11-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s18
-; GFX11-NEXT: s_cmp_lg_u32 s19, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
-; GFX11-NEXT: s_cmp_lg_u32 s20, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_cmp_lg_u32 s19, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
-; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
}
@@ -8157,185 +7586,282 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-LABEL: v_fshl_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v19, 0x7f, v16
-; GFX6-NEXT: v_not_b32_e32 v18, 63
-; GFX6-NEXT: v_sub_i32_e32 v23, vcc, 64, v19
-; GFX6-NEXT: v_add_i32_e32 v27, vcc, v19, v18
-; GFX6-NEXT: v_lshr_b64 v[23:24], v[0:1], v23
-; GFX6-NEXT: v_lshl_b64 v[25:26], v[2:3], v19
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[0:1], v19
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v27
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19
-; GFX6-NEXT: v_or_b32_e32 v19, v23, v25
-; GFX6-NEXT: v_or_b32_e32 v23, v24, v26
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v23, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v19, v0, v2, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v18, 0x7f, v16
+; GFX6-NEXT: v_not_b32_e32 v17, 63
+; GFX6-NEXT: v_sub_i32_e32 v21, vcc, 64, v18
+; GFX6-NEXT: v_add_i32_e32 v25, vcc, v18, v17
+; GFX6-NEXT: v_lshr_b64 v[21:22], v[0:1], v21
+; GFX6-NEXT: v_lshl_b64 v[23:24], v[2:3], v16
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[0:1], v16
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v25
+; GFX6-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX6-NEXT: v_or_b32_e32 v22, v22, v24
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v21, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v22, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v21, v0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v22, v1, v3, s[4:5]
; GFX6-NEXT: v_lshr_b64 v[0:1], v[8:9], 1
-; GFX6-NEXT: v_mov_b32_e32 v17, 0x7f
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 31, v10
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshr_b64 v[2:3], v[10:11], 1
-; GFX6-NEXT: v_bfi_b32 v10, v16, 0, v17
-; GFX6-NEXT: v_cndmask_b32_e32 v24, 0, v21, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v25, 0, v22, vcc
-; GFX6-NEXT: v_add_i32_e32 v16, vcc, v10, v18
-; GFX6-NEXT: v_sub_i32_e32 v21, vcc, 64, v10
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v10
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
+; GFX6-NEXT: v_not_b32_e32 v10, v16
+; GFX6-NEXT: v_and_b32_e32 v8, 0x7f, v10
+; GFX6-NEXT: v_cndmask_b32_e32 v23, 0, v18, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v24, 0, v19, vcc
+; GFX6-NEXT: v_add_i32_e32 v16, vcc, v8, v17
+; GFX6-NEXT: v_sub_i32_e32 v18, vcc, 64, v8
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], v10
; GFX6-NEXT: v_lshr_b64 v[10:11], v[0:1], v10
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v21
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[2:3], v18
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v16
-; GFX6-NEXT: v_or_b32_e32 v10, v10, v21
-; GFX6-NEXT: v_or_b32_e32 v11, v11, v22
+; GFX6-NEXT: v_or_b32_e32 v10, v10, v18
+; GFX6-NEXT: v_or_b32_e32 v11, v11, v19
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GFX6-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX6-NEXT: v_and_b32_e32 v8, 0x7f, v20
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v16
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v8
+; GFX6-NEXT: v_add_i32_e32 v16, vcc, v8, v17
; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v10
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[6:7], v16
-; GFX6-NEXT: v_or_b32_e32 v2, v19, v2
-; GFX6-NEXT: v_add_i32_e32 v19, vcc, v16, v18
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v16
-; GFX6-NEXT: v_or_b32_e32 v16, v10, v21
-; GFX6-NEXT: v_or_b32_e32 v21, v11, v22
-; GFX6-NEXT: v_lshl_b64 v[10:11], v[4:5], v19
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v8, v10, v16, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v9, v11, v21, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[12:13], 1
-; GFX6-NEXT: v_lshlrev_b32_e32 v10, 31, v14
-; GFX6-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX6-NEXT: v_lshr_b64 v[10:11], v[14:15], 1
-; GFX6-NEXT: v_bfi_b32 v14, v20, 0, v17
-; GFX6-NEXT: v_add_i32_e32 v18, vcc, v14, v18
-; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v14
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
-; GFX6-NEXT: v_lshr_b64 v[12:13], v[10:11], v14
-; GFX6-NEXT: v_lshr_b64 v[14:15], v[8:9], v14
-; GFX6-NEXT: v_lshl_b64 v[16:17], v[10:11], v16
-; GFX6-NEXT: v_lshr_b64 v[10:11], v[10:11], v18
-; GFX6-NEXT: v_or_b32_e32 v14, v14, v16
-; GFX6-NEXT: v_or_b32_e32 v15, v15, v17
-; GFX6-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v8, v10, v8, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
-; GFX6-NEXT: v_or_b32_e32 v0, v24, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v25, v1
-; GFX6-NEXT: v_or_b32_e32 v3, v23, v3
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v8
-; GFX6-NEXT: v_or_b32_e32 v5, v5, v9
-; GFX6-NEXT: v_or_b32_e32 v6, v6, v10
-; GFX6-NEXT: v_or_b32_e32 v7, v7, v11
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[6:7], v20
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v20
+; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], v16
+; GFX6-NEXT: v_or_b32_e32 v10, v10, v18
+; GFX6-NEXT: v_or_b32_e32 v11, v11, v19
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX6-NEXT: v_or_b32_e32 v2, v21, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v19, v4, v6, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v21, v5, v7, s[4:5]
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[12:13], 1
+; GFX6-NEXT: v_lshlrev_b32_e32 v6, 31, v14
+; GFX6-NEXT: v_not_b32_e32 v10, v20
+; GFX6-NEXT: v_cndmask_b32_e32 v16, 0, v8, vcc
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], 1
+; GFX6-NEXT: v_and_b32_e32 v8, 0x7f, v10
+; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v9, vcc
+; GFX6-NEXT: v_add_i32_e32 v14, vcc, v8, v17
+; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 64, v8
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], v10
+; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v10
+; GFX6-NEXT: v_lshl_b64 v[12:13], v[6:7], v12
+; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], v14
+; GFX6-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX6-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
+; GFX6-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX6-NEXT: v_or_b32_e32 v3, v22, v3
+; GFX6-NEXT: v_or_b32_e32 v4, v16, v4
+; GFX6-NEXT: v_or_b32_e32 v5, v18, v5
+; GFX6-NEXT: v_or_b32_e32 v6, v19, v6
+; GFX6-NEXT: v_or_b32_e32 v7, v21, v7
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fshl_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v19, 0x7f, v16
-; GFX8-NEXT: v_not_b32_e32 v18, 63
-; GFX8-NEXT: v_sub_u32_e32 v23, vcc, 64, v19
-; GFX8-NEXT: v_add_u32_e32 v27, vcc, v19, v18
-; GFX8-NEXT: v_lshrrev_b64 v[23:24], v23, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[25:26], v19, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], v19, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v27, v[0:1]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19
-; GFX8-NEXT: v_or_b32_e32 v19, v23, v25
-; GFX8-NEXT: v_or_b32_e32 v23, v24, v26
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v23, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v0, v2, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v18, 0x7f, v16
+; GFX8-NEXT: v_not_b32_e32 v17, 63
+; GFX8-NEXT: v_sub_u32_e32 v21, vcc, 64, v18
+; GFX8-NEXT: v_add_u32_e32 v25, vcc, v18, v17
+; GFX8-NEXT: v_lshrrev_b64 v[21:22], v21, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[23:24], v16, v[2:3]
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], v16, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v25, v[0:1]
+; GFX8-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX8-NEXT: v_or_b32_e32 v22, v22, v24
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v21, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v22, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v1, v3, s[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[8:9]
-; GFX8-NEXT: v_mov_b32_e32 v17, 0x7f
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v10
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[10:11]
-; GFX8-NEXT: v_bfi_b32 v10, v16, 0, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v21, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v25, 0, v22, vcc
-; GFX8-NEXT: v_add_u32_e32 v16, vcc, v10, v18
-; GFX8-NEXT: v_sub_u32_e32 v21, vcc, 64, v10
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v10
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
+; GFX8-NEXT: v_not_b32_e32 v10, v16
+; GFX8-NEXT: v_and_b32_e32 v8, 0x7f, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v23, 0, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v19, vcc
+; GFX8-NEXT: v_add_u32_e32 v16, vcc, v8, v17
+; GFX8-NEXT: v_sub_u32_e32 v18, vcc, 64, v8
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; GFX8-NEXT: v_lshrrev_b64 v[8:9], v10, v[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], v21, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], v18, v[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v16, v[2:3]
-; GFX8-NEXT: v_or_b32_e32 v10, v10, v21
-; GFX8-NEXT: v_or_b32_e32 v11, v11, v22
+; GFX8-NEXT: v_or_b32_e32 v10, v10, v18
+; GFX8-NEXT: v_or_b32_e32 v11, v11, v19
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GFX8-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
+; GFX8-NEXT: v_and_b32_e32 v8, 0x7f, v20
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v16
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v8
+; GFX8-NEXT: v_add_u32_e32 v16, vcc, v8, v17
; GFX8-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], v16, v[6:7]
-; GFX8-NEXT: v_or_b32_e32 v2, v19, v2
-; GFX8-NEXT: v_add_u32_e32 v19, vcc, v16, v18
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX8-NEXT: v_lshlrev_b64 v[8:9], v16, v[4:5]
-; GFX8-NEXT: v_or_b32_e32 v16, v10, v21
-; GFX8-NEXT: v_or_b32_e32 v21, v11, v22
-; GFX8-NEXT: v_lshlrev_b64 v[10:11], v19, v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v16, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v21, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX8-NEXT: v_lshlrev_b32_e32 v10, 31, v14
-; GFX8-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[14:15]
-; GFX8-NEXT: v_bfi_b32 v14, v20, 0, v17
-; GFX8-NEXT: v_add_u32_e32 v18, vcc, v14, v18
-; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v14
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
-; GFX8-NEXT: v_lshrrev_b64 v[12:13], v14, v[10:11]
-; GFX8-NEXT: v_lshrrev_b64 v[14:15], v14, v[8:9]
-; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
-; GFX8-NEXT: v_lshrrev_b64 v[10:11], v18, v[10:11]
-; GFX8-NEXT: v_or_b32_e32 v14, v14, v16
-; GFX8-NEXT: v_or_b32_e32 v15, v15, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v10, v8, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
-; GFX8-NEXT: v_or_b32_e32 v0, v24, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v25, v1
-; GFX8-NEXT: v_or_b32_e32 v3, v23, v3
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v8
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v9
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v10
-; GFX8-NEXT: v_or_b32_e32 v7, v7, v11
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], v20, v[6:7]
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], v20, v[4:5]
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; GFX8-NEXT: v_or_b32_e32 v10, v10, v18
+; GFX8-NEXT: v_or_b32_e32 v11, v11, v19
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX8-NEXT: v_or_b32_e32 v2, v21, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v4, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v5, v7, s[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[12:13]
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 31, v14
+; GFX8-NEXT: v_not_b32_e32 v10, v20
+; GFX8-NEXT: v_cndmask_b32_e32 v16, 0, v8, vcc
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX8-NEXT: v_lshrrev_b64 v[6:7], 1, v[14:15]
+; GFX8-NEXT: v_and_b32_e32 v8, 0x7f, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v9, vcc
+; GFX8-NEXT: v_add_u32_e32 v14, vcc, v8, v17
+; GFX8-NEXT: v_sub_u32_e32 v12, vcc, 64, v8
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v10, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]
+; GFX8-NEXT: v_lshlrev_b64 v[12:13], v12, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[6:7], v14, v[6:7]
+; GFX8-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX8-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
+; GFX8-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX8-NEXT: v_or_b32_e32 v3, v22, v3
+; GFX8-NEXT: v_or_b32_e32 v4, v16, v4
+; GFX8-NEXT: v_or_b32_e32 v5, v18, v5
+; GFX8-NEXT: v_or_b32_e32 v6, v19, v6
+; GFX8-NEXT: v_or_b32_e32 v7, v21, v7
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshl_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v16
+; GFX11-NEXT: v_lshlrev_b64 v[17:18], v16, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[23:24], v16, v[2:3]
+; GFX11-NEXT: v_not_b32_e32 v29, v16
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
+; GFX11-NEXT: v_sub_nc_u32_e32 v21, 64, v19
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
+; GFX11-NEXT: v_add_nc_u32_e32 v25, 0xffffffc0, v19
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v19
+; GFX11-NEXT: v_lshl_or_b32 v9, v10, 31, v9
+; GFX11-NEXT: v_lshrrev_b64 v[21:22], v21, v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v25, v[0:1]
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; GFX11-NEXT: v_lshrrev_b64 v[25:26], v29, v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e32 v31, 0, v17, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v0, v22, v24
+; GFX11-NEXT: v_and_b32_e32 v30, 0x7f, v29
+; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v30
+; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v30
+; GFX11-NEXT: v_lshlrev_b64 v[27:28], v16, v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v23, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v1, v0, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v30
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v30
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v29, v[10:11]
+; GFX11-NEXT: v_or_b32_e32 v19, v25, v27
+; GFX11-NEXT: v_or_b32_e32 v22, v26, v28
+; GFX11-NEXT: v_not_b32_e32 v26, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v19, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v17, v22, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v22, v23, v3, s0
+; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, v1, s1
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v20, v[6:7]
+; GFX11-NEXT: v_or_b32_e32 v0, v31, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v23
+; GFX11-NEXT: v_or_b32_e32 v1, v18, v3
+; GFX11-NEXT: v_and_b32_e32 v27, 0x7f, v26
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 31, v9
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v27
+; GFX11-NEXT: v_lshlrev_b64 v[12:13], v20, v[4:5]
+; GFX11-NEXT: v_add_nc_u32_e32 v20, 0xffffffc0, v27
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v27
+; GFX11-NEXT: v_or_b32_e32 v10, v2, v10
+; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
+; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
+; GFX11-NEXT: v_or_b32_e32 v2, v21, v24
+; GFX11-NEXT: v_or_b32_e32 v11, v3, v11
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v27
+; GFX11-NEXT: v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v13, 0, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v10, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v20, v[14:15]
+; GFX11-NEXT: v_or_b32_e32 v10, v16, v18
+; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
+; GFX11-NEXT: v_lshrrev_b64 v[10:11], v26, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v8, s2
+; GFX11-NEXT: v_or_b32_e32 v3, v22, v25
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v4, v9, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v10, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v11, s1
+; GFX11-NEXT: v_or_b32_e32 v4, v12, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v13, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -8423,7 +7949,6 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_or_b32_e32 v6, v16, v6
; GFX9-NEXT: v_or_b32_e32 v7, v12, v7
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshl_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -8510,104 +8035,6 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshl_v2i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v16
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX11-NEXT: v_bfi_b32 v29, v16, 0, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[17:18], v19, v[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v19
-; GFX11-NEXT: v_lshl_or_b32 v9, v10, 31, v9
-; GFX11-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v29
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v29
-; GFX11-NEXT: v_cndmask_b32_e32 v30, 0, v17, vcc_lo
-; GFX11-NEXT: v_sub_nc_u32_e32 v21, 64, v19
-; GFX11-NEXT: v_dual_cndmask_b32 v18, 0, v18 :: v_dual_add_nc_u32 v25, 0xffffffc0, v19
-; GFX11-NEXT: v_lshlrev_b64 v[23:24], v19, v[2:3]
-; GFX11-NEXT: v_lshlrev_b64 v[27:28], v16, v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshrrev_b64 v[21:22], v21, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v25, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], v29, v[8:9]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v29
-; GFX11-NEXT: v_or_b32_e32 v19, v25, v27
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v0, v22, v24
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v23, v[10:11]
-; GFX11-NEXT: v_or_b32_e32 v22, v26, v28
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v23, v1, v0, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
-; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v19, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v29, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v17, v22, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v23, v3, s0
-; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
-; GFX11-NEXT: v_bfi_b32 v20, v20, 0, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v0, s1
-; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v23
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v20
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX11-NEXT: v_lshlrev_b64 v[12:13], v23, v[4:5]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
-; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v30, v2
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
-; GFX11-NEXT: v_lshl_or_b32 v9, v14, 31, v9
-; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v1, v18, v3
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v10, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v23, v[6:7]
-; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
-; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v10, v2, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX11-NEXT: v_or_b32_e32 v2, v21, v24
-; GFX11-NEXT: v_or_b32_e32 v11, v3, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v10, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[3:4], v26, v[14:15]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
-; GFX11-NEXT: v_lshrrev_b64 v[10:11], v20, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v8, s2
-; GFX11-NEXT: v_or_b32_e32 v3, v22, v25
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v4, v9, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v11, s1
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
}
@@ -8644,3 +8071,5 @@ declare i128 @llvm.fshl.i128(i128, i128, i128) #0
declare <2 x i128> @llvm.fshl.v2i128(<2 x i128>, <2 x i128>, <2 x i128>) #0
attributes #0 = { nounwind readnone speculatable willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 6ae2b9f9e8e1b..9fcaa411b46ee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshr_i7:
@@ -79,6 +79,46 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-NEXT: s_mul_i32 s4, s3, -7
+; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s3, s3, s4
+; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_i32 s3, s3, -7
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s2, 7
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_add_i32 s4, s2, -7
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_cmp_ge_u32 s2, 7
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_add_i32 s4, s2, -7
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_sub_i32 s3, 6, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
+; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
@@ -104,15 +144,15 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
; GFX9-NEXT: s_sub_i32 s3, 6, s2
+; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_and_b32 s3, s3, 0x7f
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
@@ -137,56 +177,16 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_add_i32 s4, s2, -7
; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: s_sub_i32 s3, 6, s2
; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
+; GFX10-NEXT: s_sub_i32 s3, 6, s2
+; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
+; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i7:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-NEXT: s_mul_i32 s4, s3, -7
-; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s4
-; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_i32 s3, s3, -7
-; GFX11-NEXT: s_add_i32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s2, 7
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_add_i32 s4, s2, -7
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_ge_u32 s2, 7
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_add_i32 s4, s2, -7
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_sub_i32 s3, 6, s2
-; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
ret i7 %result
}
@@ -217,8 +217,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX6-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
@@ -249,13 +247,46 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i7:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v1.l, 0x7f, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: s_mul_i32 s1, s0, -7
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-NEXT: v_add_nc_u32_e32 v2, -7, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_sub_nc_u16 v0.h, 6, v2.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v2.l, v1.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -285,7 +316,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -315,46 +345,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_lshlrev_b16 v0, v3, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i7:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7f, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-TRUE16-NEXT: s_mul_i32 s1, s0, -7
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_mul_hi_u32 v5, v2, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, 6, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0x7f, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x7f, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i7:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -420,39 +410,39 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_and_not1_b32 s3, 7, s2
+; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i8:
; GFX9: ; %bb.0:
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i8:
; GFX10: ; %bb.0:
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_andn2_b32 s3, 7, s2
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_not1_b32 s3, 7, s2
-; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
ret i8 %result
}
@@ -482,6 +472,20 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b16 v0.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v1.h, v2.l, 7
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -493,7 +497,6 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -506,22 +509,6 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX10-NEXT: v_lshlrev_b16 v0, v3, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -556,30 +543,30 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i8_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 4
; GFX9-NEXT: s_lshr_b32 s1, s1, 4
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 4
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 4
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i8_4:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_lshr_b32 s1, s1, 4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
ret i8 %result
}
@@ -602,6 +589,15 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i8_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -610,7 +606,6 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -619,17 +614,6 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 4, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i8_4:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 4, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i8_4:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -659,30 +643,30 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i8_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 3
+; GFX11-NEXT: s_lshr_b32 s1, s1, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, 3
; GFX9-NEXT: s_lshr_b32 s1, s1, 5
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, 3
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshr_b32 s1, s1, 5
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i8_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 3
-; GFX11-NEXT: s_lshr_b32 s1, s1, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
ret i8 %result
}
@@ -705,6 +689,15 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i8_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 3, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 5, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -713,7 +706,6 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -722,17 +714,6 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 5, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i8_5:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 3, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 5, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i8_5:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -796,23 +777,50 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s2
+; GFX11-NEXT: s_lshr_b32 s6, s2, 8
+; GFX11-NEXT: s_lshl_b32 s0, s0, s5
+; GFX11-NEXT: s_lshl_b32 s3, s3, 1
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s6
+; GFX11-NEXT: s_and_b32 s6, s6, 7
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s3, s3, s5
+; GFX11-NEXT: s_lshr_b32 s4, s4, s6
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_or_b32 s2, s3, s4
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_and_b32 s1, s2, 0xff
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v2i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshr_b32 s4, s1, 8
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshr_b32 s5, s2, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s6, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_lshl_b32 s1, s3, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s5
+; GFX9-NEXT: s_and_b32 s3, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s2, s5, 7
-; GFX9-NEXT: s_and_b32 s3, s4, 0xff
+; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshr_b32 s2, s3, s2
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
@@ -820,21 +828,22 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
+; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s2
; GFX10-NEXT: s_lshr_b32 s6, s2, 8
+; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshl_b32 s3, s3, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s6
; GFX10-NEXT: s_and_b32 s6, s6, 7
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s3, s3, s5
; GFX10-NEXT: s_lshr_b32 s4, s4, s6
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
@@ -845,32 +854,6 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_v2i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_lshr_b32 s4, s1, 8
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_not1_b32 s5, 7, s2
-; GFX11-NEXT: s_lshr_b32 s6, s2, 8
-; GFX11-NEXT: s_lshl_b32 s0, s0, s5
-; GFX11-NEXT: s_lshl_b32 s3, s3, 1
-; GFX11-NEXT: s_and_not1_b32 s5, 7, s6
-; GFX11-NEXT: s_and_b32 s6, s6, 7
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s3, s3, s5
-; GFX11-NEXT: s_lshr_b32 s4, s4, s6
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_or_b32 s2, s3, s4
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_and_b32 s1, s2, 0xff
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%amt = bitcast i16 %amt.arg to <2 x i8>
@@ -930,6 +913,37 @@ define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-NEXT: v_xor_b16 v1.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_xor_b16 v0.h, v3.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v2.h, 1, v4.l
+; GFX11-NEXT: v_and_b16 v3.l, v3.l, 7
+; GFX11-NEXT: v_and_b16 v3.h, 0xff, v5.l
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
+; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: v_and_b16 v1.h, v1.h, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, v0.h, v2.h
+; GFX11-NEXT: v_lshrrev_b16 v2.h, v3.l, v3.h
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v2.l, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b16 v0.h, v0.h, v2.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -954,7 +968,6 @@ define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -981,39 +994,6 @@ define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_v2i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-TRUE16-NEXT: v_xor_b16 v1.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v3.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v4.l
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v3.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v5.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v1.h, 7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v0.h, v2.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.h, v3.l, v3.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v2.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_v2i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1153,36 +1133,89 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
+; GFX11-NEXT: s_lshr_b32 s5, s1, 8
+; GFX11-NEXT: s_lshr_b32 s7, s2, 8
+; GFX11-NEXT: s_lshl_b32 s9, s0, 1
+; GFX11-NEXT: s_and_not1_b32 s10, 7, s2
+; GFX11-NEXT: s_and_b32 s11, s2, 7
+; GFX11-NEXT: s_and_b32 s12, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s9, s9, s10
+; GFX11-NEXT: s_lshr_b32 s10, s12, s11
+; GFX11-NEXT: s_lshl_b32 s3, s3, 1
+; GFX11-NEXT: s_and_not1_b32 s11, 7, s7
+; GFX11-NEXT: s_and_b32 s7, s7, 7
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_lshr_b32 s4, s0, 24
+; GFX11-NEXT: s_lshr_b32 s6, s1, 24
+; GFX11-NEXT: s_lshr_b32 s8, s2, 24
+; GFX11-NEXT: s_lshl_b32 s3, s3, s11
+; GFX11-NEXT: s_lshr_b32 s5, s5, s7
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_or_b32 s3, s3, s5
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s2
+; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, s5
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s4, 1
+; GFX11-NEXT: s_and_not1_b32 s4, 7, s8
+; GFX11-NEXT: s_and_b32 s5, s8, 7
+; GFX11-NEXT: s_lshl_b32 s2, s2, s4
+; GFX11-NEXT: s_lshr_b32 s4, s6, s5
+; GFX11-NEXT: s_or_b32 s7, s9, s10
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_or_b32 s1, s2, s4
+; GFX11-NEXT: s_and_b32 s2, s3, 0xff
+; GFX11-NEXT: s_and_b32 s3, s7, 0xff
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_or_b32 s0, s2, s0
+; GFX11-NEXT: s_lshl_b32 s1, s1, 24
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v4i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s3, s0, 8
-; GFX9-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-NEXT: s_lshr_b32 s5, s0, 24
; GFX9-NEXT: s_lshr_b32 s6, s1, 8
; GFX9-NEXT: s_lshr_b32 s7, s1, 16
; GFX9-NEXT: s_lshr_b32 s8, s1, 24
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_lshr_b32 s3, s0, 8
+; GFX9-NEXT: s_lshr_b32 s4, s0, 16
+; GFX9-NEXT: s_lshr_b32 s5, s0, 24
; GFX9-NEXT: s_lshr_b32 s9, s2, 8
; GFX9-NEXT: s_lshr_b32 s10, s2, 16
; GFX9-NEXT: s_lshr_b32 s11, s2, 24
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_andn2_b32 s12, 7, s2
; GFX9-NEXT: s_and_b32 s2, s2, 7
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s12
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_lshl_b32 s1, s3, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s9
+; GFX9-NEXT: s_and_b32 s3, s6, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s2, s9, 7
-; GFX9-NEXT: s_and_b32 s3, s6, 0xff
+; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshr_b32 s2, s3, s2
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s2, s4, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s10
+; GFX9-NEXT: s_and_b32 s4, s7, 0xff
; GFX9-NEXT: s_lshl_b32 s2, s2, s3
; GFX9-NEXT: s_and_b32 s3, s10, 7
-; GFX9-NEXT: s_and_b32 s4, s7, 0xff
+; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshr_b32 s3, s4, s3
; GFX9-NEXT: s_or_b32 s2, s2, s3
; GFX9-NEXT: s_lshl_b32 s3, s5, 1
@@ -1202,19 +1235,20 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshl_b32 s1, s1, 24
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v4i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshr_b32 s8, s1, 24
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s9, s2, 8
; GFX10-NEXT: s_lshr_b32 s10, s2, 16
; GFX10-NEXT: s_lshr_b32 s11, s2, 24
; GFX10-NEXT: s_andn2_b32 s12, 7, s2
; GFX10-NEXT: s_and_b32 s2, s2, 7
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshr_b32 s5, s0, 24
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
@@ -1222,18 +1256,19 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX10-NEXT: s_lshl_b32 s2, s3, 1
; GFX10-NEXT: s_andn2_b32 s3, 7, s9
; GFX10-NEXT: s_and_b32 s9, s9, 7
-; GFX10-NEXT: s_and_b32 s6, s6, 0xff
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_lshl_b32 s0, s0, s12
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
; GFX10-NEXT: s_lshr_b32 s3, s6, s9
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: s_or_b32 s1, s2, s3
; GFX10-NEXT: s_lshl_b32 s2, s4, 1
+; GFX10-NEXT: s_and_b32 s4, s7, 0xff
; GFX10-NEXT: s_andn2_b32 s3, 7, s10
-; GFX10-NEXT: s_and_b32 s4, s10, 7
-; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: s_and_b32 s6, s10, 7
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
-; GFX10-NEXT: s_lshr_b32 s3, s6, s4
+; GFX10-NEXT: s_lshr_b32 s3, s4, s6
; GFX10-NEXT: s_lshl_b32 s4, s5, 1
; GFX10-NEXT: s_andn2_b32 s5, 7, s11
; GFX10-NEXT: s_and_b32 s6, s11, 7
@@ -1252,108 +1287,6 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX10-NEXT: s_lshl_b32 s1, s2, 24
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshr_v4i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s2, 8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s9, s0, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s10, 7, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s11, s2, 7
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s1, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s9, s9, s10
-; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s12, s11
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s11, 7, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s7, 7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 24
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s1, 24
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s2, 24
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, s11
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, s7
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s3, s5
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s5, 7, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 7
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s4, 1
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s4, 7, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s8, 7
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s6, s5
-; GFX11-TRUE16-NEXT: s_or_b32 s7, s9, s10
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s7, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: s_fshr_v4i8:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s1, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s1, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s1, 24
-; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s2, 8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s2, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s2, 24
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s12, 7, s2
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 7
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s0, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s0, 24
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s3, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s3, 7, s9
-; GFX11-FAKE16-NEXT: s_and_b32 s9, s9, 7
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s6, s9
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s4, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s3, 7, s10
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s10, 7
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s7, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s6, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s5, 1
-; GFX11-FAKE16-NEXT: s_and_not1_b32 s5, 7, s11
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s11, 7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, s5
-; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s8, s6
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s3, 0xff
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%amt = bitcast i32 %amt.arg to <4 x i8>
@@ -1462,6 +1395,59 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v0
+; GFX11-NEXT: v_xor_b16 v3.l, v5.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v4.l, 1, v4.l
+; GFX11-NEXT: v_and_b16 v4.h, v5.l, 7
+; GFX11-NEXT: v_and_b16 v5.l, 0xff, v7.l
+; GFX11-NEXT: v_xor_b16 v5.h, v2.h, -1
+; GFX11-NEXT: v_and_b16 v3.l, v3.l, 7
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 24, v1
+; GFX11-NEXT: v_xor_b16 v3.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: v_and_b16 v2.h, v2.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v3.l, v3.l, v4.l
+; GFX11-NEXT: v_lshrrev_b16 v4.l, v4.h, v5.l
+; GFX11-NEXT: v_xor_b16 v4.h, v9.l, -1
+; GFX11-NEXT: v_and_b16 v5.l, v5.h, 7
+; GFX11-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-NEXT: v_lshlrev_b16 v5.h, 1, v6.l
+; GFX11-NEXT: v_and_b16 v6.l, v9.l, 7
+; GFX11-NEXT: v_and_b16 v4.h, v4.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: v_and_b16 v3.h, v3.h, 7
+; GFX11-NEXT: v_or_b16 v4.l, v3.l, v4.l
+; GFX11-NEXT: v_lshlrev_b16 v0.h, v5.l, v0.h
+; GFX11-NEXT: v_lshrrev_b16 v1.h, v2.h, v1.h
+; GFX11-NEXT: v_lshlrev_b16 v2.h, v4.h, v5.h
+; GFX11-NEXT: v_lshrrev_b16 v3.l, v6.l, v8.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v2.l, v1.l
+; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-NEXT: v_or_b16 v2.l, v0.h, v1.h
+; GFX11-NEXT: v_or_b16 v3.l, v2.h, v3.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 24, v3
+; GFX11-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1510,7 +1496,6 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1563,61 +1548,6 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_v4i8:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX11-TRUE16-NEXT: v_xor_b16 v3.l, v5.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 1, v4.l
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, v5.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v7.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v5.h, v2.h, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v3.l, 7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 24, v1
-; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v2.h, 7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, v3.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.l, v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v4.h, v9.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, v5.h, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 1, v6.l
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, v9.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, v4.h, 7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 7
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v3.h, v3.h, 7
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v3.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v5.l, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, v4.h, v5.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.l, v6.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v2.h, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX11-TRUE16-NEXT: v_or3_b32 v0, v0, v1, v2
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_v4i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1683,76 +1613,79 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
}
define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) {
-; GFX6-LABEL: s_fshr_i24:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s3, v0
-; GFX6-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX6-NEXT: v_mul_hi_u32 v0, v0, s4
-; GFX6-NEXT: v_readfirstlane_b32 s4, v0
-; GFX6-NEXT: s_add_i32 s3, s3, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s3
-; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s3, v0
-; GFX6-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX6-NEXT: s_add_i32 s2, s2, s3
-; GFX6-NEXT: s_cmp_ge_u32 s2, 24
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_sub_i32 s4, s2, 24
-; GFX6-NEXT: s_cmp_lg_u32 s3, 0
-; GFX6-NEXT: s_cselect_b32 s2, s4, s2
-; GFX6-NEXT: s_cmp_ge_u32 s2, 24
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_sub_i32 s4, s2, 24
-; GFX6-NEXT: s_cmp_lg_u32 s3, 0
-; GFX6-NEXT: s_cselect_b32 s2, s4, s2
-; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffffff
-; GFX6-NEXT: s_sub_i32 s3, 23, s2
-; GFX6-NEXT: s_lshl_b32 s0, s0, s3
-; GFX6-NEXT: s_lshr_b32 s1, s1, s2
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i24:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4
-; GFX8-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8-NEXT: s_add_i32 s3, s3, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX8-NEXT: s_add_i32 s2, s2, s3
-; GFX8-NEXT: s_cmp_ge_u32 s2, 24
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_sub_i32 s4, s2, 24
-; GFX8-NEXT: s_cmp_lg_u32 s3, 0
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_cmp_ge_u32 s2, 24
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_sub_i32 s4, s2, 24
-; GFX8-NEXT: s_cmp_lg_u32 s3, 0
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff
-; GFX8-NEXT: s_sub_i32 s3, 23, s2
-; GFX8-NEXT: s_lshl_b32 s0, s0, s3
-; GFX8-NEXT: s_lshr_b32 s1, s1, s2
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i24:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: s_and_b32 s2, s2, 0xffffff
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s3, v0
+; GCN-NEXT: s_mul_i32 s4, s3, 0xffffffe8
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s4
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: s_add_i32 s3, s3, s4
+; GCN-NEXT: v_mov_b32_e32 v0, s3
+; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
+; GCN-NEXT: v_readfirstlane_b32 s3, v0
+; GCN-NEXT: s_mulk_i32 s3, 0xffe8
+; GCN-NEXT: s_add_i32 s2, s2, s3
+; GCN-NEXT: s_cmp_ge_u32 s2, 24
+; GCN-NEXT: s_cselect_b32 s3, 1, 0
+; GCN-NEXT: s_sub_i32 s4, s2, 24
+; GCN-NEXT: s_cmp_lg_u32 s3, 0
+; GCN-NEXT: s_cselect_b32 s2, s4, s2
+; GCN-NEXT: s_cmp_ge_u32 s2, 24
+; GCN-NEXT: s_cselect_b32 s3, 1, 0
+; GCN-NEXT: s_sub_i32 s4, s2, 24
+; GCN-NEXT: s_cmp_lg_u32 s3, 0
+; GCN-NEXT: s_cselect_b32 s2, s4, s2
+; GCN-NEXT: s_lshl_b32 s0, s0, 1
+; GCN-NEXT: s_and_b32 s1, s1, 0xffffff
+; GCN-NEXT: s_sub_i32 s3, 23, s2
+; GCN-NEXT: s_lshl_b32 s0, s0, s3
+; GCN-NEXT: s_lshr_b32 s1, s1, s2
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: s_and_b32 s2, s2, 0xffffff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-NEXT: s_mul_i32 s4, s3, 0xffffffe8
+; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s3, s3, s4
+; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mulk_i32 s3, 0xffe8
+; GFX11-NEXT: s_add_i32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_sub_i32 s3, 23, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 0xffffff
+; GFX11-NEXT: s_lshl_b32 s0, s0, s3
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -1784,7 +1717,6 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -1816,45 +1748,6 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-NEXT: s_mul_i32 s4, s3, 0xffffffe8
-; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s4
-; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mulk_i32 s3, 0xffe8
-; GFX11-NEXT: s_add_i32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_sub_i32 s4, s2, 24
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_sub_i32 s4, s2, 24
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_sub_i32 s3, 23, s2
-; GFX11-NEXT: s_and_b32 s1, s1, 0xffffff
-; GFX11-NEXT: s_lshl_b32 s0, s0, s3
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
ret i24 %result
}
@@ -1879,15 +1772,13 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
@@ -1912,79 +1803,18 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v4
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: v_fshr_i24:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_not_b32_e32 v4, 23
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_readfirstlane_b32 s4, v3
-; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v4, v[2:3]
-; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v3, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_fshr_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v3
-; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v3, v[2:3]
-; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, v2, v1
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, v3, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-LABEL: v_fshr_i24:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2015,13 +1845,67 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v3, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fshr_i24:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_not_b32_e32 v4, 23
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
+; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
+; GFX9-NEXT: s_add_i32 s4, s4, s5
+; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v4, v[2:3]
+; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v3, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fshr_i24:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v3
+; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
+; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
+; GFX10-NEXT: s_add_i32 s4, s4, s5
+; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v3, v[2:3]
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, v3, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
ret i24 %result
}
@@ -2269,6 +2153,114 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s1, s2, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v2i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: s_lshr_b32 s6, s0, 8
+; GFX11-NEXT: s_and_b32 s8, s0, 0xff
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: s_and_b32 s10, s2, 0xff
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s9, s1, 8
+; GFX11-NEXT: s_or_b32 s6, s8, s6
+; GFX11-NEXT: s_lshr_b32 s8, s2, 8
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_and_b32 s8, s8, 0xff
+; GFX11-NEXT: s_lshr_b32 s7, s0, 24
+; GFX11-NEXT: s_lshl_b32 s8, s8, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: s_or_b32 s8, s10, s8
+; GFX11-NEXT: s_lshr_b32 s10, s4, 8
+; GFX11-NEXT: s_lshr_b32 s11, s3, 8
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_and_b32 s10, s10, 0xff
+; GFX11-NEXT: s_or_b32 s1, s7, s1
+; GFX11-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-NEXT: s_lshr_b32 s9, s2, 24
+; GFX11-NEXT: v_readfirstlane_b32 s13, v0
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_and_b32 s12, s4, 0xff
+; GFX11-NEXT: s_lshl_b32 s10, s10, 8
+; GFX11-NEXT: s_or_b32 s3, s9, s3
+; GFX11-NEXT: s_and_b32 s9, s11, 0xff
+; GFX11-NEXT: s_lshr_b32 s11, s4, 24
+; GFX11-NEXT: s_or_b32 s10, s12, s10
+; GFX11-NEXT: s_lshr_b32 s4, s4, 16
+; GFX11-NEXT: s_mul_i32 s12, s13, 0xffffffe8
+; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_mul_hi_u32 s12, s13, s12
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s10, s4
+; GFX11-NEXT: s_add_i32 s13, s13, s12
+; GFX11-NEXT: s_lshr_b32 s14, s5, 8
+; GFX11-NEXT: s_mul_hi_u32 s10, s4, s13
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_mulk_i32 s10, 0xffe8
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshl_b32 s5, s5, 8
+; GFX11-NEXT: s_add_i32 s4, s4, s10
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_or_b32 s5, s11, s5
+; GFX11-NEXT: s_and_b32 s10, s14, 0xff
+; GFX11-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s6, s0
+; GFX11-NEXT: s_cselect_b32 s11, 1, 0
+; GFX11-NEXT: s_sub_i32 s12, s4, 24
+; GFX11-NEXT: s_cmp_lg_u32 s11, 0
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s8, s2
+; GFX11-NEXT: s_cselect_b32 s4, s12, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s10
+; GFX11-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s7
+; GFX11-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-NEXT: s_sub_i32 s8, s4, 24
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s9
+; GFX11-NEXT: s_cselect_b32 s4, s8, s4
+; GFX11-NEXT: s_mul_hi_u32 s8, s5, s13
+; GFX11-NEXT: s_sub_i32 s6, 23, s4
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_mulk_i32 s8, 0xffe8
+; GFX11-NEXT: s_lshl_b32 s0, s0, s6
+; GFX11-NEXT: s_lshr_b32 s2, s2, s4
+; GFX11-NEXT: s_add_i32 s5, s5, s8
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, s5, 24
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_cselect_b32 s2, s4, s5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s2, 24
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_sub_i32 s5, s2, 24
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s2, s5, s2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 1
+; GFX11-NEXT: s_sub_i32 s4, 23, s2
+; GFX11-NEXT: s_lshr_b32 s2, s3, s2
+; GFX11-NEXT: s_lshl_b32 s1, s1, s4
+; GFX11-NEXT: s_and_b32 s3, s0, 0xff
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_bfe_u32 s2, s0, 0x80008
+; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_and_b32 s3, s1, 0xff
+; GFX11-NEXT: s_or_b32 s0, s2, s0
+; GFX11-NEXT: s_lshl_b32 s2, s3, 24
+; GFX11-NEXT: s_bfe_u32 s3, s1, 0x80010
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s9, s1, 8
@@ -2290,39 +2282,43 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s8, s8, 8
-; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_or_b32 s2, s2, s8
; GFX9-NEXT: s_and_b32 s8, s9, 0xff
-; GFX9-NEXT: s_and_b32 s3, s3, 0xff
+; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
-; GFX9-NEXT: s_lshl_b32 s3, s3, 8
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: s_and_b32 s3, s3, 0xff
; GFX9-NEXT: s_or_b32 s2, s2, s8
-; GFX9-NEXT: s_or_b32 s3, s10, s3
+; GFX9-NEXT: s_lshl_b32 s3, s3, 8
; GFX9-NEXT: s_and_b32 s8, s11, 0xff
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_or_b32 s3, s10, s3
+; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s3, s3, s8
; GFX9-NEXT: s_lshr_b32 s8, s4, 8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s8, s8, 0xff
; GFX9-NEXT: s_lshr_b32 s9, s4, 16
; GFX9-NEXT: s_lshr_b32 s10, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s8, s8, 8
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: s_lshr_b32 s11, s5, 8
; GFX9-NEXT: s_or_b32 s4, s4, s8
; GFX9-NEXT: s_and_b32 s8, s9, 0xff
-; GFX9-NEXT: s_and_b32 s5, s5, 0xff
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: s_lshr_b32 s11, s5, 8
; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
-; GFX9-NEXT: s_lshl_b32 s5, s5, 8
+; GFX9-NEXT: s_and_b32 s5, s5, 0xff
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_or_b32 s4, s4, s8
-; GFX9-NEXT: s_or_b32 s5, s10, s5
+; GFX9-NEXT: s_lshl_b32 s5, s5, 8
; GFX9-NEXT: s_and_b32 s8, s11, 0xff
+; GFX9-NEXT: s_or_b32 s5, s10, s5
+; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
; GFX9-NEXT: s_or_b32 s5, s5, s8
@@ -2333,7 +2329,9 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_mul_hi_u32 s9, s4, s8
; GFX9-NEXT: s_mulk_i32 s9, 0xffe8
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
; GFX9-NEXT: s_add_i32 s4, s4, s9
; GFX9-NEXT: s_cmp_ge_u32 s4, 24
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
@@ -2387,7 +2385,6 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_or_b32 s1, s2, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -2395,8 +2392,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
@@ -2411,74 +2408,80 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_lshr_b32 s10, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
; GFX10-NEXT: s_lshl_b32 s8, s8, 8
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: s_lshr_b32 s11, s3, 8
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_and_b32 s8, s9, 0xff
-; GFX10-NEXT: s_lshr_b32 s11, s3, 8
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
+; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
+; GFX10-NEXT: s_and_b32 s9, s11, 0xff
+; GFX10-NEXT: s_or_b32 s3, s10, s3
+; GFX10-NEXT: s_and_b32 s9, 0xffff, s9
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_lshr_b32 s8, s4, 8
-; GFX10-NEXT: s_or_b32 s3, s10, s3
-; GFX10-NEXT: s_and_b32 s9, s11, 0xff
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: s_and_b32 s8, s8, 0xff
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
; GFX10-NEXT: s_lshl_b32 s9, s9, 16
-; GFX10-NEXT: s_and_b32 s10, s4, 0xff
-; GFX10-NEXT: s_lshl_b32 s8, s8, 8
+; GFX10-NEXT: s_and_b32 s8, s8, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s3, s3, s9
; GFX10-NEXT: s_lshr_b32 s9, s4, 16
-; GFX10-NEXT: s_or_b32 s8, s10, s8
-; GFX10-NEXT: v_readfirstlane_b32 s10, v0
-; GFX10-NEXT: s_and_b32 s9, s9, 0xff
-; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX10-NEXT: s_lshl_b32 s9, s9, 16
+; GFX10-NEXT: s_lshr_b32 s10, s4, 24
+; GFX10-NEXT: s_and_b32 s4, s4, 0xff
+; GFX10-NEXT: s_lshl_b32 s8, s8, 8
; GFX10-NEXT: s_lshr_b32 s11, s5, 8
-; GFX10-NEXT: s_or_b32 s8, s8, s9
-; GFX10-NEXT: s_mul_i32 s9, s10, 0xffffffe8
+; GFX10-NEXT: s_or_b32 s4, s4, s8
+; GFX10-NEXT: s_and_b32 s8, s9, 0xff
+; GFX10-NEXT: v_readfirstlane_b32 s9, v0
+; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: s_lshl_b32 s8, s8, 16
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
-; GFX10-NEXT: s_mul_hi_u32 s9, s10, s9
-; GFX10-NEXT: s_lshr_b32 s4, s4, 24
-; GFX10-NEXT: s_add_i32 s10, s10, s9
+; GFX10-NEXT: s_or_b32 s4, s4, s8
+; GFX10-NEXT: s_mul_i32 s8, s9, 0xffffffe8
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_mul_hi_u32 s9, s8, s10
-; GFX10-NEXT: s_or_b32 s4, s4, s5
-; GFX10-NEXT: s_and_b32 s5, s11, 0xff
-; GFX10-NEXT: s_mulk_i32 s9, 0xffe8
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: s_lshl_b32 s5, s5, 16
-; GFX10-NEXT: s_add_i32 s8, s8, s9
+; GFX10-NEXT: s_mul_hi_u32 s8, s9, s8
+; GFX10-NEXT: s_or_b32 s5, s10, s5
+; GFX10-NEXT: s_add_i32 s9, s9, s8
+; GFX10-NEXT: s_and_b32 s10, s11, 0xff
+; GFX10-NEXT: s_mul_hi_u32 s8, s4, s9
+; GFX10-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX10-NEXT: s_mulk_i32 s8, 0xffe8
+; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX10-NEXT: s_lshl_b32 s10, s10, 16
+; GFX10-NEXT: s_add_i32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: s_or_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_ge_u32 s8, 24
-; GFX10-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-NEXT: s_sub_i32 s9, s8, 24
-; GFX10-NEXT: s_cmp_lg_u32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s5, s9, s8
-; GFX10-NEXT: s_cmp_ge_u32 s5, 24
+; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX10-NEXT: s_or_b32 s5, s5, s10
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: s_sub_i32 s9, s5, 24
+; GFX10-NEXT: s_sub_i32 s10, s4, 24
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s5, s9, s5
+; GFX10-NEXT: s_cselect_b32 s4, s10, s4
+; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_cselect_b32 s8, 1, 0
+; GFX10-NEXT: s_sub_i32 s10, s4, 24
+; GFX10-NEXT: s_cmp_lg_u32 s8, 0
+; GFX10-NEXT: s_cselect_b32 s4, s10, s4
; GFX10-NEXT: s_lshl_b32 s6, s6, 17
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: s_sub_i32 s8, 23, s5
+; GFX10-NEXT: s_sub_i32 s8, 23, s4
; GFX10-NEXT: s_or_b32 s0, s6, s0
-; GFX10-NEXT: s_mul_hi_u32 s6, s4, s10
+; GFX10-NEXT: s_mul_hi_u32 s6, s5, s9
; GFX10-NEXT: s_lshl_b32 s0, s0, s8
; GFX10-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX10-NEXT: s_lshr_b32 s2, s2, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s6
+; GFX10-NEXT: s_lshr_b32 s2, s2, s4
+; GFX10-NEXT: s_add_i32 s5, s5, s6
; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_cmp_ge_u32 s4, 24
+; GFX10-NEXT: s_cmp_ge_u32 s5, 24
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_sub_i32 s5, s4, 24
+; GFX10-NEXT: s_sub_i32 s4, s5, 24
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s2, s5, s4
+; GFX10-NEXT: s_cselect_b32 s2, s4, s5
; GFX10-NEXT: s_cmp_ge_u32 s2, 24
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_sub_i32 s5, s2, 24
@@ -2506,116 +2509,6 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_or_b32 s0, s0, s2
; GFX10-NEXT: s_or_b32 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshr_v2i24:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s0, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s2, 0xff
-; GFX11-TRUE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s1, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s6, s8, s6
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s2, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s8, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s0, 24
-; GFX11-TRUE16-NEXT: s_lshl_b32 s8, s8, 8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-TRUE16-NEXT: s_or_b32 s8, s10, s8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s4, 8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s3, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s10, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s7, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s9, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s2, 24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s4, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s10, s10, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s9, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s4, 24
-; GFX11-TRUE16-NEXT: s_or_b32 s10, s12, s10
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: s_mul_i32 s12, s13, 0xffffffe8
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s12, s13, s12
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, s12
-; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s5, 8
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s10, s4, s13
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-TRUE16-NEXT: s_mulk_i32 s10, 0xffe8
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, s10
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s5, s11, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s14, 0xff
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s6, s0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s12, s4, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s11, 0
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s8, s2
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s12, s4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s5, s10
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s4, 24
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s7
-; GFX11-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s8, s4, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s9
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s8, s4
-; GFX11-TRUE16-NEXT: s_mul_hi_u32 s8, s5, s13
-; GFX11-TRUE16-NEXT: s_sub_i32 s6, 23, s4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_mulk_i32 s8, 0xffe8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, s4
-; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, s8
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s5, 24
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s4, s5, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_cmp_ge_u32 s2, 24
-; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 0
-; GFX11-TRUE16-NEXT: s_sub_i32 s5, s2, 24
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 1
-; GFX11-TRUE16-NEXT: s_sub_i32 s4, 23, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_bfe_u32 s2, s0, 0x80008
-; GFX11-TRUE16-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s2, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s3, 24
-; GFX11-TRUE16-NEXT: s_bfe_u32 s3, s1, 0x80010
-; GFX11-TRUE16-NEXT: s_bfe_u32 s1, s1, 0x80008
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s3
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshr_v2i24:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
@@ -2623,8 +2516,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s0, 24
-; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-FAKE16-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-FAKE16-NEXT: s_or_b32 s1, s8, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 8
@@ -2639,76 +2532,82 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s2, 24
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s3, 8
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s8
; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
-; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s3, 8
; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s9, s11, 0xff
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s10, s3
+; GFX11-FAKE16-NEXT: s_and_b32 s9, 0xffff, s9
; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s8
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s4, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s10, s3
-; GFX11-FAKE16-NEXT: s_and_b32 s9, s11, 0xff
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s8, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s3, 0xffff, s3
; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s10, s4, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s8, 0xff
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s9
; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s4, 16
-; GFX11-FAKE16-NEXT: s_or_b32 s8, s10, s8
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v0
-; GFX11-FAKE16-NEXT: s_and_b32 s9, s9, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s4, 24
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 8
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s8, s8, s9
-; GFX11-FAKE16-NEXT: s_mul_i32 s9, s10, 0xffffffe8
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s8
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s9, 0xff
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
; GFX11-FAKE16-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s9, s10, s9
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s4, 24
-; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, s9
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s8
+; GFX11-FAKE16-NEXT: s_mul_i32 s8, s9, 0xffffffe8
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s9, s8, s10
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
-; GFX11-FAKE16-NEXT: s_and_b32 s5, s11, 0xff
-; GFX11-FAKE16-NEXT: s_mulk_i32 s9, 0xffe8
-; GFX11-FAKE16-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, s9
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s8, s9, s8
+; GFX11-FAKE16-NEXT: s_or_b32 s5, s10, s5
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, s8
+; GFX11-FAKE16-NEXT: s_and_b32 s10, s11, 0xff
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s8, s4, s9
+; GFX11-FAKE16-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX11-FAKE16-NEXT: s_mulk_i32 s8, 0xffe8
+; GFX11-FAKE16-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s10, s10, 16
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s8
; GFX11-FAKE16-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-FAKE16-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s8, 24
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s9, s8, 24
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s9, s8
+; GFX11-FAKE16-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX11-FAKE16-NEXT: s_or_b32 s5, s5, s10
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX11-FAKE16-NEXT: s_sub_i32 s10, s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
+; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s10, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s9, s5, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s10, s4, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s9, s5
+; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s10, s4
; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s6, 17
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_sub_i32 s8, 23, s5
+; GFX11-FAKE16-NEXT: s_sub_i32 s8, 23, s4
; GFX11-FAKE16-NEXT: s_or_b32 s0, s6, s0
-; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s4, s10
+; GFX11-FAKE16-NEXT: s_mul_hi_u32 s6, s5, s9
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, s8
; GFX11-FAKE16-NEXT: s_mulk_i32 s6, 0xffe8
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s5
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s6
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, s4
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s6
; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s4, 24
+; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s5, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_sub_i32 s5, s4, 24
+; GFX11-FAKE16-NEXT: s_sub_i32 s4, s5, 24
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s5, s4
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s4, s5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_cmp_ge_u32 s2, 24
; GFX11-FAKE16-NEXT: s_cselect_b32 s4, 1, 0
@@ -2776,10 +2675,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX6-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v6
@@ -2790,8 +2687,6 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2827,10 +2722,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX8-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v6
@@ -2841,51 +2734,97 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: v_fshr_v2i24:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_not_b32_e32 v8, 23
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s4, v6
-; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX9-NEXT: s_add_i32 s6, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v6, v4, s6
-; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, v8, v[4:5]
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v5
-; GFX9-NEXT: v_mul_hi_u32 v5, v4, s6
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
-; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9-NEXT: v_add_u32_e32 v4, 0xffffffe8, v2
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
+; GFX11-LABEL: v_fshr_v2i24:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s0, v6
+; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
+; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
+; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 23, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, v5, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, v6, v2
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, v4, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fshr_v2i24:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_not_b32_e32 v8, 23
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
+; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
+; GFX9-NEXT: s_add_i32 s6, s4, s5
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, s6
+; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, v8, v[4:5]
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v5
+; GFX9-NEXT: v_mul_hi_u32 v5, v4, s6
+; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
+; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 0xffffffe8, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
@@ -2893,7 +2832,6 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v4, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2938,81 +2876,26 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v5, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_v2i24:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX11-NEXT: v_readfirstlane_b32 s0, v6
-; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
-; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
-; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, v6, v2
-; GFX11-NEXT: v_lshl_or_b32 v1, v1, v4, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
ret <2 x i24> %result
}
define amdgpu_ps i32 @s_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
-; GFX6-LABEL: s_fshr_i32:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_mov_b32_e32 v1, s2
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
@@ -3020,22 +2903,12 @@ define amdgpu_ps i32 @s_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, v0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshr_i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshr_i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -3048,77 +2921,59 @@ define amdgpu_ps i32 @s_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
}
define amdgpu_ps i32 @s_fshr_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
-; GFX6-LABEL: s_fshr_i32_5:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 5
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i32_5:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 5
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i32_5:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 5
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i32_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i32_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 5
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i32_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 5
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i32_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 5)
ret i32 %result
}
define amdgpu_ps i32 @s_fshr_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
-; GFX6-LABEL: s_fshr_i32_8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 8
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i32_8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 8
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i32_8:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 8
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i32_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i32_8:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 8
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i32_8:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 8
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i32_8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 8)
ret i32 %result
}
@@ -3130,12 +2985,11 @@ define i32 @v_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
; GCN-NEXT: v_alignbit_b32 v0, v0, v1, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_fshr_i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX11-LABEL: v_fshr_i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, v2.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-LABEL: v_fshr_i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3178,34 +3032,25 @@ define i32 @v_fshr_i32_8(i32 %lhs, i32 %rhs) {
}
define amdgpu_ps float @v_fshr_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
-; GFX6-LABEL: v_fshr_i32_ssv:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v1, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshr_i32_ssv:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v1, v0
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshr_i32_ssv:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v1, v0
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i32_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i32_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v1, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i32_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i32_ssv:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i32_ssv:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, v0
@@ -3216,36 +3061,27 @@ define amdgpu_ps float @v_fshr_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt)
}
define amdgpu_ps float @v_fshr_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt) {
-; GFX6-LABEL: v_fshr_i32_svs:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshr_i32_svs:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshr_i32_svs:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i32_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i32_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i32_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i32_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i32_svs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, s1
@@ -3256,40 +3092,30 @@ define amdgpu_ps float @v_fshr_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
}
define amdgpu_ps float @v_fshr_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
-; GFX6-LABEL: v_fshr_i32_vss:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: v_mov_b32_e32 v1, s2
-; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: v_fshr_i32_vss:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
-; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, v1
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: v_fshr_i32_vss:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_alignbit_b32 v0, s0, v0, v1
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i32_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i32_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i32_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i32_vss:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i32_vss:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -3309,13 +3135,12 @@ define <2 x i32> @v_fshr_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
; GCN-NEXT: v_alignbit_b32 v1, v1, v3, v5
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_fshr_v2i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX11-LABEL: v_fshr_v2i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v2, v4.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v3, v5.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-LABEL: v_fshr_v2i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3335,14 +3160,13 @@ define <3 x i32> @v_fshr_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
; GCN-NEXT: v_alignbit_b32 v2, v2, v5, v8
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_fshr_v3i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX11-LABEL: v_fshr_v3i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v3, v6.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v4, v7.l
+; GFX11-NEXT: v_alignbit_b32 v2, v2, v5, v8.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-LABEL: v_fshr_v3i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3364,15 +3188,14 @@ define <4 x i32> @v_fshr_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
; GCN-NEXT: v_alignbit_b32 v3, v3, v7, v11
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: v_fshr_v4i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX11-LABEL: v_fshr_v4i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_alignbit_b32 v0, v0, v4, v8.l
+; GFX11-NEXT: v_alignbit_b32 v1, v1, v5, v9.l
+; GFX11-NEXT: v_alignbit_b32 v2, v2, v6, v10.l
+; GFX11-NEXT: v_alignbit_b32 v3, v3, v7, v11.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-LABEL: v_fshr_v4i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3408,17 +3231,27 @@ define amdgpu_ps i16 @s_fshr_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: s_fshr_i16:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s3, s2, 15
-; GFX9-NEXT: s_andn2_b32 s2, 15, s2
-; GFX9-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-LABEL: s_fshr_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s3, s2, 15
+; GFX11-NEXT: s_and_not1_b32 s2, 15, s2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_lshr_b32 s1, s1, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: s_fshr_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_and_b32 s3, s2, 15
+; GFX9-NEXT: s_andn2_b32 s2, 15, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s1, s1, s3
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s3, s2, 15
@@ -3429,18 +3262,6 @@ define amdgpu_ps i16 @s_fshr_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s3, s2, 15
-; GFX11-NEXT: s_and_not1_b32 s2, 15, s2
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, s2
-; GFX11-NEXT: s_lshr_b32 s1, s1, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
ret i16 %result
}
@@ -3461,6 +3282,14 @@ define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i16_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 12
+; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i16_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3468,7 +3297,6 @@ define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: s_lshr_b32 s1, s1, 4
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i16_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3476,15 +3304,6 @@ define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX10-NEXT: s_lshr_b32 s1, s1, 4
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i16_4:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, 12
-; GFX11-NEXT: s_lshr_b32 s1, s1, 4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
ret i16 %result
}
@@ -3505,6 +3324,14 @@ define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i16_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 11
+; GFX11-NEXT: s_lshr_b32 s1, s1, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i16_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3512,7 +3339,6 @@ define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: s_lshr_b32 s1, s1, 5
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i16_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3520,15 +3346,6 @@ define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX10-NEXT: s_lshr_b32 s1, s1, 5
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i16_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, 11
-; GFX11-NEXT: s_lshr_b32 s1, s1, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
ret i16 %result
}
@@ -3550,15 +3367,23 @@ define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX8-LABEL: v_fshr_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v3, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b16 v0.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v2.l, v1.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3570,7 +3395,6 @@ define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v3, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3582,21 +3406,6 @@ define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX10-NEXT: v_lshlrev_b16 v0, v3, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v2.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 15
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3631,6 +3440,14 @@ define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i16_4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 12, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 4, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i16_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3638,7 +3455,6 @@ define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, 4, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i16_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3646,16 +3462,6 @@ define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 4, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16_4:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 12, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i16_4:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3685,6 +3491,14 @@ define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i16_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 11, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 5, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i16_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3692,7 +3506,6 @@ define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, 5, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i16_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3700,16 +3513,6 @@ define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
; GFX10-NEXT: v_lshrrev_b16 v1, 5, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16_5:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 11, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 5, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-FAKE16-LABEL: v_fshr_i16_5:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3737,15 +3540,22 @@ define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
;
; GFX8-LABEL: v_fshr_i16_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_and_b32_e32 v1, 15, v0
-; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0
-; GFX8-NEXT: v_lshrrev_b16_e64 v1, v1, s1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s1
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i16_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_xor_b16 v0.h, v0.l, -1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: v_lshrrev_b16 v0.l, v0.l, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, v0.h, s0
+; GFX11-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i16_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v1, 15, v0
@@ -3756,7 +3566,6 @@ define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX9-NEXT: v_lshrrev_b16_e64 v1, v1, s1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i16_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -3767,20 +3576,6 @@ define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX10-NEXT: v_lshlrev_b16 v1, v1, s0
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16_ssv:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v0.l, -1
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 15
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 15
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v0.l, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v0.h, s0
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i16_ssv:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -3812,14 +3607,23 @@ define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
;
; GFX8-LABEL: v_fshr_i16_svs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s2, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_andn2_b32 s2, 15, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_lshl_b32 s0, s0, s1
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, s2, v0
+; GFX8-NEXT: s_lshl_b32 s0, s0, s2
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, s1, v0
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i16_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshrrev_b16 v0.l, s1, v0.l
+; GFX11-NEXT: s_and_not1_b32 s2, 15, s1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i16_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s2, s1, 15
@@ -3829,7 +3633,6 @@ define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX9-NEXT: v_lshrrev_b16_e32 v0, s2, v0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i16_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s2, s1, 15
@@ -3839,19 +3642,6 @@ define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX10-NEXT: s_lshl_b32 s0, s0, s1
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 15
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s1, 15, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, s2, v0.l
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i16_svs:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 15
@@ -3883,7 +3673,7 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX8-LABEL: v_fshr_i16_vss:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s2, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_xor_b32 s1, s1, -1
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: v_lshlrev_b16_e32 v0, s1, v0
@@ -3891,6 +3681,18 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i16_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: s_xor_b32 s2, s1, -1
+; GFX11-NEXT: s_and_b32 s1, s1, 15
+; GFX11-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
+; GFX11-NEXT: s_lshr_b32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, s0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i16_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s2, s1, 15
@@ -3901,7 +3703,6 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX9-NEXT: s_lshr_b32 s0, s0, s2
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i16_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
@@ -3912,20 +3713,6 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX10-NEXT: v_lshlrev_b16 v0, s2, v0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: v_fshr_i16_vss:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 15, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 15
-; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, s0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: v_fshr_i16_vss:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
@@ -3991,6 +3778,28 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v2i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
+; GFX11-NEXT: s_lshl_b32 s3, s3, 1
+; GFX11-NEXT: s_and_b32 s4, s2, 0xf000f
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_and_not1_b32 s2, 0xf000f, s2
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s2, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, s2
+; GFX11-NEXT: s_lshl_b32 s2, s3, s5
+; GFX11-NEXT: s_and_b32 s3, s1, 0xffff
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_lshr_b32 s5, s4, 16
+; GFX11-NEXT: s_lshr_b32 s3, s3, s4
+; GFX11-NEXT: s_lshr_b32 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s3, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s4, s0, 16
@@ -4012,7 +3821,6 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
@@ -4034,29 +3842,6 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1
; GFX10-NEXT: s_or_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_v2i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s3, s0, 16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
-; GFX11-NEXT: s_lshl_b32 s3, s3, 1
-; GFX11-NEXT: s_and_b32 s4, s2, 0xf000f
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX11-NEXT: s_and_not1_b32 s2, 0xf000f, s2
-; GFX11-NEXT: s_lshr_b32 s3, s0, 16
-; GFX11-NEXT: s_lshr_b32 s5, s2, 16
-; GFX11-NEXT: s_lshl_b32 s0, s0, s2
-; GFX11-NEXT: s_lshl_b32 s2, s3, s5
-; GFX11-NEXT: s_and_b32 s3, s1, 0xffff
-; GFX11-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-NEXT: s_lshr_b32 s5, s4, 16
-; GFX11-NEXT: s_lshr_b32 s3, s3, s4
-; GFX11-NEXT: s_lshr_b32 s1, s1, s5
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -4093,28 +3878,36 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX8-LABEL: v_fshr_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 15, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshlrev_b16_e32 v5, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, v4, v5
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, v3, v1
-; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX8-NEXT: v_mov_b32_e32 v4, 15
-; GFX8-NEXT: v_mov_b32_e32 v5, -1
-; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, v3, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v1
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, -1
; GFX8-NEXT: v_mov_b32_e32 v5, 1
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_xor_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v2i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v2, 0xf000f, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xf000f, v3
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, v2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v3, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4126,7 +3919,6 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4138,20 +3930,6 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v3, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_v2i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v2, 0xf000f, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xf000f, v3
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, v2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v3, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
ret <2 x i16> %result
}
@@ -4185,6 +3963,14 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v2i16_4_8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 0x8000c, v0
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 0x80004, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i16_4_8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4194,7 +3980,6 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i16_4_8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4202,15 +3987,6 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX10-NEXT: v_pk_lshrrev_b16 v1, 0x80004, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_v2i16_4_8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 0x8000c, v0
-; GFX11-NEXT: v_pk_lshrrev_b16 v1, 0x80004, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> <i16 4, i16 8>)
ret <2 x i16> %result
}
@@ -4244,29 +4020,39 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
;
; GFX8-LABEL: v_fshr_v2i16_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
-; GFX8-NEXT: v_and_b32_e32 v1, 15, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
+; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_lshlrev_b16_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b16_e64 v1, v1, s1
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, 15
-; GFX8-NEXT: v_mov_b32_e32 v3, -1
-; GFX8-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, v0, s1
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
-; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, -1
+; GFX8-NEXT: v_xor_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: s_lshl_b32 s0, s2, 1
-; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0
-; GFX8-NEXT: v_lshrrev_b16_e64 v2, v2, s3
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_lshlrev_b16_e64 v2, v2, s0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_v2i16_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xf000f, v0
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
+; GFX11-NEXT: s_lshl_b32 s2, s2, 1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xf000f, v1
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, v0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, v1, s0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_v2i16_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s2, s0, 16
@@ -4280,7 +4066,6 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, s1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_v2i16_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
@@ -4294,21 +4079,6 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v1, s0
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_v2i16_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: v_and_b32_e32 v0, 0xf000f, v0
-; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
-; GFX11-NEXT: s_lshl_b32 s2, s2, 1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xf000f, v1
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-NEXT: v_pk_lshrrev_b16 v0, v0, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v1, s0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4342,26 +4112,42 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX8-LABEL: v_fshr_v2i16_svs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
-; GFX8-NEXT: s_lshr_b32 s3, s1, 16
-; GFX8-NEXT: s_and_b32 s4, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_andn2_b32 s4, 15, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_lshl_b32 s0, s0, s1
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, s4, v0
+; GFX8-NEXT: s_lshr_b32 s3, s1, 16
+; GFX8-NEXT: s_lshl_b32 s0, s0, s4
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, s1, v0
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
-; GFX8-NEXT: s_and_b32 s0, s3, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s3
-; GFX8-NEXT: s_lshl_b32 s2, s2, 1
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-NEXT: s_lshl_b32 s1, s2, s1
+; GFX8-NEXT: s_andn2_b32 s0, 15, s3
+; GFX8-NEXT: s_lshl_b32 s1, s2, 1
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: s_lshl_b32 s0, s1, s0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v0, s1, v0
+; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: v_fshr_v2i16_svs:
+; GFX11-LABEL: v_fshr_v2i16_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
+; GFX11-NEXT: s_lshl_b32 s2, s2, 1
+; GFX11-NEXT: s_and_b32 s3, s1, 0xf000f
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s4, s1, 16
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, s3, v0
+; GFX11-NEXT: s_lshl_b32 s0, s0, s1
+; GFX11-NEXT: s_lshl_b32 s1, s2, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: v_fshr_v2i16_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 0x10001
@@ -4377,7 +4163,6 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s2, v0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_v2i16_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 16
@@ -4394,25 +4179,6 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_v2i16_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
-; GFX11-NEXT: s_lshl_b32 s2, s2, 1
-; GFX11-NEXT: s_and_b32 s3, s1, 0xf000f
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-NEXT: v_pk_lshrrev_b16 v0, s3, v0
-; GFX11-NEXT: s_lshl_b32 s0, s0, s1
-; GFX11-NEXT: s_lshl_b32 s1, s2, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4448,7 +4214,7 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_and_b32 s4, s1, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s1
+; GFX8-NEXT: s_xor_b32 s1, s1, -1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v0
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, s1, v1
@@ -4456,7 +4222,7 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: v_mov_b32_e32 v2, 1
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
; GFX8-NEXT: s_and_b32 s0, s3, 15
-; GFX8-NEXT: s_andn2_b32 s1, 15, s3
+; GFX8-NEXT: s_xor_b32 s1, s3, -1
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_lshlrev_b16_e32 v0, s1, v0
; GFX8-NEXT: s_lshr_b32 s0, s2, s0
@@ -4466,6 +4232,22 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_v2i16_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
+; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
+; GFX11-NEXT: s_and_b32 s3, s0, 0xffff
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s4, s2, 16
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, s1, v0
+; GFX11-NEXT: s_lshr_b32 s1, s3, s2
+; GFX11-NEXT: s_lshr_b32 s0, s0, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s1, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_v2i16_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s2, s1, 0xf000f
@@ -4480,7 +4262,6 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_v2i16_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
@@ -4495,23 +4276,6 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_v2i16_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f
-; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1
-; GFX11-NEXT: s_and_b32 s3, s0, 0xffff
-; GFX11-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, s1, v0
-; GFX11-NEXT: s_lshr_b32 s1, s3, s2
-; GFX11-NEXT: s_lshr_b32 s0, s0, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s1, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_or_b32_e32 v0, s0, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -4582,6 +4346,45 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v3i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s6, s0, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
+; GFX11-NEXT: s_lshl_b32 s6, s6, 1
+; GFX11-NEXT: s_and_b32 s7, s4, 0xf000f
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
+; GFX11-NEXT: s_lshr_b32 s6, s0, 16
+; GFX11-NEXT: s_lshr_b32 s8, s4, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, s4
+; GFX11-NEXT: s_lshl_b32 s4, s6, s8
+; GFX11-NEXT: s_and_b32 s6, s2, 0xffff
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4
+; GFX11-NEXT: s_lshr_b32 s4, s1, 16
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshr_b32 s8, s7, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x10001
+; GFX11-NEXT: s_lshl_b32 s4, s4, 1
+; GFX11-NEXT: s_lshr_b32 s6, s6, s7
+; GFX11-NEXT: s_lshr_b32 s2, s2, s8
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s6, s2
+; GFX11-NEXT: s_and_b32 s6, s5, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: s_lshr_b32 s7, s4, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, s4
+; GFX11-NEXT: s_lshl_b32 s4, s5, s7
+; GFX11-NEXT: s_and_b32 s5, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_lshr_b32 s7, s6, 16
+; GFX11-NEXT: s_lshr_b32 s5, s5, s6
+; GFX11-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v3i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s7, s0, 16
@@ -4626,7 +4429,6 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX9-NEXT: s_or_b32 s0, s0, s2
; GFX9-NEXT: s_and_b32 s1, s1, 0xffff
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v3i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s6, s0, 16
@@ -4671,47 +4473,6 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX10-NEXT: s_or_b32 s0, s0, s3
; GFX10-NEXT: s_and_b32 s1, s1, 0xffff
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: s_fshr_v3i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s0, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 0x10001
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s6, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s4, 0xf000f
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s4, 0xf000f, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s6, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s2, 0xffff
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s7, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 0x10001
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 1
-; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s6, s7
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, s8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_not1_b32 s4, 0xf000f, s5
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s6, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xf000f
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s5, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s3, 0xffff
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s6, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, s6
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s3
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
; GFX11-FAKE16-LABEL: s_fshr_v3i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s0, 16
@@ -4802,29 +4563,22 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX8-LABEL: v_fshr_v3i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 15, v4
-; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
-; GFX8-NEXT: v_lshlrev_b16_e32 v8, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v7, v7, v8
-; GFX8-NEXT: v_lshrrev_b16_e32 v6, v6, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX8-NEXT: v_mov_b32_e32 v7, 15
-; GFX8-NEXT: v_mov_b32_e32 v8, -1
-; GFX8-NEXT: v_and_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX8-NEXT: v_mov_b32_e32 v7, -1
; GFX8-NEXT: v_mov_b32_e32 v8, 1
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_xor_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v7, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, v4, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v2, v3
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v5, v3
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
@@ -4832,6 +4586,26 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v3i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX11-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, v7, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v3i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4848,13 +4622,8 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
-; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
-; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
-; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v3i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4869,59 +4638,10 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
-; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
-; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-LABEL: v_fshr_v3i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v6, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v7, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: v_fshr_v3i16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
-; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v6, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v7, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
@@ -5016,6 +4736,45 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v4i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s6, s0, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
+; GFX11-NEXT: s_lshl_b32 s6, s6, 1
+; GFX11-NEXT: s_and_b32 s7, s4, 0xf000f
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
+; GFX11-NEXT: s_lshr_b32 s6, s0, 16
+; GFX11-NEXT: s_lshr_b32 s8, s4, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, s4
+; GFX11-NEXT: s_lshl_b32 s4, s6, s8
+; GFX11-NEXT: s_and_b32 s6, s2, 0xffff
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4
+; GFX11-NEXT: s_lshr_b32 s4, s1, 16
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_lshr_b32 s8, s7, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x10001
+; GFX11-NEXT: s_lshl_b32 s4, s4, 1
+; GFX11-NEXT: s_lshr_b32 s6, s6, s7
+; GFX11-NEXT: s_lshr_b32 s2, s2, s8
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s6, s2
+; GFX11-NEXT: s_and_b32 s6, s5, 0xf000f
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: s_lshr_b32 s7, s4, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, s4
+; GFX11-NEXT: s_lshl_b32 s4, s5, s7
+; GFX11-NEXT: s_and_b32 s5, s3, 0xffff
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: s_lshr_b32 s7, s6, 16
+; GFX11-NEXT: s_lshr_b32 s5, s5, s6
+; GFX11-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
+; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s7, s0, 16
@@ -5055,7 +4814,6 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s6, s0, 16
@@ -5095,46 +4853,6 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX10-NEXT: s_or_b32 s0, s0, s2
; GFX10-NEXT: s_or_b32 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_v4i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s6, s0, 16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 0x10001
-; GFX11-NEXT: s_lshl_b32 s6, s6, 1
-; GFX11-NEXT: s_and_b32 s7, s4, 0xf000f
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s4
-; GFX11-NEXT: s_lshr_b32 s6, s0, 16
-; GFX11-NEXT: s_lshr_b32 s8, s4, 16
-; GFX11-NEXT: s_lshl_b32 s0, s0, s4
-; GFX11-NEXT: s_lshl_b32 s4, s6, s8
-; GFX11-NEXT: s_and_b32 s6, s2, 0xffff
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX11-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-NEXT: s_lshr_b32 s8, s7, 16
-; GFX11-NEXT: s_lshl_b32 s1, s1, 0x10001
-; GFX11-NEXT: s_lshl_b32 s4, s4, 1
-; GFX11-NEXT: s_lshr_b32 s6, s6, s7
-; GFX11-NEXT: s_lshr_b32 s2, s2, s8
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s5
-; GFX11-NEXT: s_pack_ll_b32_b16 s2, s6, s2
-; GFX11-NEXT: s_and_b32 s6, s5, 0xf000f
-; GFX11-NEXT: s_lshr_b32 s5, s1, 16
-; GFX11-NEXT: s_lshr_b32 s7, s4, 16
-; GFX11-NEXT: s_lshl_b32 s1, s1, s4
-; GFX11-NEXT: s_lshl_b32 s4, s5, s7
-; GFX11-NEXT: s_and_b32 s5, s3, 0xffff
-; GFX11-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-NEXT: s_lshr_b32 s7, s6, 16
-; GFX11-NEXT: s_lshr_b32 s5, s5, s6
-; GFX11-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: s_or_b32 s1, s1, s3
-; GFX11-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
%cast.result = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast.result
@@ -5193,83 +4911,36 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-LABEL: v_fshr_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 15, v4
-; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
-; GFX8-NEXT: v_lshlrev_b16_e32 v8, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v7, v7, v8
-; GFX8-NEXT: v_lshrrev_b16_e32 v6, v6, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX8-NEXT: v_mov_b32_e32 v7, 15
-; GFX8-NEXT: v_mov_b32_e32 v9, -1
-; GFX8-NEXT: v_and_b32_sdwa v8, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v10, 1
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX8-NEXT: v_mov_b32_e32 v7, -1
+; GFX8-NEXT: v_mov_b32_e32 v9, 1
+; GFX8-NEXT: v_xor_b32_sdwa v8, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v8, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, 15, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, v4, v6
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v2, v3
-; GFX8-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_and_b32_sdwa v4, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v5, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v5, 15, v5
-; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, v5, v1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v2, v2, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX8-NEXT: v_xor_b32_sdwa v4, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v4, v1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: v_fshr_v4i16:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v6, 0xf000f, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v5
-; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
-; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_fshr_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3
-; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
-; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-LABEL: v_fshr_v4i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5290,30 +4961,66 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fshr_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v6, 0xf000f, v4
+; GFX9-NEXT: v_xor_b32_e32 v4, -1, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX9-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v5
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
+; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fshr_v4i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX10-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX10-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX10-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX10-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX10-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX10-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
%cast.result = bitcast <4 x i16> %result to <4 x half>
ret <4 x half> %cast.result
}
define amdgpu_ps i64 @s_fshr_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt) {
-; GFX6-LABEL: s_fshr_i64:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX6-NEXT: s_not_b32 s5, s4
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
-; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i64:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX8-NEXT: s_not_b32 s5, s4
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
-; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GCN-NEXT: s_not_b32 s5, s4
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
+; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_not_b32 s5, s4
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5322,7 +5029,6 @@ define amdgpu_ps i64 @s_fshr_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt)
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5331,16 +5037,6 @@ define amdgpu_ps i64 @s_fshr_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt)
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_not_b32 s5, s4
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
ret i64 %result
}
@@ -5406,8 +5102,7 @@ define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: v_bfi_b32 v5, v4, 0, 63
-; GFX6-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX6-NEXT: v_not_b32_e32 v5, v4
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v5
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
@@ -5418,14 +5113,25 @@ define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: v_bfi_b32 v5, v4, 0, 63
-; GFX8-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX8-NEXT: v_not_b32_e32 v5, v4
; GFX8-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_not_b32_e32 v5, v4
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v4, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5437,7 +5143,6 @@ define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5449,20 +5154,6 @@ define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: v_and_b32_e32 v5, 63, v4
-; GFX11-NEXT: v_bfi_b32 v4, v4, 0, 63
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
ret i64 %result
}
@@ -5486,6 +5177,14 @@ define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i64_5:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v4, v0
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 27, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i64_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5493,7 +5192,6 @@ define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i64_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5501,15 +5199,6 @@ define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
; GFX10-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_i64_5:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v4, v0
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 27, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
ret i64 %result
}
@@ -5547,28 +5236,26 @@ define i64 @v_fshr_i64_48(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i64_48:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i64_48:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i64_48:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_i64_48:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 48)
ret i64 %result
}
@@ -5577,8 +5264,7 @@ define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX6-LABEL: v_fshr_i64_ssv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX6-NEXT: v_bfi_b32 v1, v0, 0, 63
-; GFX6-NEXT: v_and_b32_e32 v0, 63, v0
+; GFX6-NEXT: v_not_b32_e32 v1, v0
; GFX6-NEXT: v_lshl_b64 v[1:2], s[0:1], v1
; GFX6-NEXT: v_lshr_b64 v[3:4], s[2:3], v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v3
@@ -5588,14 +5274,24 @@ define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX8-LABEL: v_fshr_i64_ssv:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX8-NEXT: v_bfi_b32 v1, v0, 0, 63
-; GFX8-NEXT: v_and_b32_e32 v0, 63, v0
+; GFX8-NEXT: v_not_b32_e32 v1, v0
; GFX8-NEXT: v_lshlrev_b64 v[1:2], v1, s[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[3:4], v0, s[2:3]
; GFX8-NEXT: v_or_b32_e32 v0, v1, v3
; GFX8-NEXT: v_or_b32_e32 v1, v2, v4
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i64_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_not_b32_e32 v2, v0
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v0, s[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v2, s[0:1]
+; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i64_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5606,7 +5302,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX9-NEXT: v_or_b32_e32 v0, v1, v3
; GFX9-NEXT: v_or_b32_e32 v1, v2, v4
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i64_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v1, v0, 0, 63
@@ -5617,20 +5312,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i64_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_bfi_b32 v1, v0, 0, 63
-; GFX11-NEXT: v_and_b32_e32 v2, 63, v0
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v1, s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v2, s[2:3]
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -5641,7 +5322,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_not_b32 s3, s2
-; GFX6-NEXT: s_and_b32 s2, s2, 63
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
@@ -5654,7 +5334,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_not_b32 s3, s2
-; GFX8-NEXT: s_and_b32 s2, s2, 63
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX8-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, s1
@@ -5663,6 +5342,18 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i64_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_not_b32 s3, s2
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i64_svs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5675,7 +5366,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i64_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5688,19 +5378,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX10-NEXT: v_or_b32_e32 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i64_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_not_b32 s3, s2
-; GFX11-NEXT: s_and_b32 s2, s2, 63
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -5710,7 +5387,7 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX6-LABEL: v_fshr_i64_vss:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: s_andn2_b32 s3, 63, s2
+; GFX6-NEXT: s_not_b32 s3, s2
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
@@ -5722,7 +5399,7 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX8-LABEL: v_fshr_i64_vss:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: s_andn2_b32 s3, 63, s2
+; GFX8-NEXT: s_not_b32 s3, s2
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
@@ -5731,6 +5408,18 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i64_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: s_not_b32 s3, s2
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i64_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
@@ -5742,7 +5431,6 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i64_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
@@ -5754,53 +5442,39 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i64_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: s_and_not1_b32 s3, 63, s2
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x i64> @s_fshr_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs, <2 x i64> inreg %amt) {
-; GFX6-LABEL: s_fshr_v2i64:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX6-NEXT: s_not_b32 s9, s8
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_not_b32 s4, s10
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], s10
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_v2i64:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX8-NEXT: s_not_b32 s9, s8
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_not_b32 s4, s10
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[6:7], s10
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_v2i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GCN-NEXT: s_not_b32 s9, s8
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
+; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
+; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: s_not_b32 s4, s10
+; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], s10
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_not_b32 s9, s8
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
+; GFX11-NEXT: s_not_b32 s9, s10
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s9
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s10
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5814,7 +5488,6 @@ define amdgpu_ps <2 x i64> @s_fshr_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %
; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], s10
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5828,20 +5501,6 @@ define amdgpu_ps <2 x i64> @s_fshr_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_v2i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_not_b32 s9, s8
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX11-NEXT: s_not_b32 s9, s10
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s9
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s10
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
ret <2 x i64> %result
}
@@ -5851,16 +5510,14 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: v_bfi_b32 v9, v8, 0, 63
-; GFX6-NEXT: v_and_b32_e32 v8, 63, v8
+; GFX6-NEXT: v_not_b32_e32 v9, v8
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v9
; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v8
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_bfi_b32 v4, v10, 0, 63
+; GFX6-NEXT: v_not_b32_e32 v4, v10
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v4
-; GFX6-NEXT: v_and_b32_e32 v4, 63, v10
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], v4
+; GFX6-NEXT: v_lshr_b64 v[6:7], v[6:7], v10
; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
; GFX6-NEXT: v_or_b32_e32 v3, v3, v7
@@ -5870,22 +5527,39 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: v_bfi_b32 v9, v8, 0, 63
-; GFX8-NEXT: v_and_b32_e32 v8, 63, v8
+; GFX8-NEXT: v_not_b32_e32 v9, v8
; GFX8-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_bfi_b32 v4, v10, 0, 63
+; GFX8-NEXT: v_not_b32_e32 v4, v10
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
-; GFX8-NEXT: v_and_b32_e32 v4, 63, v10
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v4, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v3, v3, v7
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: v_fshr_v2i64:
+; GFX11-LABEL: v_fshr_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: v_not_b32_e32 v9, v8
+; GFX11-NEXT: v_not_b32_e32 v11, v10
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fshr_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
@@ -5903,7 +5577,6 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX9-NEXT: v_or_b32_e32 v2, v2, v6
; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5922,126 +5595,103 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_v2i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_bfi_b32 v9, v8, 0, 63
-; GFX11-NEXT: v_and_b32_e32 v8, 63, v8
-; GFX11-NEXT: v_bfi_b32 v11, v10, 0, 63
-; GFX11-NEXT: v_and_b32_e32 v10, 63, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
-; GFX11-NEXT: v_lshrrev_b64 v[6:7], v10, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
ret <2 x i64> %result
}
define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
-; GFX6-LABEL: s_fshr_i128:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_lshr_b32 s0, s1, 31
-; GFX6-NEXT: s_or_b32 s2, s2, s0
-; GFX6-NEXT: s_andn2_b32 s0, 0x7f, s8
-; GFX6-NEXT: s_not_b32 s9, s8
-; GFX6-NEXT: s_sub_i32 s16, s0, 64
-; GFX6-NEXT: s_sub_i32 s12, 64, s0
-; GFX6-NEXT: s_cmp_lt_u32 s0, 64
-; GFX6-NEXT: s_cselect_b32 s17, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s0, 0
-; GFX6-NEXT: s_cselect_b32 s18, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[12:13], s[10:11], s12
-; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s9
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[10:11], s9
-; GFX6-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[10:11], s16
-; GFX6-NEXT: s_cmp_lg_u32 s17, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s18, 0
-; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11]
-; GFX6-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX6-NEXT: s_sub_i32 s14, s9, 64
-; GFX6-NEXT: s_sub_i32 s12, 64, s9
-; GFX6-NEXT: s_cmp_lt_u32 s9, 64
-; GFX6-NEXT: s_cselect_b32 s15, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s9, 0
-; GFX6-NEXT: s_cselect_b32 s16, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[6:7], s8
-; GFX6-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX6-NEXT: s_lshl_b64 s[12:13], s[6:7], s12
-; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
-; GFX6-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
-; GFX6-NEXT: s_cmp_lg_u32 s16, 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
-; GFX6-NEXT: s_cselect_b64 s[6:7], s[10:11], 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i128:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_lshr_b32 s0, s1, 31
-; GFX8-NEXT: s_or_b32 s2, s2, s0
-; GFX8-NEXT: s_andn2_b32 s0, 0x7f, s8
-; GFX8-NEXT: s_not_b32 s9, s8
-; GFX8-NEXT: s_sub_i32 s16, s0, 64
-; GFX8-NEXT: s_sub_i32 s12, 64, s0
-; GFX8-NEXT: s_cmp_lt_u32 s0, 64
-; GFX8-NEXT: s_cselect_b32 s17, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s0, 0
-; GFX8-NEXT: s_cselect_b32 s18, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[12:13], s[10:11], s12
-; GFX8-NEXT: s_lshl_b64 s[14:15], s[2:3], s9
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[10:11], s9
-; GFX8-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[10:11], s16
-; GFX8-NEXT: s_cmp_lg_u32 s17, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s18, 0
-; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11]
-; GFX8-NEXT: s_and_b32 s9, s8, 0x7f
-; GFX8-NEXT: s_sub_i32 s14, s9, 64
-; GFX8-NEXT: s_sub_i32 s12, 64, s9
-; GFX8-NEXT: s_cmp_lt_u32 s9, 64
-; GFX8-NEXT: s_cselect_b32 s15, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s9, 0
-; GFX8-NEXT: s_cselect_b32 s16, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[6:7], s8
-; GFX8-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX8-NEXT: s_lshl_b64 s[12:13], s[6:7], s12
-; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
-; GFX8-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
-; GFX8-NEXT: s_cmp_lg_u32 s16, 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
-; GFX8-NEXT: s_cselect_b64 s[6:7], s[10:11], 0
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i128:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: s_lshr_b32 s0, s1, 31
+; GCN-NEXT: s_or_b32 s2, s2, s0
+; GCN-NEXT: s_andn2_b32 s0, 0x7f, s8
+; GCN-NEXT: s_not_b32 s9, s8
+; GCN-NEXT: s_sub_i32 s16, s0, 64
+; GCN-NEXT: s_sub_i32 s12, 64, s0
+; GCN-NEXT: s_cmp_lt_u32 s0, 64
+; GCN-NEXT: s_cselect_b32 s17, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s0, 0
+; GCN-NEXT: s_cselect_b32 s18, 1, 0
+; GCN-NEXT: s_lshr_b64 s[12:13], s[10:11], s12
+; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s9
+; GCN-NEXT: s_lshl_b64 s[0:1], s[10:11], s9
+; GCN-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
+; GCN-NEXT: s_lshl_b64 s[10:11], s[10:11], s16
+; GCN-NEXT: s_cmp_lg_u32 s17, 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s18, 0
+; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11]
+; GCN-NEXT: s_and_b32 s9, s8, 0x7f
+; GCN-NEXT: s_sub_i32 s14, s9, 64
+; GCN-NEXT: s_sub_i32 s12, 64, s9
+; GCN-NEXT: s_cmp_lt_u32 s9, 64
+; GCN-NEXT: s_cselect_b32 s15, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s9, 0
+; GCN-NEXT: s_cselect_b32 s16, 1, 0
+; GCN-NEXT: s_lshr_b64 s[10:11], s[6:7], s8
+; GCN-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
+; GCN-NEXT: s_lshl_b64 s[12:13], s[6:7], s12
+; GCN-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
+; GCN-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
+; GCN-NEXT: s_cmp_lg_u32 s15, 0
+; GCN-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; GCN-NEXT: s_cmp_lg_u32 s16, 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
+; GCN-NEXT: s_cmp_lg_u32 s15, 0
+; GCN-NEXT: s_cselect_b64 s[6:7], s[10:11], 0
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b32 s9, s1, 31
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_or_b32 s2, s2, s9
+; GFX11-NEXT: s_and_not1_b32 s9, 0x7f, s8
+; GFX11-NEXT: s_not_b32 s14, s8
+; GFX11-NEXT: s_sub_i32 s16, s9, 64
+; GFX11-NEXT: s_sub_i32 s10, 64, s9
+; GFX11-NEXT: s_cmp_lt_u32 s9, 64
+; GFX11-NEXT: s_cselect_b32 s17, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s9, 0
+; GFX11-NEXT: s_cselect_b32 s9, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s10
+; GFX11-NEXT: s_lshl_b64 s[12:13], s[2:3], s14
+; GFX11-NEXT: s_lshl_b64 s[14:15], s[0:1], s14
+; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s16
+; GFX11-NEXT: s_cmp_lg_u32 s17, 0
+; GFX11-NEXT: s_cselect_b64 s[12:13], s[14:15], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s9, 0
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GFX11-NEXT: s_and_b32 s0, s8, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s14, s0, 64
+; GFX11-NEXT: s_sub_i32 s9, 64, s0
+; GFX11-NEXT: s_cmp_lt_u32 s0, 64
+; GFX11-NEXT: s_cselect_b32 s15, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s16, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], s8
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s9
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[6:7], s8
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
+; GFX11-NEXT: s_cmp_lg_u32 s15, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
+; GFX11-NEXT: s_cmp_lg_u32 s16, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s15, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], 0
+; GFX11-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
@@ -6087,7 +5737,6 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
@@ -6133,53 +5782,6 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX10-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_lshr_b32 s9, s1, 31
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_or_b32 s2, s2, s9
-; GFX11-NEXT: s_and_not1_b32 s9, 0x7f, s8
-; GFX11-NEXT: s_not_b32 s14, s8
-; GFX11-NEXT: s_sub_i32 s16, s9, 64
-; GFX11-NEXT: s_sub_i32 s10, 64, s9
-; GFX11-NEXT: s_cmp_lt_u32 s9, 64
-; GFX11-NEXT: s_cselect_b32 s17, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s9, 0
-; GFX11-NEXT: s_cselect_b32 s9, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s10
-; GFX11-NEXT: s_lshl_b64 s[12:13], s[2:3], s14
-; GFX11-NEXT: s_lshl_b64 s[14:15], s[0:1], s14
-; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s16
-; GFX11-NEXT: s_cmp_lg_u32 s17, 0
-; GFX11-NEXT: s_cselect_b64 s[12:13], s[14:15], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s9, 0
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX11-NEXT: s_and_b32 s0, s8, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s14, s0, 64
-; GFX11-NEXT: s_sub_i32 s9, 64, s0
-; GFX11-NEXT: s_cmp_lt_u32 s0, 64
-; GFX11-NEXT: s_cselect_b32 s15, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s16, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], s8
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s9
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[6:7], s8
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
-; GFX11-NEXT: s_cmp_lg_u32 s15, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
-; GFX11-NEXT: s_cmp_lg_u32 s16, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s15, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], 0
-; GFX11-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
}
@@ -6189,17 +5791,17 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
+; GFX6-NEXT: v_not_b32_e32 v13, v8
; GFX6-NEXT: v_lshl_b64 v[9:10], v[0:1], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GFX6-NEXT: v_and_b32_e32 v15, 0x7f, v13
; GFX6-NEXT: v_or_b32_e32 v2, v2, v0
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x7f
-; GFX6-NEXT: v_bfi_b32 v15, v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 64, v15
; GFX6-NEXT: v_not_b32_e32 v16, 63
; GFX6-NEXT: v_lshr_b64 v[0:1], v[9:10], v0
-; GFX6-NEXT: v_lshl_b64 v[11:12], v[2:3], v15
+; GFX6-NEXT: v_lshl_b64 v[11:12], v[2:3], v13
; GFX6-NEXT: v_add_i32_e32 v17, vcc, v15, v16
-; GFX6-NEXT: v_lshl_b64 v[13:14], v[9:10], v15
+; GFX6-NEXT: v_lshl_b64 v[13:14], v[9:10], v13
; GFX6-NEXT: v_or_b32_e32 v11, v0, v11
; GFX6-NEXT: v_or_b32_e32 v12, v1, v12
; GFX6-NEXT: v_lshl_b64 v[0:1], v[9:10], v17
@@ -6213,13 +5815,13 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-NEXT: v_cndmask_b32_e32 v11, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v12, v1, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v14
-; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], v14
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], v8
; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], v2
; GFX6-NEXT: v_add_i32_e32 v15, vcc, v14, v16
; GFX6-NEXT: v_or_b32_e32 v2, v0, v2
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], v15
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], v14
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], v8
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -6238,17 +5840,17 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX8-NEXT: v_not_b32_e32 v13, v8
; GFX8-NEXT: v_lshlrev_b64 v[9:10], 1, v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GFX8-NEXT: v_and_b32_e32 v15, 0x7f, v13
; GFX8-NEXT: v_or_b32_e32 v2, v2, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, 0x7f
-; GFX8-NEXT: v_bfi_b32 v15, v8, 0, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 64, v15
; GFX8-NEXT: v_not_b32_e32 v16, 63
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, v[9:10]
-; GFX8-NEXT: v_lshlrev_b64 v[11:12], v15, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[11:12], v13, v[2:3]
; GFX8-NEXT: v_add_u32_e32 v17, vcc, v15, v16
-; GFX8-NEXT: v_lshlrev_b64 v[13:14], v15, v[9:10]
+; GFX8-NEXT: v_lshlrev_b64 v[13:14], v13, v[9:10]
; GFX8-NEXT: v_or_b32_e32 v11, v0, v11
; GFX8-NEXT: v_or_b32_e32 v12, v1, v12
; GFX8-NEXT: v_lshlrev_b64 v[0:1], v17, v[9:10]
@@ -6262,13 +5864,13 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_cndmask_b32_e32 v11, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v12, v1, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v14
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v8, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7]
; GFX8-NEXT: v_add_u32_e32 v15, vcc, v14, v16
; GFX8-NEXT: v_or_b32_e32 v2, v0, v2
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v15, v[6:7]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v14, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -6283,6 +5885,58 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_or_b32_e32 v3, v12, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_not_b32_e32 v11, v8
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 31, v1
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v21, 0x7f, v11
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[9:10], v11, v[0:1]
+; GFX11-NEXT: v_sub_nc_u32_e32 v13, 64, v21
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v21
+; GFX11-NEXT: v_and_b32_e32 v22, 0x7f, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v15, 0xffffffc0, v21
+; GFX11-NEXT: v_lshlrev_b64 v[11:12], v11, v[2:3]
+; GFX11-NEXT: v_lshrrev_b64 v[13:14], v13, v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v17, 64, v22
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
+; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v22
+; GFX11-NEXT: v_lshrrev_b64 v[15:16], v8, v[4:5]
+; GFX11-NEXT: v_or_b32_e32 v11, v13, v11
+; GFX11-NEXT: v_lshlrev_b64 v[17:18], v17, v[6:7]
+; GFX11-NEXT: v_or_b32_e32 v12, v14, v12
+; GFX11-NEXT: v_lshrrev_b64 v[19:20], v19, v[6:7]
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v22
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v0, v11, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v22
+; GFX11-NEXT: v_or_b32_e32 v0, v15, v17
+; GFX11-NEXT: v_or_b32_e32 v13, v16, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v1, v12, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v19, v0, s1
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v8, v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, v13, s1
+; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v11, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v12, v3, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v14, v4, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v0, v9, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v7, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6330,7 +5984,6 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX9-NEXT: v_or_b32_e32 v2, v11, v2
; GFX9-NEXT: v_or_b32_e32 v3, v12, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -6377,61 +6030,6 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_bfi_b32 v18, v8, 0, 0x7f
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 31, v1
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: v_and_b32_e32 v19, 0x7f, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v18
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v9
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v16, 64, v19
-; GFX11-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v10, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3]
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v19
-; GFX11-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v18
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0xffffffc0, v18
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
-; GFX11-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e32 v20, v0, v8, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v10, v[6:7]
-; GFX11-NEXT: v_or_b32_e32 v0, v14, v16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v20, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v12, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v1, v7, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v8
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
}
@@ -6439,108 +6037,158 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshr_i128_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x7f
+; GFX6-NEXT: v_not_b32_e32 v5, v0
; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_lshr_b32 s0, s1, 31
-; GFX6-NEXT: v_bfi_b32 v7, v0, 0, v1
+; GFX6-NEXT: v_and_b32_e32 v7, 0x7f, v5
; GFX6-NEXT: s_or_b32 s2, s2, s0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 64, v7
; GFX6-NEXT: v_not_b32_e32 v8, 63
; GFX6-NEXT: v_lshr_b64 v[1:2], s[8:9], v1
-; GFX6-NEXT: v_lshl_b64 v[3:4], s[2:3], v7
+; GFX6-NEXT: v_lshl_b64 v[3:4], s[2:3], v5
; GFX6-NEXT: v_add_i32_e32 v9, vcc, v7, v8
-; GFX6-NEXT: v_lshl_b64 v[5:6], s[8:9], v7
+; GFX6-NEXT: v_lshl_b64 v[5:6], s[8:9], v5
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
; GFX6-NEXT: v_or_b32_e32 v4, v2, v4
; GFX6-NEXT: v_lshl_b64 v[1:2], s[8:9], v9
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s2
; GFX6-NEXT: v_mov_b32_e32 v4, s3
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX6-NEXT: v_and_b32_e32 v11, 0x7f, v0
+; GFX6-NEXT: v_and_b32_e32 v12, 0x7f, v0
; GFX6-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v10, v2, v4, vcc
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v11
-; GFX6-NEXT: v_lshr_b64 v[0:1], s[4:5], v11
-; GFX6-NEXT: v_lshl_b64 v[2:3], s[6:7], v2
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, v11, v8
-; GFX6-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v11, v2, v4, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 64, v12
+; GFX6-NEXT: v_lshr_b64 v[1:2], s[4:5], v0
+; GFX6-NEXT: v_lshl_b64 v[3:4], s[6:7], v3
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GFX6-NEXT: v_lshr_b64 v[5:6], s[6:7], v0
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
; GFX6-NEXT: v_lshr_b64 v[0:1], s[6:7], v8
-; GFX6-NEXT: v_lshr_b64 v[4:5], s[6:7], v11
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s5
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v11
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v12
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; GFX6-NEXT: v_or_b32_e32 v0, v9, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v10, v1
; GFX6-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX6-NEXT: v_or_b32_e32 v3, v11, v3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_fshr_i128_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x7f
+; GFX8-NEXT: v_not_b32_e32 v5, v0
; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_lshr_b32 s0, s1, 31
-; GFX8-NEXT: v_bfi_b32 v7, v0, 0, v1
+; GFX8-NEXT: v_and_b32_e32 v7, 0x7f, v5
; GFX8-NEXT: s_or_b32 s2, s2, s0
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 64, v7
; GFX8-NEXT: v_not_b32_e32 v8, 63
; GFX8-NEXT: v_lshrrev_b64 v[1:2], v1, s[8:9]
-; GFX8-NEXT: v_lshlrev_b64 v[3:4], v7, s[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[3:4], v5, s[2:3]
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v7, v8
-; GFX8-NEXT: v_lshlrev_b64 v[5:6], v7, s[8:9]
+; GFX8-NEXT: v_lshlrev_b64 v[5:6], v5, s[8:9]
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
; GFX8-NEXT: v_or_b32_e32 v4, v2, v4
; GFX8-NEXT: v_lshlrev_b64 v[1:2], v9, s[8:9]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX8-NEXT: v_and_b32_e32 v11, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v12, 0x7f, v0
; GFX8-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v10, v2, v4, vcc
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v11
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], v11, s[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, s[6:7]
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, v11, v8
-; GFX8-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v2, v4, vcc
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 64, v12
+; GFX8-NEXT: v_lshrrev_b64 v[1:2], v0, s[4:5]
+; GFX8-NEXT: v_lshlrev_b64 v[3:4], v3, s[6:7]
+; GFX8-NEXT: v_add_u32_e32 v8, vcc, v12, v8
+; GFX8-NEXT: v_lshrrev_b64 v[5:6], v0, s[6:7]
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v8, s[6:7]
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], v11, s[6:7]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v11
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v12
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; GFX8-NEXT: v_or_b32_e32 v0, v9, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v10, v1
; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX8-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v11, v3
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i128_ssv:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_not_b32_e32 v3, v0
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], 1
+; GFX11-NEXT: s_lshr_b32 s2, s1, 31
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_or_b32 s8, s8, s2
+; GFX11-NEXT: v_lshlrev_b64 v[1:2], v3, s[0:1]
+; GFX11-NEXT: v_and_b32_e32 v15, 0x7f, v3
+; GFX11-NEXT: v_lshlrev_b64 v[3:4], v3, s[8:9]
+; GFX11-NEXT: v_lshrrev_b64 v[9:10], v0, s[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v15
+; GFX11-NEXT: v_and_b32_e32 v16, 0x7f, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, 64, v15
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffc0, v15
+; GFX11-NEXT: v_lshrrev_b64 v[5:6], v5, s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[7:8], v7, s[0:1]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v15
+; GFX11-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v11, 64, v16
+; GFX11-NEXT: v_add_nc_u32_e32 v13, 0xffffffc0, v16
+; GFX11-NEXT: v_or_b32_e32 v1, v6, v4
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX11-NEXT: v_lshlrev_b64 v[11:12], v11, s[6:7]
+; GFX11-NEXT: v_lshrrev_b64 v[13:14], v13, s[6:7]
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v8, v1, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v0, s[6:7]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s8, s0
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v11
+; GFX11-NEXT: v_or_b32_e32 v6, v10, v12
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s9, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v13, v4, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v14, v6, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s4, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s5, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v5, v4
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v6
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v8
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v9
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i128_ssv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7f
@@ -6591,7 +6239,6 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
; GFX9-NEXT: v_or_b32_e32 v3, v9, v3
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i128_ssv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v11, v0, 0, 0x7f
@@ -6637,56 +6284,6 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX10-NEXT: v_or_b32_e32 v2, v7, v8
; GFX10-NEXT: v_or_b32_e32 v3, v4, v9
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i128_ssv:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_bfi_b32 v11, v0, 0, 0x7f
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], 1
-; GFX11-NEXT: s_lshr_b32 s2, s1, 31
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_or_b32 s8, s8, s2
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, 64, v11
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], v11, s[0:1]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0x7f, v0
-; GFX11-NEXT: v_lshlrev_b64 v[3:4], v11, s[8:9]
-; GFX11-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0xffffffc0, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
-; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v12
-; GFX11-NEXT: v_lshrrev_b64 v[7:8], v12, s[4:5]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v12
-; GFX11-NEXT: v_or_b32_e32 v3, v1, v3
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0xffffffc0, v12
-; GFX11-NEXT: v_lshlrev_b64 v[9:10], v9, s[6:7]
-; GFX11-NEXT: v_or_b32_e32 v4, v2, v4
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v14, v0, v3, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
-; GFX11-NEXT: v_or_b32_e32 v0, v7, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v8, v10
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v0, s1
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v12, s[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v14, s8, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s9, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s5, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v1, s1
-; GFX11-NEXT: v_or_b32_e32 v0, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v1, v6, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v7, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v9
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
@@ -6717,26 +6314,26 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX6-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
; GFX6-NEXT: s_cmp_lg_u32 s14, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7]
-; GFX6-NEXT: s_and_b32 s4, s4, 0x7f
-; GFX6-NEXT: s_sub_i32 s5, s4, 64
-; GFX6-NEXT: s_sub_i32 s6, 64, s4
-; GFX6-NEXT: s_cmp_lt_u32 s4, 64
-; GFX6-NEXT: s_cselect_b32 s7, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s4, 0
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s6
+; GFX6-NEXT: s_and_b32 s5, s4, 0x7f
+; GFX6-NEXT: s_sub_i32 s6, s5, 64
+; GFX6-NEXT: s_sub_i32 s7, 64, s5
+; GFX6-NEXT: s_cmp_lt_u32 s5, 64
; GFX6-NEXT: s_cselect_b32 s8, 1, 0
+; GFX6-NEXT: s_cmp_eq_u32 s5, 0
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s7
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s4
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s5
-; GFX6-NEXT: s_cmp_lg_u32 s7, 0
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s6
+; GFX6-NEXT: s_cmp_lg_u32 s8, 0
; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s8, 0
+; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s7, 0
+; GFX6-NEXT: s_cmp_lg_u32 s8, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
@@ -6776,26 +6373,26 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
; GFX8-NEXT: s_cmp_lg_u32 s14, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7]
-; GFX8-NEXT: s_and_b32 s4, s4, 0x7f
-; GFX8-NEXT: s_sub_i32 s5, s4, 64
-; GFX8-NEXT: s_sub_i32 s6, 64, s4
-; GFX8-NEXT: s_cmp_lt_u32 s4, 64
-; GFX8-NEXT: s_cselect_b32 s7, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s4, 0
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s6, v[2:3]
+; GFX8-NEXT: s_and_b32 s5, s4, 0x7f
+; GFX8-NEXT: s_sub_i32 s6, s5, 64
+; GFX8-NEXT: s_sub_i32 s7, 64, s5
+; GFX8-NEXT: s_cmp_lt_u32 s5, 64
; GFX8-NEXT: s_cselect_b32 s8, 1, 0
+; GFX8-NEXT: s_cmp_eq_u32 s5, 0
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], s7, v[2:3]
+; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], s5, v[2:3]
-; GFX8-NEXT: s_cmp_lg_u32 s7, 0
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], s6, v[2:3]
+; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s8, 0
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s7, 0
+; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
@@ -6811,13 +6408,71 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: v_or_b32_e32 v3, v3, v5
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: v_fshr_i128_svs:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX9-NEXT: s_lshr_b32 s0, s1, 31
-; GFX9-NEXT: s_or_b32 s2, s2, s0
-; GFX9-NEXT: s_andn2_b32 s0, 0x7f, s4
+; GFX11-LABEL: v_fshr_i128_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b32 s5, s1, 31
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_or_b32 s2, s2, s5
+; GFX11-NEXT: s_and_not1_b32 s5, 0x7f, s4
+; GFX11-NEXT: s_not_b32 s10, s4
+; GFX11-NEXT: s_sub_i32 s12, s5, 64
+; GFX11-NEXT: s_sub_i32 s6, 64, s5
+; GFX11-NEXT: s_cmp_lt_u32 s5, 64
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s13, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s5, 0
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3]
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s10
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
+; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s12
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX11-NEXT: s_and_b32 s2, s4, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s5, 64, s2
+; GFX11-NEXT: s_sub_i32 s3, s2, 64
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
+; GFX11-NEXT: s_cmp_lt_u32 s2, 64
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3]
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX11-NEXT: ; return to shader part epilog
+; GFX9-LABEL: v_fshr_i128_svs:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX9-NEXT: s_lshr_b32 s0, s1, 31
+; GFX9-NEXT: s_or_b32 s2, s2, s0
+; GFX9-NEXT: s_andn2_b32 s0, 0x7f, s4
; GFX9-NEXT: s_not_b32 s5, s4
; GFX9-NEXT: s_sub_i32 s12, s0, 64
; GFX9-NEXT: s_sub_i32 s8, 64, s0
@@ -6869,7 +6524,6 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i128_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
@@ -6928,64 +6582,6 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v7
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i128_svs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_lshr_b32 s5, s1, 31
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_or_b32 s2, s2, s5
-; GFX11-NEXT: s_and_not1_b32 s5, 0x7f, s4
-; GFX11-NEXT: s_not_b32 s10, s4
-; GFX11-NEXT: s_sub_i32 s12, s5, 64
-; GFX11-NEXT: s_sub_i32 s6, 64, s5
-; GFX11-NEXT: s_cmp_lt_u32 s5, 64
-; GFX11-NEXT: s_cselect_b32 s13, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s10
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
-; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s12
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-NEXT: s_and_b32 s2, s4, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s4, 64, s2
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
-; GFX11-NEXT: s_sub_i32 s3, s2, 64
-; GFX11-NEXT: s_cmp_lt_u32 s2, 64
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], s2, v[2:3]
-; GFX11-NEXT: s_cselect_b32 s4, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 0
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3]
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s5, 0
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
@@ -6995,28 +6591,29 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-LABEL: v_fshr_i128_vss:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: s_andn2_b32 s5, 0x7f, s4
+; GFX6-NEXT: s_andn2_b32 s6, 0x7f, s4
; GFX6-NEXT: v_lshl_b64 v[4:5], v[0:1], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX6-NEXT: s_sub_i32 s6, s5, 64
-; GFX6-NEXT: s_sub_i32 s7, 64, s5
+; GFX6-NEXT: s_not_b32 s5, s4
+; GFX6-NEXT: s_sub_i32 s7, s6, 64
+; GFX6-NEXT: s_sub_i32 s8, 64, s6
; GFX6-NEXT: v_or_b32_e32 v2, v2, v0
-; GFX6-NEXT: s_cmp_lt_u32 s5, 64
-; GFX6-NEXT: s_cselect_b32 s8, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s5, 0
-; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s7
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5
+; GFX6-NEXT: s_cmp_lt_u32 s6, 64
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
+; GFX6-NEXT: s_cmp_eq_u32 s6, 0
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s8
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5
+; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s5
-; GFX6-NEXT: s_cmp_lg_u32 s8, 0
+; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: v_or_b32_e32 v6, v0, v6
; GFX6-NEXT: v_or_b32_e32 v7, v1, v7
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s6
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s7
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX6-NEXT: s_cmp_lg_u32 s9, 0
+; GFX6-NEXT: s_cmp_lg_u32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7053,28 +6650,29 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-LABEL: v_fshr_i128_vss:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: s_andn2_b32 s5, 0x7f, s4
+; GFX8-NEXT: s_andn2_b32 s6, 0x7f, s4
; GFX8-NEXT: v_lshlrev_b64 v[4:5], 1, v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX8-NEXT: s_sub_i32 s6, s5, 64
-; GFX8-NEXT: s_sub_i32 s7, 64, s5
+; GFX8-NEXT: s_not_b32 s5, s4
+; GFX8-NEXT: s_sub_i32 s7, s6, 64
+; GFX8-NEXT: s_sub_i32 s8, 64, s6
; GFX8-NEXT: v_or_b32_e32 v2, v2, v0
-; GFX8-NEXT: s_cmp_lt_u32 s5, 64
-; GFX8-NEXT: s_cselect_b32 s8, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s5, 0
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], s7, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
+; GFX8-NEXT: s_cmp_lt_u32 s6, 64
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
+; GFX8-NEXT: s_cmp_eq_u32 s6, 0
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], s8, v[4:5]
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
+; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: v_lshlrev_b64 v[8:9], s5, v[4:5]
-; GFX8-NEXT: s_cmp_lg_u32 s8, 0
+; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: v_or_b32_e32 v6, v0, v6
; GFX8-NEXT: v_or_b32_e32 v7, v1, v7
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], s6, v[4:5]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], s7, v[4:5]
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
-; GFX8-NEXT: s_cmp_lg_u32 s9, 0
+; GFX8-NEXT: s_cmp_lg_u32 s6, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
@@ -7108,6 +6706,64 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: v_fshr_i128_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v1
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: s_and_not1_b32 s5, 0x7f, s4
+; GFX11-NEXT: s_not_b32 s6, s4
+; GFX11-NEXT: s_sub_i32 s7, 64, s5
+; GFX11-NEXT: s_sub_i32 s8, s5, 64
+; GFX11-NEXT: s_cmp_lt_u32 s5, 64
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], s7, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s7, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s5, 0
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], s6, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s9, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s7, 0
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], s6, v[2:3]
+; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
+; GFX11-NEXT: s_cselect_b32 s5, exec_lo, 0
+; GFX11-NEXT: s_cmp_lg_u32 s9, 0
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], s8, v[0:1]
+; GFX11-NEXT: s_cselect_b32 s6, exec_lo, 0
+; GFX11-NEXT: s_and_b32 s7, s4, 0x7f
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-NEXT: s_sub_i32 s12, s7, 64
+; GFX11-NEXT: s_sub_i32 s10, 64, s7
+; GFX11-NEXT: s_cmp_lt_u32 s7, 64
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-NEXT: s_cselect_b32 s13, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s7, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5
+; GFX11-NEXT: s_cselect_b32 s7, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[0:1], s4
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[2:3], s4
+; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
+; GFX11-NEXT: s_cmp_lg_u32 s7, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
+; GFX11-NEXT: s_cmp_lg_u32 s13, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_or_b32_e32 v0, v6, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v1, v7, v1
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: v_fshr_i128_vss:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
@@ -7165,7 +6821,6 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
; GFX9-NEXT: v_or_b32_e32 v3, v7, v3
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: v_fshr_i128_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
@@ -7223,95 +6878,35 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10-NEXT: v_or_b32_e32 v2, v2, v4
; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: v_fshr_i128_vss:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v1
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: s_and_not1_b32 s5, 0x7f, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s6, 64, s5
-; GFX11-NEXT: s_sub_i32 s7, s5, 64
-; GFX11-NEXT: s_cmp_lt_u32 s5, 64
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
-; GFX11-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], s5, v[0:1]
-; GFX11-NEXT: s_cselect_b32 s8, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
-; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: s_cselect_b32 s5, exec_lo, 0
-; GFX11-NEXT: s_cmp_lg_u32 s8, 0
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1]
-; GFX11-NEXT: s_cselect_b32 s6, exec_lo, 0
-; GFX11-NEXT: s_and_b32 s7, s4, 0x7f
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-NEXT: s_sub_i32 s12, s7, 64
-; GFX11-NEXT: s_sub_i32 s10, 64, s7
-; GFX11-NEXT: s_cmp_lt_u32 s7, 64
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: s_cselect_b32 s13, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s7, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5
-; GFX11-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[0:1], s4
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
-; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[2:3], s4
-; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s7, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX11-NEXT: v_or_b32_e32 v0, v6, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v7, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result
}
define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
-; GFX6-LABEL: s_fshr_i128_65:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s4, 0
-; GFX6-NEXT: s_lshl_b32 s5, s0, 31
-; GFX6-NEXT: s_lshl_b32 s3, s2, 31
-; GFX6-NEXT: s_mov_b32 s2, s4
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
-; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i128_65:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b32 s4, 0
-; GFX8-NEXT: s_lshl_b32 s5, s0, 31
-; GFX8-NEXT: s_lshl_b32 s3, s2, 31
-; GFX8-NEXT: s_mov_b32 s2, s4
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
-; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i128_65:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_mov_b32 s4, 0
+; GCN-NEXT: s_lshl_b32 s5, s0, 31
+; GCN-NEXT: s_lshl_b32 s3, s2, 31
+; GCN-NEXT: s_mov_b32 s2, s4
+; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[0:1]
+; GCN-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; GCN-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_i128_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_lshl_b32 s5, s0, 31
+; GFX11-NEXT: s_lshl_b32 s3, s2, 31
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[0:1], 1
+; GFX11-NEXT: s_or_b64 s[0:1], s[4:5], s[6:7]
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s4, 0
@@ -7323,7 +6918,6 @@ define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_i128_65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s4, 0
@@ -7335,18 +6929,6 @@ define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX10-NEXT: s_or_b64 s[0:1], s[4:5], s[6:7]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_i128_65:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_mov_b32 s4, 0
-; GFX11-NEXT: s_lshl_b32 s5, s0, 31
-; GFX11-NEXT: s_lshl_b32 s3, s2, 31
-; GFX11-NEXT: s_mov_b32 s2, s4
-; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[0:1], 1
-; GFX11-NEXT: s_or_b64 s[0:1], s[4:5], s[6:7]
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
ret i128 %result
}
@@ -7374,6 +6956,18 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_i128_65:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshl_or_b32 v1, v0, 31, v5
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 31, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v0, v4
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -7384,7 +6978,6 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_lshl_or_b32 v1, v0, 31, v5
; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_i128_65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -7395,200 +6988,188 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX10-NEXT: v_lshl_or_b32 v3, v8, 31, v3
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_i128_65:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v8, v2
-; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v1, v0, 31, v5
-; GFX11-NEXT: v_lshl_or_b32 v3, v8, 31, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_mov_b32_e32 v0, v4
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
ret i128 %result
}
define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
-; GFX6-LABEL: s_fshr_v2i128:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b64 s[18:19], s[0:1], 1
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_lshr_b32 s0, s1, 31
-; GFX6-NEXT: s_or_b32 s2, s2, s0
-; GFX6-NEXT: s_andn2_b32 s0, 0x7f, s16
-; GFX6-NEXT: s_not_b32 s17, s16
-; GFX6-NEXT: s_sub_i32 s21, s0, 64
-; GFX6-NEXT: s_sub_i32 s22, 64, s0
-; GFX6-NEXT: s_cmp_lt_u32 s0, 64
-; GFX6-NEXT: s_cselect_b32 s26, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s0, 0
-; GFX6-NEXT: s_cselect_b32 s27, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[22:23], s[18:19], s22
-; GFX6-NEXT: s_lshl_b64 s[24:25], s[2:3], s17
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[18:19], s17
-; GFX6-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
-; GFX6-NEXT: s_lshl_b64 s[18:19], s[18:19], s21
-; GFX6-NEXT: s_cmp_lg_u32 s26, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX6-NEXT: s_cselect_b64 s[18:19], s[22:23], s[18:19]
-; GFX6-NEXT: s_cmp_lg_u32 s27, 0
-; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
-; GFX6-NEXT: s_and_b32 s17, s16, 0x7f
-; GFX6-NEXT: s_sub_i32 s21, s17, 64
-; GFX6-NEXT: s_sub_i32 s22, 64, s17
-; GFX6-NEXT: s_cmp_lt_u32 s17, 64
-; GFX6-NEXT: s_cselect_b32 s24, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s17, 0
-; GFX6-NEXT: s_cselect_b32 s25, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[18:19], s[10:11], s16
-; GFX6-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
-; GFX6-NEXT: s_lshl_b64 s[22:23], s[10:11], s22
-; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s21
-; GFX6-NEXT: s_cmp_lg_u32 s24, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s25, 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s24, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[18:19], 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
-; GFX6-NEXT: s_lshl_b64 s[8:9], s[4:5], 1
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX6-NEXT: s_lshr_b32 s4, s5, 31
-; GFX6-NEXT: s_or_b32 s6, s6, s4
-; GFX6-NEXT: s_andn2_b32 s4, 0x7f, s20
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; GFX6-NEXT: s_not_b32 s16, s20
-; GFX6-NEXT: s_sub_i32 s18, s4, 64
-; GFX6-NEXT: s_sub_i32 s10, 64, s4
-; GFX6-NEXT: s_cmp_lt_u32 s4, 64
-; GFX6-NEXT: s_cselect_b32 s19, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s4, 0
-; GFX6-NEXT: s_cselect_b32 s21, 1, 0
-; GFX6-NEXT: s_lshl_b64 s[4:5], s[8:9], s16
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[8:9], s10
-; GFX6-NEXT: s_lshl_b64 s[16:17], s[6:7], s16
-; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX6-NEXT: s_lshl_b64 s[8:9], s[8:9], s18
-; GFX6-NEXT: s_cmp_lg_u32 s19, 0
-; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
-; GFX6-NEXT: s_cmp_lg_u32 s21, 0
-; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[8:9]
-; GFX6-NEXT: s_and_b32 s8, s20, 0x7f
-; GFX6-NEXT: s_sub_i32 s18, s8, 64
-; GFX6-NEXT: s_sub_i32 s16, 64, s8
-; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: s_cselect_b32 s19, 1, 0
-; GFX6-NEXT: s_cmp_eq_u32 s8, 0
-; GFX6-NEXT: s_cselect_b32 s21, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[12:13], s20
-; GFX6-NEXT: s_lshl_b64 s[16:17], s[14:15], s16
-; GFX6-NEXT: s_lshr_b64 s[8:9], s[14:15], s20
-; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX6-NEXT: s_lshr_b64 s[14:15], s[14:15], s18
-; GFX6-NEXT: s_cmp_lg_u32 s19, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
-; GFX6-NEXT: s_cmp_lg_u32 s21, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s19, 0
-; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
-; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
-; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_v2i128:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b64 s[18:19], s[0:1], 1
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_lshr_b32 s0, s1, 31
-; GFX8-NEXT: s_or_b32 s2, s2, s0
-; GFX8-NEXT: s_andn2_b32 s0, 0x7f, s16
-; GFX8-NEXT: s_not_b32 s17, s16
-; GFX8-NEXT: s_sub_i32 s21, s0, 64
-; GFX8-NEXT: s_sub_i32 s22, 64, s0
-; GFX8-NEXT: s_cmp_lt_u32 s0, 64
-; GFX8-NEXT: s_cselect_b32 s26, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s0, 0
-; GFX8-NEXT: s_cselect_b32 s27, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[22:23], s[18:19], s22
-; GFX8-NEXT: s_lshl_b64 s[24:25], s[2:3], s17
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[18:19], s17
-; GFX8-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
-; GFX8-NEXT: s_lshl_b64 s[18:19], s[18:19], s21
-; GFX8-NEXT: s_cmp_lg_u32 s26, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX8-NEXT: s_cselect_b64 s[18:19], s[22:23], s[18:19]
-; GFX8-NEXT: s_cmp_lg_u32 s27, 0
-; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
-; GFX8-NEXT: s_and_b32 s17, s16, 0x7f
-; GFX8-NEXT: s_sub_i32 s21, s17, 64
-; GFX8-NEXT: s_sub_i32 s22, 64, s17
-; GFX8-NEXT: s_cmp_lt_u32 s17, 64
-; GFX8-NEXT: s_cselect_b32 s24, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s17, 0
-; GFX8-NEXT: s_cselect_b32 s25, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[18:19], s[10:11], s16
-; GFX8-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
-; GFX8-NEXT: s_lshl_b64 s[22:23], s[10:11], s22
-; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s21
-; GFX8-NEXT: s_cmp_lg_u32 s24, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s25, 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s24, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], 0
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
-; GFX8-NEXT: s_lshl_b64 s[8:9], s[4:5], 1
-; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX8-NEXT: s_lshr_b32 s4, s5, 31
-; GFX8-NEXT: s_or_b32 s6, s6, s4
-; GFX8-NEXT: s_andn2_b32 s4, 0x7f, s20
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
-; GFX8-NEXT: s_not_b32 s16, s20
-; GFX8-NEXT: s_sub_i32 s18, s4, 64
-; GFX8-NEXT: s_sub_i32 s10, 64, s4
-; GFX8-NEXT: s_cmp_lt_u32 s4, 64
-; GFX8-NEXT: s_cselect_b32 s19, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s4, 0
-; GFX8-NEXT: s_cselect_b32 s21, 1, 0
-; GFX8-NEXT: s_lshl_b64 s[4:5], s[8:9], s16
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[8:9], s10
-; GFX8-NEXT: s_lshl_b64 s[16:17], s[6:7], s16
-; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX8-NEXT: s_lshl_b64 s[8:9], s[8:9], s18
-; GFX8-NEXT: s_cmp_lg_u32 s19, 0
-; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
-; GFX8-NEXT: s_cmp_lg_u32 s21, 0
-; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[8:9]
-; GFX8-NEXT: s_and_b32 s8, s20, 0x7f
-; GFX8-NEXT: s_sub_i32 s18, s8, 64
-; GFX8-NEXT: s_sub_i32 s16, 64, s8
-; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: s_cselect_b32 s19, 1, 0
-; GFX8-NEXT: s_cmp_eq_u32 s8, 0
-; GFX8-NEXT: s_cselect_b32 s21, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[12:13], s20
-; GFX8-NEXT: s_lshl_b64 s[16:17], s[14:15], s16
-; GFX8-NEXT: s_lshr_b64 s[8:9], s[14:15], s20
-; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
-; GFX8-NEXT: s_lshr_b64 s[14:15], s[14:15], s18
-; GFX8-NEXT: s_cmp_lg_u32 s19, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
-; GFX8-NEXT: s_cmp_lg_u32 s21, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s19, 0
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
-; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
-; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX8-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_v2i128:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b64 s[18:19], s[0:1], 1
+; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: s_lshr_b32 s0, s1, 31
+; GCN-NEXT: s_or_b32 s2, s2, s0
+; GCN-NEXT: s_andn2_b32 s0, 0x7f, s16
+; GCN-NEXT: s_not_b32 s17, s16
+; GCN-NEXT: s_sub_i32 s21, s0, 64
+; GCN-NEXT: s_sub_i32 s22, 64, s0
+; GCN-NEXT: s_cmp_lt_u32 s0, 64
+; GCN-NEXT: s_cselect_b32 s26, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s0, 0
+; GCN-NEXT: s_cselect_b32 s27, 1, 0
+; GCN-NEXT: s_lshr_b64 s[22:23], s[18:19], s22
+; GCN-NEXT: s_lshl_b64 s[24:25], s[2:3], s17
+; GCN-NEXT: s_lshl_b64 s[0:1], s[18:19], s17
+; GCN-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
+; GCN-NEXT: s_lshl_b64 s[18:19], s[18:19], s21
+; GCN-NEXT: s_cmp_lg_u32 s26, 0
+; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
+; GCN-NEXT: s_cselect_b64 s[18:19], s[22:23], s[18:19]
+; GCN-NEXT: s_cmp_lg_u32 s27, 0
+; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
+; GCN-NEXT: s_and_b32 s17, s16, 0x7f
+; GCN-NEXT: s_sub_i32 s21, s17, 64
+; GCN-NEXT: s_sub_i32 s22, 64, s17
+; GCN-NEXT: s_cmp_lt_u32 s17, 64
+; GCN-NEXT: s_cselect_b32 s24, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s17, 0
+; GCN-NEXT: s_cselect_b32 s25, 1, 0
+; GCN-NEXT: s_lshr_b64 s[18:19], s[10:11], s16
+; GCN-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
+; GCN-NEXT: s_lshl_b64 s[22:23], s[10:11], s22
+; GCN-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
+; GCN-NEXT: s_lshr_b64 s[10:11], s[10:11], s21
+; GCN-NEXT: s_cmp_lg_u32 s24, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s25, 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s24, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[18:19], 0
+; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
+; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], 1
+; GCN-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
+; GCN-NEXT: s_lshr_b32 s4, s5, 31
+; GCN-NEXT: s_or_b32 s6, s6, s4
+; GCN-NEXT: s_andn2_b32 s4, 0x7f, s20
+; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
+; GCN-NEXT: s_not_b32 s16, s20
+; GCN-NEXT: s_sub_i32 s18, s4, 64
+; GCN-NEXT: s_sub_i32 s10, 64, s4
+; GCN-NEXT: s_cmp_lt_u32 s4, 64
+; GCN-NEXT: s_cselect_b32 s19, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s4, 0
+; GCN-NEXT: s_cselect_b32 s21, 1, 0
+; GCN-NEXT: s_lshl_b64 s[4:5], s[8:9], s16
+; GCN-NEXT: s_lshr_b64 s[10:11], s[8:9], s10
+; GCN-NEXT: s_lshl_b64 s[16:17], s[6:7], s16
+; GCN-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
+; GCN-NEXT: s_lshl_b64 s[8:9], s[8:9], s18
+; GCN-NEXT: s_cmp_lg_u32 s19, 0
+; GCN-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
+; GCN-NEXT: s_cmp_lg_u32 s21, 0
+; GCN-NEXT: s_cselect_b64 s[6:7], s[6:7], s[8:9]
+; GCN-NEXT: s_and_b32 s8, s20, 0x7f
+; GCN-NEXT: s_sub_i32 s18, s8, 64
+; GCN-NEXT: s_sub_i32 s16, 64, s8
+; GCN-NEXT: s_cmp_lt_u32 s8, 64
+; GCN-NEXT: s_cselect_b32 s19, 1, 0
+; GCN-NEXT: s_cmp_eq_u32 s8, 0
+; GCN-NEXT: s_cselect_b32 s21, 1, 0
+; GCN-NEXT: s_lshr_b64 s[10:11], s[12:13], s20
+; GCN-NEXT: s_lshl_b64 s[16:17], s[14:15], s16
+; GCN-NEXT: s_lshr_b64 s[8:9], s[14:15], s20
+; GCN-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
+; GCN-NEXT: s_lshr_b64 s[14:15], s[14:15], s18
+; GCN-NEXT: s_cmp_lg_u32 s19, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
+; GCN-NEXT: s_cmp_lg_u32 s21, 0
+; GCN-NEXT: s_cselect_b64 s[10:11], s[12:13], s[10:11]
+; GCN-NEXT: s_cmp_lg_u32 s19, 0
+; GCN-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
+; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
+; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GCN-NEXT: ; return to shader part epilog
;
+; GFX11-LABEL: s_fshr_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT: s_lshr_b32 s17, s1, 31
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT: s_or_b32 s2, s2, s17
+; GFX11-NEXT: s_and_not1_b32 s17, 0x7f, s16
+; GFX11-NEXT: s_not_b32 s21, s16
+; GFX11-NEXT: s_sub_i32 s26, s17, 64
+; GFX11-NEXT: s_sub_i32 s18, 64, s17
+; GFX11-NEXT: s_cmp_lt_u32 s17, 64
+; GFX11-NEXT: s_cselect_b32 s27, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s17, 0
+; GFX11-NEXT: s_cselect_b32 s17, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[18:19], s[0:1], s18
+; GFX11-NEXT: s_lshl_b64 s[22:23], s[2:3], s21
+; GFX11-NEXT: s_lshl_b64 s[24:25], s[0:1], s21
+; GFX11-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23]
+; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s26
+; GFX11-NEXT: s_cmp_lg_u32 s27, 0
+; GFX11-NEXT: s_cselect_b64 s[22:23], s[24:25], 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[18:19], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s17, 0
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
+; GFX11-NEXT: s_and_b32 s0, s16, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s21, s0, 64
+; GFX11-NEXT: s_sub_i32 s17, 64, s0
+; GFX11-NEXT: s_cmp_lt_u32 s0, 64
+; GFX11-NEXT: s_cselect_b32 s24, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s25, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], s16
+; GFX11-NEXT: s_lshl_b64 s[18:19], s[10:11], s17
+; GFX11-NEXT: s_lshr_b64 s[16:17], s[10:11], s16
+; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
+; GFX11-NEXT: s_lshr_b64 s[10:11], s[10:11], s21
+; GFX11-NEXT: s_cmp_lg_u32 s24, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
+; GFX11-NEXT: s_cmp_lg_u32 s25, 0
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
+; GFX11-NEXT: s_cmp_lg_u32 s24, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
+; GFX11-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GFX11-NEXT: s_lshr_b32 s8, s5, 31
+; GFX11-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1]
+; GFX11-NEXT: s_or_b32 s6, s6, s8
+; GFX11-NEXT: s_and_not1_b32 s8, 0x7f, s20
+; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], 1
+; GFX11-NEXT: s_not_b32 s16, s20
+; GFX11-NEXT: s_sub_i32 s18, s8, 64
+; GFX11-NEXT: s_sub_i32 s9, 64, s8
+; GFX11-NEXT: s_cmp_lt_u32 s8, 64
+; GFX11-NEXT: s_cselect_b32 s19, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s8, 0
+; GFX11-NEXT: s_cselect_b32 s21, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[4:5], s9
+; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s16
+; GFX11-NEXT: s_lshl_b64 s[16:17], s[4:5], s16
+; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s18
+; GFX11-NEXT: s_cmp_lg_u32 s19, 0
+; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GFX11-NEXT: s_cmp_lg_u32 s21, 0
+; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
+; GFX11-NEXT: s_and_b32 s4, s20, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s18, s4, 64
+; GFX11-NEXT: s_sub_i32 s8, 64, s4
+; GFX11-NEXT: s_cmp_lt_u32 s4, 64
+; GFX11-NEXT: s_cselect_b32 s19, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s21, 1, 0
+; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], s20
+; GFX11-NEXT: s_lshl_b64 s[8:9], s[14:15], s8
+; GFX11-NEXT: s_lshr_b64 s[16:17], s[14:15], s20
+; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], s18
+; GFX11-NEXT: s_cmp_lg_u32 s19, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
+; GFX11-NEXT: s_cmp_lg_u32 s21, 0
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5]
+; GFX11-NEXT: s_cmp_lg_u32 s19, 0
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
+; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; GFX11-NEXT: ; return to shader part epilog
; GFX9-LABEL: s_fshr_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[18:19], s[0:1], 1
@@ -7676,7 +7257,6 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX9-NEXT: ; return to shader part epilog
-;
; GFX10-LABEL: s_fshr_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
@@ -7764,96 +7344,6 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX10-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: ; return to shader part epilog
-;
-; GFX11-LABEL: s_fshr_v2i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX11-NEXT: s_lshr_b32 s17, s1, 31
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
-; GFX11-NEXT: s_or_b32 s2, s2, s17
-; GFX11-NEXT: s_and_not1_b32 s17, 0x7f, s16
-; GFX11-NEXT: s_not_b32 s21, s16
-; GFX11-NEXT: s_sub_i32 s26, s17, 64
-; GFX11-NEXT: s_sub_i32 s18, 64, s17
-; GFX11-NEXT: s_cmp_lt_u32 s17, 64
-; GFX11-NEXT: s_cselect_b32 s27, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s17, 0
-; GFX11-NEXT: s_cselect_b32 s17, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[18:19], s[0:1], s18
-; GFX11-NEXT: s_lshl_b64 s[22:23], s[2:3], s21
-; GFX11-NEXT: s_lshl_b64 s[24:25], s[0:1], s21
-; GFX11-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23]
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s26
-; GFX11-NEXT: s_cmp_lg_u32 s27, 0
-; GFX11-NEXT: s_cselect_b64 s[22:23], s[24:25], 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[18:19], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s17, 0
-; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX11-NEXT: s_and_b32 s0, s16, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s21, s0, 64
-; GFX11-NEXT: s_sub_i32 s17, 64, s0
-; GFX11-NEXT: s_cmp_lt_u32 s0, 64
-; GFX11-NEXT: s_cselect_b32 s24, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s25, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], s16
-; GFX11-NEXT: s_lshl_b64 s[18:19], s[10:11], s17
-; GFX11-NEXT: s_lshr_b64 s[16:17], s[10:11], s16
-; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[18:19]
-; GFX11-NEXT: s_lshr_b64 s[10:11], s[10:11], s21
-; GFX11-NEXT: s_cmp_lg_u32 s24, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
-; GFX11-NEXT: s_cmp_lg_u32 s25, 0
-; GFX11-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s24, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
-; GFX11-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX11-NEXT: s_lshr_b32 s8, s5, 31
-; GFX11-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1]
-; GFX11-NEXT: s_or_b32 s6, s6, s8
-; GFX11-NEXT: s_and_not1_b32 s8, 0x7f, s20
-; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], 1
-; GFX11-NEXT: s_not_b32 s16, s20
-; GFX11-NEXT: s_sub_i32 s18, s8, 64
-; GFX11-NEXT: s_sub_i32 s9, 64, s8
-; GFX11-NEXT: s_cmp_lt_u32 s8, 64
-; GFX11-NEXT: s_cselect_b32 s19, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s8, 0
-; GFX11-NEXT: s_cselect_b32 s21, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[4:5], s9
-; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s16
-; GFX11-NEXT: s_lshl_b64 s[16:17], s[4:5], s16
-; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s18
-; GFX11-NEXT: s_cmp_lg_u32 s19, 0
-; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX11-NEXT: s_cmp_lg_u32 s21, 0
-; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
-; GFX11-NEXT: s_and_b32 s4, s20, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s18, s4, 64
-; GFX11-NEXT: s_sub_i32 s8, 64, s4
-; GFX11-NEXT: s_cmp_lt_u32 s4, 64
-; GFX11-NEXT: s_cselect_b32 s19, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s4, 0
-; GFX11-NEXT: s_cselect_b32 s21, 1, 0
-; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], s20
-; GFX11-NEXT: s_lshl_b64 s[8:9], s[14:15], s8
-; GFX11-NEXT: s_lshr_b64 s[16:17], s[14:15], s20
-; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], s18
-; GFX11-NEXT: s_cmp_lg_u32 s19, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
-; GFX11-NEXT: s_cmp_lg_u32 s21, 0
-; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5]
-; GFX11-NEXT: s_cmp_lg_u32 s19, 0
-; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
-; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
}
@@ -7863,184 +7353,285 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: v_mov_b32_e32 v18, 0x7f
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[0:1], 1
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[0:1], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX6-NEXT: v_bfi_b32 v19, v16, 0, v18
+; GFX6-NEXT: v_not_b32_e32 v23, v16
; GFX6-NEXT: v_or_b32_e32 v2, v2, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7f, v23
; GFX6-NEXT: v_not_b32_e32 v17, 63
-; GFX6-NEXT: v_sub_i32_e32 v23, vcc, 64, v19
-; GFX6-NEXT: v_add_i32_e32 v27, vcc, v19, v17
-; GFX6-NEXT: v_lshr_b64 v[23:24], v[21:22], v23
-; GFX6-NEXT: v_lshl_b64 v[25:26], v[2:3], v19
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[21:22], v19
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[21:22], v27
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19
-; GFX6-NEXT: v_or_b32_e32 v19, v23, v25
-; GFX6-NEXT: v_or_b32_e32 v23, v24, v26
-; GFX6-NEXT: v_cndmask_b32_e32 v24, 0, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v21, v19, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v19, v0, v2, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v16
-; GFX6-NEXT: v_cndmask_b32_e32 v25, 0, v1, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc
-; GFX6-NEXT: v_add_i32_e32 v16, vcc, v2, v17
-; GFX6-NEXT: v_sub_i32_e32 v21, vcc, 64, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
-; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v2
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[8:9], v2
-; GFX6-NEXT: v_lshl_b64 v[21:22], v[10:11], v21
+; GFX6-NEXT: v_add_i32_e32 v25, vcc, v0, v17
+; GFX6-NEXT: v_sub_i32_e32 v21, vcc, 64, v0
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[18:19], v23
+; GFX6-NEXT: v_lshr_b64 v[21:22], v[18:19], v21
+; GFX6-NEXT: v_lshl_b64 v[23:24], v[2:3], v23
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[18:19], v25
+; GFX6-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX6-NEXT: v_cndmask_b32_e32 v23, 0, v0, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v18, v21, vcc
+; GFX6-NEXT: v_or_b32_e32 v22, v22, v24
+; GFX6-NEXT: v_cndmask_b32_e64 v21, v0, v2, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7f, v16
+; GFX6-NEXT: v_cndmask_b32_e32 v24, 0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v19, v22, vcc
+; GFX6-NEXT: v_sub_i32_e32 v18, vcc, 64, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v22, v1, v3, s[4:5]
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[8:9], v16
+; GFX6-NEXT: v_lshl_b64 v[18:19], v[10:11], v18
+; GFX6-NEXT: v_add_i32_e32 v25, vcc, v0, v17
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[10:11], v16
+; GFX6-NEXT: v_or_b32_e32 v16, v2, v18
+; GFX6-NEXT: v_or_b32_e32 v18, v3, v19
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[10:11], v25
; GFX6-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
-; GFX6-NEXT: v_or_b32_e32 v21, v2, v21
-; GFX6-NEXT: v_or_b32_e32 v22, v3, v22
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[10:11], v16
-; GFX6-NEXT: v_bfi_b32 v16, v20, 0, v18
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v21, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v22, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
-; GFX6-NEXT: v_or_b32_e32 v0, v24, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v25, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v19, v8
-; GFX6-NEXT: v_or_b32_e32 v3, v23, v9
+; GFX6-NEXT: v_or_b32_e32 v0, v23, v2
+; GFX6-NEXT: v_or_b32_e32 v1, v24, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v21, v8
+; GFX6-NEXT: v_or_b32_e32 v3, v22, v9
; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX6-NEXT: v_not_b32_e32 v16, v20
; GFX6-NEXT: v_or_b32_e32 v6, v6, v4
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v16
-; GFX6-NEXT: v_add_i32_e32 v21, vcc, v16, v17
+; GFX6-NEXT: v_and_b32_e32 v4, 0x7f, v16
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v4
+; GFX6-NEXT: v_add_i32_e32 v21, vcc, v4, v17
; GFX6-NEXT: v_lshr_b64 v[10:11], v[8:9], v10
; GFX6-NEXT: v_lshl_b64 v[18:19], v[6:7], v16
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GFX6-NEXT: v_lshl_b64 v[4:5], v[8:9], v16
; GFX6-NEXT: v_lshl_b64 v[8:9], v[8:9], v21
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
; GFX6-NEXT: v_or_b32_e32 v10, v10, v18
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX6-NEXT: v_cndmask_b32_e32 v16, 0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX6-NEXT: v_or_b32_e32 v11, v11, v19
-; GFX6-NEXT: v_cndmask_b32_e64 v10, v4, v6, s[4:5]
-; GFX6-NEXT: v_and_b32_e32 v6, 0x7f, v20
-; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v5, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc
-; GFX6-NEXT: v_add_i32_e32 v17, vcc, v6, v17
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v6
-; GFX6-NEXT: v_cndmask_b32_e64 v11, v5, v7, s[4:5]
-; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[14:15], v6
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[12:13], v6
-; GFX6-NEXT: v_lshl_b64 v[8:9], v[14:15], v8
-; GFX6-NEXT: v_or_b32_e32 v8, v6, v8
-; GFX6-NEXT: v_or_b32_e32 v9, v7, v9
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], v17
-; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
-; GFX6-NEXT: v_or_b32_e32 v4, v16, v6
-; GFX6-NEXT: v_or_b32_e32 v5, v18, v7
-; GFX6-NEXT: v_or_b32_e32 v6, v10, v8
-; GFX6-NEXT: v_or_b32_e32 v7, v11, v9
+; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
+; GFX6-NEXT: v_and_b32_e32 v8, 0x7f, v20
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v8
+; GFX6-NEXT: v_add_i32_e32 v18, vcc, v8, v17
+; GFX6-NEXT: v_lshr_b64 v[10:11], v[12:13], v20
+; GFX6-NEXT: v_lshl_b64 v[16:17], v[14:15], v16
+; GFX6-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
+; GFX6-NEXT: v_or_b32_e32 v16, v10, v16
+; GFX6-NEXT: v_or_b32_e32 v17, v11, v17
+; GFX6-NEXT: v_lshr_b64 v[10:11], v[14:15], v18
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[14:15], v20
+; GFX6-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v10, v10, v12, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v11, v11, v13, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v10
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v11
+; GFX6-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX6-NEXT: v_or_b32_e32 v7, v7, v9
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fshr_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v18, 0x7f
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], 1, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], 1, v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX8-NEXT: v_bfi_b32 v19, v16, 0, v18
+; GFX8-NEXT: v_not_b32_e32 v23, v16
; GFX8-NEXT: v_or_b32_e32 v2, v2, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v23
; GFX8-NEXT: v_not_b32_e32 v17, 63
-; GFX8-NEXT: v_sub_u32_e32 v23, vcc, 64, v19
-; GFX8-NEXT: v_add_u32_e32 v27, vcc, v19, v17
-; GFX8-NEXT: v_lshrrev_b64 v[23:24], v23, v[21:22]
-; GFX8-NEXT: v_lshlrev_b64 v[25:26], v19, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v19, v[21:22]
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], v27, v[21:22]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19
-; GFX8-NEXT: v_or_b32_e32 v19, v23, v25
-; GFX8-NEXT: v_or_b32_e32 v23, v24, v26
-; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v21, v19, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v0, v2, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v16
-; GFX8-NEXT: v_cndmask_b32_e32 v25, 0, v1, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc
-; GFX8-NEXT: v_add_u32_e32 v16, vcc, v2, v17
-; GFX8-NEXT: v_sub_u32_e32 v21, vcc, 64, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[10:11]
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v2, v[8:9]
-; GFX8-NEXT: v_lshlrev_b64 v[21:22], v21, v[10:11]
+; GFX8-NEXT: v_add_u32_e32 v25, vcc, v0, v17
+; GFX8-NEXT: v_sub_u32_e32 v21, vcc, 64, v0
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v23, v[18:19]
+; GFX8-NEXT: v_lshrrev_b64 v[21:22], v21, v[18:19]
+; GFX8-NEXT: v_lshlrev_b64 v[23:24], v23, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], v25, v[18:19]
+; GFX8-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX8-NEXT: v_cndmask_b32_e32 v23, 0, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v21, vcc
+; GFX8-NEXT: v_or_b32_e32 v22, v22, v24
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v0, v2, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v22, vcc
+; GFX8-NEXT: v_sub_u32_e32 v18, vcc, 64, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v1, v3, s[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], v16, v[8:9]
+; GFX8-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
+; GFX8-NEXT: v_add_u32_e32 v25, vcc, v0, v17
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v16, v[10:11]
+; GFX8-NEXT: v_or_b32_e32 v16, v2, v18
+; GFX8-NEXT: v_or_b32_e32 v18, v3, v19
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], v25, v[10:11]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; GFX8-NEXT: v_or_b32_e32 v21, v2, v21
-; GFX8-NEXT: v_or_b32_e32 v22, v3, v22
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v16, v[10:11]
-; GFX8-NEXT: v_bfi_b32 v16, v20, 0, v18
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v21, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v22, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
-; GFX8-NEXT: v_or_b32_e32 v0, v24, v2
-; GFX8-NEXT: v_or_b32_e32 v1, v25, v3
-; GFX8-NEXT: v_or_b32_e32 v2, v19, v8
-; GFX8-NEXT: v_or_b32_e32 v3, v23, v9
+; GFX8-NEXT: v_or_b32_e32 v0, v23, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v24, v3
+; GFX8-NEXT: v_or_b32_e32 v2, v21, v8
+; GFX8-NEXT: v_or_b32_e32 v3, v22, v9
; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX8-NEXT: v_not_b32_e32 v16, v20
; GFX8-NEXT: v_or_b32_e32 v6, v6, v4
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v16
-; GFX8-NEXT: v_add_u32_e32 v21, vcc, v16, v17
+; GFX8-NEXT: v_and_b32_e32 v4, 0x7f, v16
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v4
+; GFX8-NEXT: v_add_u32_e32 v21, vcc, v4, v17
; GFX8-NEXT: v_lshrrev_b64 v[10:11], v10, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[18:19], v16, v[6:7]
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; GFX8-NEXT: v_lshlrev_b64 v[4:5], v16, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[8:9], v21, v[8:9]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
; GFX8-NEXT: v_or_b32_e32 v10, v10, v18
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX8-NEXT: v_cndmask_b32_e32 v16, 0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX8-NEXT: v_or_b32_e32 v11, v11, v19
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v4, v6, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v6, 0x7f, v20
-; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, v6, v17
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v6
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v5, v7, s[4:5]
-; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], v6, v[14:15]
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v6, v[12:13]
-; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[14:15]
-; GFX8-NEXT: v_or_b32_e32 v8, v6, v8
-; GFX8-NEXT: v_or_b32_e32 v9, v7, v9
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
-; GFX8-NEXT: v_or_b32_e32 v4, v16, v6
-; GFX8-NEXT: v_or_b32_e32 v5, v18, v7
-; GFX8-NEXT: v_or_b32_e32 v6, v10, v8
-; GFX8-NEXT: v_or_b32_e32 v7, v11, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
+; GFX8-NEXT: v_and_b32_e32 v8, 0x7f, v20
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v8
+; GFX8-NEXT: v_add_u32_e32 v18, vcc, v8, v17
+; GFX8-NEXT: v_lshrrev_b64 v[10:11], v20, v[12:13]
+; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
+; GFX8-NEXT: v_or_b32_e32 v16, v10, v16
+; GFX8-NEXT: v_or_b32_e32 v17, v11, v17
+; GFX8-NEXT: v_lshrrev_b64 v[10:11], v18, v[14:15]
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v12, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v13, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v10
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v11
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX8-NEXT: v_or_b32_e32 v7, v7, v9
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fshr_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 31, v1
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_not_b32_e32 v19, v16
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX11-NEXT: v_and_b32_e32 v27, 0x7f, v16
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b64 v[23:24], v19, v[0:1]
+; GFX11-NEXT: v_and_b32_e32 v25, 0x7f, v19
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b64 v[21:22], v19, v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v25
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v28, v18, v22
+; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v25
+; GFX11-NEXT: v_or_b32_e32 v19, v17, v21
+; GFX11-NEXT: v_sub_nc_u32_e32 v21, 64, v27
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], v16, v[8:9]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v26, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[21:22], v21, v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v0, v19, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v1, v28, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v17, v17, v21
+; GFX11-NEXT: v_or_b32_e32 v18, v18, v22
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v21, v19, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v25, v25, v3, s0
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v16, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v27
+; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v27
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v26, v[10:11]
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v5
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v26, 0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc_lo
+; GFX11-NEXT: v_not_b32_e32 v17, v20
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v27
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v18, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v22, 0x7f, v17
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
+; GFX11-NEXT: v_lshlrev_b64 v[10:11], v17, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e32 v27, 0, v3, vcc_lo
+; GFX11-NEXT: v_sub_nc_u32_e32 v8, 64, v22
+; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
+; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v22
+; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], v17, v[6:7]
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v23
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v22
+; GFX11-NEXT: v_add_nc_u32_e32 v24, 0xffffffc0, v23
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[12:13]
+; GFX11-NEXT: v_or_b32_e32 v8, v2, v8
+; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
+; GFX11-NEXT: v_or_b32_e32 v2, v21, v26
+; GFX11-NEXT: v_or_b32_e32 v9, v3, v9
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v8, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[3:4], v24, v[14:15]
+; GFX11-NEXT: v_or_b32_e32 v8, v16, v18
+; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v22
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v23
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX11-NEXT: v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v11, 0, v11
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v12, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v8, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v9, s1
+; GFX11-NEXT: v_or_b32_e32 v3, v25, v27
+; GFX11-NEXT: v_or_b32_e32 v4, v10, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v11, v12
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -8130,7 +7721,6 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_or_b32_e32 v6, v8, v10
; GFX9-NEXT: v_or_b32_e32 v7, v9, v11
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
; GFX10-LABEL: v_fshr_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -8219,100 +7809,6 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-NEXT: v_or_b32_e32 v6, v6, v8
; GFX10-NEXT: v_or_b32_e32 v7, v7, v9
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fshr_v2i128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX11-NEXT: v_bfi_b32 v25, v16, 0, 0x7f
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 31, v1
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v25
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
-; GFX11-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
-; GFX11-NEXT: v_and_b32_e32 v26, 0x7f, v16
-; GFX11-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v25
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
-; GFX11-NEXT: v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v24, 0, v24
-; GFX11-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
-; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v26
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1]
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
-; GFX11-NEXT: v_bfi_b32 v25, v20, 0, 0x7f
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v21, v0, v21 :: v_dual_cndmask_b32 v22, v1, v22
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
-; GFX11-NEXT: v_or_b32_e32 v17, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e64 v22, v22, v3, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v26
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v5
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
-; GFX11-NEXT: v_sub_nc_u32_e32 v8, 64, v25
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v10
-; GFX11-NEXT: v_dual_cndmask_b32 v26, 0, v2 :: v_dual_cndmask_b32 v27, 0, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], v25, v[6:7]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
-; GFX11-NEXT: v_lshlrev_b64 v[10:11], v25, v[4:5]
-; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
-; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
-; GFX11-NEXT: v_or_b32_e32 v8, v2, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
-; GFX11-NEXT: v_or_b32_e32 v9, v3, v9
-; GFX11-NEXT: v_or_b32_e32 v2, v21, v26
-; GFX11-NEXT: v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v11, 0, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_and_b32 v20, 0x7f, v20
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v20
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[12:13]
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v8, vcc_lo
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX11-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
-; GFX11-NEXT: v_or_b32_e32 v8, v16, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v12, s2
-; GFX11-NEXT: v_or_b32_e32 v3, v22, v27
-; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, v8, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v9, s1
-; GFX11-NEXT: v_or_b32_e32 v4, v10, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v5, v11, v12
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v9
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
}
@@ -8349,3 +7845,5 @@ declare i128 @llvm.fshr.i128(i128, i128, i128) #0
declare <2 x i128> @llvm.fshr.v2i128(<2 x i128>, <2 x i128>, <2 x i128>) #0
attributes #0 = { nounwind readnone speculatable willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir
new file mode 100644
index 0000000000000..bfbc7aaa24175
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir
@@ -0,0 +1,316 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+# A shift only reads the low log2(bitwidth) bits of its amount, so an (and amt,
+# mask) covering those bits is folded away by the constrained shift patterns.
+# G_CONSTANT stays in the SGPR bank, so a VGPR G_AND reads it through a COPY;
+# the patterns have to see through it.
+
+---
+name: shl_i32_masked_amount_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: shl_i32_masked_amount_through_copy
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 31
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i32) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+---
+name: lshr_i32_masked_amount_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: lshr_i32_masked_amount_through_copy
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 31
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i32) = G_LSHR %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+---
+name: ashr_i32_masked_amount_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: ashr_i32_masked_amount_through_copy
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 31
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i32) = G_ASHR %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# A mask wider than the modulo mask still covers the low bits.
+---
+name: shl_i32_superset_mask_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: shl_i32_superset_mask_through_copy
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 255
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i32) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+---
+name: shl_i16_masked_amount_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: shl_i16_masked_amount_through_copy
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:vgpr(i16) = G_TRUNC %0
+ %3:vgpr(i16) = G_TRUNC %1
+ %4:sgpr(i16) = G_CONSTANT i16 15
+ %5:vgpr(i16) = COPY %4
+ %6:vgpr(i16) = G_AND %3, %5
+ %7:vgpr(i16) = G_SHL %2, %6
+ %8:vgpr(i32) = G_ANYEXT %7
+ S_ENDPGM 0, implicit %8
+...
+
+---
+name: shl_i64_masked_amount_through_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: shl_i64_masked_amount_through_copy
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B64_e64_]]
+ %0:vgpr(i64) = COPY $vgpr0_vgpr1
+ %1:vgpr(i32) = COPY $vgpr2
+ %2:sgpr(i32) = G_CONSTANT i32 63
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i64) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# The other place a copy shows up: an SGPR AND feeding a VGPR shift, so the
+# copy sits between the AND and the shift rather than inside the mask.
+---
+name: shl_i32_sgpr_and_vgpr_shift
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; CHECK-LABEL: name: shl_i32_sgpr_and_vgpr_shift
+ ; CHECK: liveins: $vgpr0, $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:sgpr(i32) = COPY $sgpr0
+ %2:sgpr(i32) = G_CONSTANT i32 31
+ %3:sgpr(i32) = G_AND %1, %2
+ %4:vgpr(i32) = COPY %3
+ %5:vgpr(i32) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# Negative: same shape, but mask 30 does not cover bit 0.
+---
+name: shl_i32_sgpr_and_vgpr_shift_misses_low_bit
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; CHECK-LABEL: name: shl_i32_sgpr_and_vgpr_shift_misses_low_bit
+ ; CHECK: liveins: $vgpr0, $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 30
+ ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY2]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:sgpr(i32) = COPY $sgpr0
+ %2:sgpr(i32) = G_CONSTANT i32 30
+ %3:sgpr(i32) = G_AND %1, %2
+ %4:vgpr(i32) = COPY %3
+ %5:vgpr(i32) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# An SGPR shift keeps the constant in the SGPR bank, so there is no copy to
+# look through.
+---
+name: shl_i32_masked_amount_uniform
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: shl_i32_masked_amount_uniform
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ %0:sgpr(i32) = COPY $sgpr0
+ %1:sgpr(i32) = COPY $sgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 31
+ %3:sgpr(i32) = G_AND %1, %2
+ %4:sgpr(i32) = G_SHL %0, %3
+ S_ENDPGM 0, implicit %4
+...
+
+# Negative: mask 30 does not cover bit 0.
+---
+name: shl_i32_mask_misses_low_bit
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: shl_i32_mask_misses_low_bit
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 30
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY2]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[V_AND_B32_e64_]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:sgpr(i32) = G_CONSTANT i32 30
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i32) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# Negative: mask 15 is too narrow for an i64 shift, which needs 6 bits.
+---
+name: shl_i64_mask_too_narrow
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: shl_i64_mask_too_narrow
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY2]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 [[V_AND_B32_e64_]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B64_e64_]]
+ %0:vgpr(i64) = COPY $vgpr0_vgpr1
+ %1:vgpr(i32) = COPY $vgpr2
+ %2:sgpr(i32) = G_CONSTANT i32 15
+ %3:vgpr(i32) = COPY %2
+ %4:vgpr(i32) = G_AND %1, %3
+ %5:vgpr(i64) = G_SHL %0, %4
+ S_ENDPGM 0, implicit %5
+...
+
+# Negative: the mask is not a constant.
+---
+name: shl_i32_variable_mask
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+ ; CHECK-LABEL: name: shl_i32_variable_mask
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY2]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[V_AND_B32_e64_]], [[COPY]], implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(i32) = COPY $vgpr0
+ %1:vgpr(i32) = COPY $vgpr1
+ %2:vgpr(i32) = COPY $vgpr2
+ %3:vgpr(i32) = G_AND %1, %2
+ %4:vgpr(i32) = G_SHL %0, %3
+ S_ENDPGM 0, implicit %4
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index 1f10aaf81646a..fe1d275dbdf1a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -10,7 +10,6 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_lshr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -18,19 +17,18 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX8-LABEL: v_lshr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -38,15 +36,13 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX11-TRUE16-LABEL: v_lshr_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_lshr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -162,7 +158,6 @@ define i24 @v_lshr_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_lshr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -170,7 +165,6 @@ define i24 @v_lshr_i24(i24 %value, i24 %amount) {
; GFX10PLUS-LABEL: v_lshr_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
@@ -623,7 +617,6 @@ define i16 @v_lshr_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_lshr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -759,7 +752,6 @@ define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) {
define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: lshr_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -796,7 +788,6 @@ define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: lshr_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -836,7 +827,6 @@ define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v2
@@ -953,7 +943,6 @@ define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
@@ -989,7 +978,6 @@ define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
@@ -1035,18 +1023,16 @@ define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6-LABEL: v_lshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v2
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, v2, v4
; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
@@ -1182,30 +1168,26 @@ define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-LABEL: v_lshr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v4
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v0
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, v4, v8
; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v8, v8, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v5, v1
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, v6, v5
; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, v5, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v7
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v6, v7, v6
; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v6, v6, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll
new file mode 100644
index 0000000000000..f901455ec08ad
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12-amd-amdhsa -global-isel -stop-after=amdgpu-reg-bank-legalize -o - %s | FileCheck %s
+
+define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) {
+ ; CHECK-LABEL: name: fadd_v2_v_fneg_lo
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:sgpr(p1) = G_LOAD [[COPY]](p4) :: (dereferenceable invariant load (p1) from %ir.a.kernarg.offset1, align 16, addrspace 4)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:sgpr(f32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (f32) from %ir.x.kernarg.offset, align 8, addrspace 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1023
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY [[C1]](i32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY [[C2]](i32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(i32) = nsw G_SHL [[AND]], [[COPY4]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(i64) = G_MERGE_VALUES [[SHL]](i32), [[C3]](i32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(p1) = COPY [[LOAD]](p1)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:vgpr(p1) = nusw inbounds G_PTR_ADD [[COPY5]], [[MV]](i64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:vgpr(<2 x f32>) = G_LOAD [[PTR_ADD1]](p1) :: (load (<2 x f32>) from %ir.gep, addrspace 1)
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:sgpr(f32) = G_FNEG [[LOAD1]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[FNEG]](f32)
+ ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(f32) = G_FCANONICALIZE [[COPY6]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[LOAD2]](<2 x f32>)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(f32) = G_FADD [[UV]], [[FCANONICALIZE]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(f32) = COPY [[LOAD1]](f32)
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:vgpr(f32) = G_FADD [[UV1]], [[COPY7]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x f32>), [[PTR_ADD1]](p1) :: (store (<2 x f32>) into %ir.gep, addrspace 1)
+ ; CHECK-NEXT: S_ENDPGM 0
+ %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
+ %load = load <2 x float>, ptr addrspace(1) %gep, align 8
+ %fneg = fsub float -0.0, %x
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
+ %k = insertelement <2 x float> %tmp1, float %x, i64 1
+ %add = fadd <2 x float> %load, %k
+ store <2 x float> %add, ptr addrspace(1) %gep, align 8
+ ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index 7730d2e14032c..a328d9f248820 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -10,40 +10,36 @@ define i8 @v_shl_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_shl_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_shl_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_shl_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_shl_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_shl_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_shl_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = shl i8 %value, %amount
@@ -136,14 +132,12 @@ define i24 @v_shl_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_shl_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_shl_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = shl i24 %value, %amount
@@ -593,7 +587,6 @@ define i16 @v_shl_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_shl_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -701,7 +694,6 @@ define amdgpu_ps i16 @s_shl_i16_15(i16 inreg %value) {
define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: shl_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
@@ -737,7 +729,6 @@ define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: shl_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
@@ -776,7 +767,6 @@ define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -895,7 +885,6 @@ define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -932,7 +921,6 @@ define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -980,18 +968,16 @@ define <2 x float> @v_shl_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v3, v5
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -1129,20 +1115,18 @@ define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v12, 0xffff, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v12, v0
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v5
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, v5, v1
; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v5, v5, v9
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, v8, v1
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v6
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, v6, v2
; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
@@ -1150,15 +1134,13 @@ define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v7
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, v7, v3
; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v7, v7, v11
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, v8, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
diff --git a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll
index d2fee5930dd9c..479da756ff6be 100644
--- a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll
+++ b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll
@@ -16,7 +16,6 @@ define i16 @csh_16(i16 %a, i16 %b) {
; GISEL-LABEL: csh_16:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v1, 15, v1
; GISEL-NEXT: v_lshlrev_b16_e32 v2, v1, v0
; GISEL-NEXT: v_lshrrev_b16_e32 v3, v1, v0
; GISEL-NEXT: v_ashrrev_i16_e32 v0, v1, v0
@@ -45,7 +44,6 @@ define i32 @csh_32(i32 %a, i32 %b) {
; GISEL-LABEL: csh_32:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v1, 31, v1
; GISEL-NEXT: v_lshlrev_b32_e32 v2, v1, v0
; GISEL-NEXT: v_lshrrev_b32_e32 v3, v1, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v0, v1, v0
@@ -139,10 +137,6 @@ define <4 x i32> @csh_v4i32(<4 x i32> %a, <4 x i32> %b) {
; GISEL-LABEL: csh_v4i32:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v4, 31, v4
-; GISEL-NEXT: v_and_b32_e32 v5, 31, v5
-; GISEL-NEXT: v_and_b32_e32 v6, 31, v6
-; GISEL-NEXT: v_and_b32_e32 v7, 31, v7
; GISEL-NEXT: v_lshlrev_b32_e32 v8, v4, v0
; GISEL-NEXT: v_lshlrev_b32_e32 v9, v5, v1
; GISEL-NEXT: v_lshlrev_b32_e32 v10, v6, v2
@@ -246,12 +240,11 @@ define i64 @csh_64(i64 %a, i64 %b) {
; GISEL-LABEL: csh_64:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v6, 63, v2
-; GISEL-NEXT: v_lshlrev_b64 v[2:3], v6, v[0:1]
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], v6, v[0:1]
-; GISEL-NEXT: v_ashrrev_i64 v[0:1], v6, v[0:1]
-; GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
+; GISEL-NEXT: v_lshlrev_b64 v[3:4], v2, v[0:1]
+; GISEL-NEXT: v_lshrrev_b64 v[5:6], v2, v[0:1]
+; GISEL-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]
+; GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v3, v5
+; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0
; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -336,7 +329,6 @@ define i32 @cshl_or(i32 %a, i32 %b) {
; GISEL-LABEL: cshl_or:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v1, 31, v1
; GISEL-NEXT: v_lshl_or_b32 v0, v0, v1, v0
; GISEL-NEXT: s_setpc_b64 s[30:31]
%and = and i32 %b, 31
@@ -355,7 +347,6 @@ define i32 @cshl_add(i32 %a, i32 %b, i32 %c) {
; GISEL-LABEL: cshl_add:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v1, 31, v1
; GISEL-NEXT: v_lshl_add_u32 v0, v0, v1, v2
; GISEL-NEXT: s_setpc_b64 s[30:31]
%and = and i32 %b, 31
@@ -374,8 +365,7 @@ define i32 @add_cshl(i32 %a, i32 %b) {
; GISEL-LABEL: add_cshl:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_and_b32_e32 v2, 31, v1
-; GISEL-NEXT: v_add_lshl_u32 v0, v0, v1, v2
+; GISEL-NEXT: v_add_lshl_u32 v0, v0, v1, v1
; GISEL-NEXT: s_setpc_b64 s[30:31]
%add = add i32 %a, %b
%and = and i32 %b, 31
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