[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)

[Benjamin Maxwell via llvm-commits]

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@@ -171,14 +171,10 @@ define void @fbyte(<vscale x 16 x i8> %v){
 ; SPLIT-PAIR-NEXT:    sub sp, sp, #16
 ; SPLIT-PAIR-NEXT:    addvl sp, sp, #-16
 ; SPLIT-PAIR-NEXT:    ptrue pn8.b
-; SPLIT-PAIR-NEXT:    st1b { z22.b, z23.b }, pn8, [sp] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z20.b, z21.b }, pn8, [sp, #2, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z18.b, z19.b }, pn8, [sp, #4, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z16.b, z17.b }, pn8, [sp, #6, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z14.b, z15.b }, pn8, [sp, #8, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z12.b, z13.b }, pn8, [sp, #10, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z10.b, z11.b }, pn8, [sp, #12, mul vl] // 32-byte Folded Spill
-; SPLIT-PAIR-NEXT:    st1b { z8.b, z9.b }, pn8, [sp, #14, mul vl] // 32-byte Folded Spill
+; SPLIT-PAIR-NEXT:    st1b { z20.b - z23.b }, pn8, [sp] // 64-byte Folded Spill
+; SPLIT-PAIR-NEXT:    st1b { z16.b - z19.b }, pn8, [sp, #4, mul vl] // 64-byte Folded Spill
+; SPLIT-PAIR-NEXT:    st1b { z12.b - z15.b }, pn8, [sp, #8, mul vl] // 64-byte Folded Spill
+; SPLIT-PAIR-NEXT:    st1b { z8.b - z11.b }, pn8, [sp, #12, mul vl] // 64-byte Folded Spill
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MacDue wrote:

I think the fix looks reasonable :+1:  I think we should split this PR though. Could you first put up a patch to fix the frame indices for the paired case as a separate PR. 

https://github.com/llvm/llvm-project/pull/225100