[llvm] [InstCombine] Misc fixups for #227987 (PR #228076)
Aiden Grossman via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 06:36:37 PDT 2026
https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/228076
* Use ProfcheckDisableMetadataFixes so we can properly ablate this fix with the rest.
* Use UTC for updating the tests rather than modifying them manually.
* Use existing functions in tests rather than duplicating coverage.
* Update profcheck-xfail.txt
>From d3270ce17ebe3058fb20f735ac5f9871743ae891 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Thu, 1 Oct 2026 13:34:55 +0000
Subject: [PATCH] [InstCombine] Misc fixups for #227987
* Use ProfcheckDisableMetadataFixes so we can properly ablate this fix
with the rest.
* Use UTC for updating the tests rather than modifying them manually.
* Use existing functions in tests rather than duplicating coverage.
* Update profcheck-xfail.txt
---
.../InstCombine/InstCombineShifts.cpp | 14 ++--
.../pull-conditional-binop-through-shift.ll | 65 ++-----------------
llvm/test/Transforms/InstCombine/shift.ll | 13 +++-
llvm/utils/profcheck-xfail.txt | 2 -
4 files changed, 26 insertions(+), 68 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 025470f067730..ddac28c675049 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -20,6 +20,10 @@ using namespace PatternMatch;
#define DEBUG_TYPE "instcombine"
+namespace llvm {
+extern cl::opt<bool> ProfcheckDisableMetadataFixes;
+}
+
bool canTryToConstantAddTwoShiftAmounts(Value *Sh0, Value *ShAmt0, Value *Sh1,
Value *ShAmt1) {
// We have two shift amounts from two different shifts. The types of those
@@ -994,8 +998,9 @@ Instruction *InstCombinerImpl::FoldShiftByConstant(Value *Op0, Constant *C1,
Value *NewShift = Builder.CreateBinOp(I.getOpcode(), FalseVal, C1);
Value *NewOp = Builder.CreateBinOp(TBO->getOpcode(), NewShift, NewRHS);
- return SelectInst::Create(Cond, NewOp, NewShift, "", nullptr,
- cast<SelectInst>(Op0));
+ return SelectInst::Create(
+ Cond, NewOp, NewShift, "", nullptr,
+ ProfcheckDisableMetadataFixes ? nullptr : cast<SelectInst>(Op0));
}
}
@@ -1012,8 +1017,9 @@ Instruction *InstCombinerImpl::FoldShiftByConstant(Value *Op0, Constant *C1,
Value *NewShift = Builder.CreateBinOp(I.getOpcode(), TrueVal, C1);
Value *NewOp = Builder.CreateBinOp(FBO->getOpcode(), NewShift, NewRHS);
- return SelectInst::Create(Cond, NewShift, NewOp, "", nullptr,
- cast<SelectInst>(Op0));
+ return SelectInst::Create(
+ Cond, NewShift, NewOp, "", nullptr,
+ ProfcheckDisableMetadataFixes ? nullptr : cast<SelectInst>(Op0));
}
}
diff --git a/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll b/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
index 36bc7bbb1c601..ecb8712712295 100644
--- a/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
+++ b/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals smart
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; shift left
@@ -109,11 +109,11 @@ define i32 @and_signbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_signbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 16776960
-; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]], !prof [[PROF0:![0-9]+]], !unpredictable [[META1:![0-9]+]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 4294901760 ; 0xFFFF0000
- %t1 = select i1 %cond, i32 %t0, i32 %x
+ %t1 = select i1 %cond, i32 %t0, i32 %x, !prof !0, !unpredictable !1
%r = lshr i32 %t1, 8
ret i32 %r
}
@@ -307,63 +307,10 @@ define i32 @add_nosignbit_select_ashr(i32 %x, i1 %cond) {
ret i32 %r
}
-; Branch weights stay on the new select, and stay attached to the same
-; condition arms. The binop may be on either arm.
-
-define i32 @and_select_shl_prof(i32 %x, i1 %cond) {
-; CHECK-LABEL: @and_select_shl_prof(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
-; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]], !prof [[PROF0:![0-9]+]]
-; CHECK-NEXT: ret i32 [[R]]
-;
- %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
- %t1 = select i1 %cond, i32 %t0, i32 %x, !prof !0
- %r = shl i32 %t1, 8
- ret i32 %r
-}
-
-define i32 @and_select_shl_prof_binop_on_false(i32 %x, i1 %cond) {
-; CHECK-LABEL: @and_select_shl_prof_binop_on_false(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
-; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]], !prof [[PROF0]]
-; CHECK-NEXT: ret i32 [[R]]
-;
- %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
- %t1 = select i1 %cond, i32 %x, i32 %t0, !prof !0
- %r = shl i32 %t1, 8
- ret i32 %r
-}
-
-define i32 @and_select_shl_unpredictable(i32 %x, i1 %cond) {
-; CHECK-LABEL: @and_select_shl_unpredictable(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
-; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]], !unpredictable [[UNPREDICTABLE:![0-9]+]]
-; CHECK-NEXT: ret i32 [[R]]
-;
- %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
- %t1 = select i1 %cond, i32 %t0, i32 %x, !unpredictable !1
- %r = shl i32 %t1, 8
- ret i32 %r
-}
-
-define i32 @and_select_shl_unpredictable_binop_on_false(i32 %x, i1 %cond) {
-; CHECK-LABEL: @and_select_shl_unpredictable_binop_on_false(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
-; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]], !unpredictable [[UNPREDICTABLE]]
-; CHECK-NEXT: ret i32 [[R]]
-;
- %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
- %t1 = select i1 %cond, i32 %x, i32 %t0, !unpredictable !1
- %r = shl i32 %t1, 8
- ret i32 %r
-}
-
!0 = !{!"branch_weights", i32 1, i32 99}
!1 = !{}
+;.
; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 99}
-; CHECK: [[UNPREDICTABLE]] = !{}
+; CHECK: [[META1]] = !{}
+;.
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 71914ec6393e6..06df073f512dd 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals smart
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; RUN: opt < %s -passes=instcombine -use-constant-int-for-fixed-length-splat -S | FileCheck %s
@@ -1467,11 +1467,11 @@ define i32 @shl_select_and_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_and_false(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]], !prof [[PROF0:![0-9]+]], !unpredictable [[META1:![0-9]+]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 7
- %2 = select i1 %cond, i32 %x, i32 %1
+ %2 = select i1 %cond, i32 %x, i32 %1, !prof !0, !unpredictable !1
%3 = shl i32 %2, 1
ret i32 %3
}
@@ -2402,3 +2402,10 @@ define i8 @src_ashr_exact_fail(i8 %x) {
}
declare i16 @llvm.umax.i16(i16, i16)
+
+!0 = !{!"branch_weights", i32 1, i32 99}
+!1 = !{}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 99}
+; CHECK: [[META1]] = !{}
+;.
diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt
index b8d2d60ccb7f2..29405d55e773a 100644
--- a/llvm/utils/profcheck-xfail.txt
+++ b/llvm/utils/profcheck-xfail.txt
@@ -53,12 +53,10 @@ Transforms/InstCombine/nested-select.ll
Transforms/InstCombine/pow-1.ll
Transforms/InstCombine/pow-3.ll
Transforms/InstCombine/pow-sqrt.ll
-Transforms/InstCombine/pull-conditional-binop-through-shift.ll
Transforms/InstCombine/select-factorize.ll
Transforms/InstCombine/select-min-max.ll
Transforms/InstCombine/select-of-symmetric-selects.ll
Transforms/InstCombine/select-select.ll
-Transforms/InstCombine/shift.ll
Transforms/InstCombine/simplify-demanded-fpclass.ll
Transforms/InstCombine/sink-not-into-another-hand-of-logical-and.ll
Transforms/InstCombine/sink-not-into-another-hand-of-logical-or.ll
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