[llvm] e8848e5 - AMDGPU: Merge live interval critical edge splitting tests (#228051)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-10-01T12:47:55Z
New Revision: e8848e5fedbad3f20c9412eedf84fc35f6e5229a

URL: https://github.com/llvm/llvm-project/commit/e8848e5fedbad3f20c9412eedf84fc35f6e5229a
DIFF: https://github.com/llvm/llvm-project/commit/e8848e5fedbad3f20c9412eedf84fc35f6e5229a.diff

LOG: AMDGPU: Merge live interval critical edge splitting tests (#228051)

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir

Removed: 
    llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir
deleted file mode 100644
index 0d94737654a62..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir
+++ /dev/null
@@ -1,43 +0,0 @@
-# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass=liveintervals,phi-node-elimination -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgpu9.00 -verify-each -passes='require<live-intervals>,phi-node-elimination' -o - %s | FileCheck %s
-
-# Splitting the critical edge from %bb.1 to %bb.2 removes the new block's
-# interval from %wide. Only %wide.sub0 is live out of %bb.1; %wide.sub1 has a
-# later, non-overlapping segment in %bb.4. Do not try to remove the new block's
-# interval from that non-overlapping subrange.
-
-# CHECK-LABEL: name: split_critical_edge_nonoverlapping_subrange
-# CHECK: bb.1:
-# CHECK: bb.5:
-# CHECK: bb.2:
-
----
-name: split_critical_edge_nonoverlapping_subrange
-tracksRegLiveness: true
-body: |
-  bb.0:
-    %lo:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %hi:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %wide:vreg_64 = REG_SEQUENCE %lo, %subreg.sub0, %hi, %subreg.sub1
-    %phisrc:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
-    $scc = IMPLICIT_DEF
-    S_CBRANCH_SCC1 %bb.1, implicit $scc
-    S_BRANCH %bb.4
-
-  bb.1:
-    $scc = IMPLICIT_DEF
-    S_CBRANCH_SCC1 %bb.3, implicit $scc
-    S_BRANCH %bb.2
-
-  bb.2:
-    %phi:vgpr_32 = PHI %phisrc, %bb.1, %other:vgpr_32, %bb.4
-    S_ENDPGM 0, implicit %phi
-
-  bb.3:
-    S_ENDPGM 0, implicit %wide.sub0, implicit %phisrc
-
-  bb.4:
-    %other:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
-    S_NOP 0, implicit %wide.sub1
-    S_BRANCH %bb.2
-...

diff  --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
index 385153eb1b88d..2f66313d2089b 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
@@ -66,3 +66,77 @@ body:             |
   bb.3:
     S_ENDPGM 0, implicit %2.sub0
 ...
+
+# Splitting the critical edge from %bb.1 to %bb.2 removes the new
+# block's interval from %wide. Only %wide.sub0 is live out of %bb.1;
+# %wide.sub1 has a later, non-overlapping segment in %bb.4. Do not try
+# to remove the new block's interval from that non-overlapping
+# subrange.
+
+---
+name: split_critical_edge_nonoverlapping_subrange
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: split_critical_edge_nonoverlapping_subrange
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %lo:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   %hi:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+  ; CHECK-NEXT:   %wide:vreg_64 = REG_SEQUENCE %lo, %subreg.sub0, %hi, %subreg.sub1
+  ; CHECK-NEXT:   %phisrc:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+  ; CHECK-NEXT:   $scc = IMPLICIT_DEF
+  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
+  ; CHECK-NEXT:   S_BRANCH %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $scc = IMPLICIT_DEF
+  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.3, implicit $scc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY %phisrc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   %phi:vgpr_32 = COPY [[COPY]]
+  ; CHECK-NEXT:   S_ENDPGM 0, implicit %phi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   S_ENDPGM 0, implicit %wide.sub0, implicit %phisrc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %other:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+  ; CHECK-NEXT:   S_NOP 0, implicit %wide.sub1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY %other
+  ; CHECK-NEXT:   S_BRANCH %bb.2
+  bb.0:
+    %lo:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %hi:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %wide:vreg_64 = REG_SEQUENCE %lo, %subreg.sub0, %hi, %subreg.sub1
+    %phisrc:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+    $scc = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.1, implicit $scc
+    S_BRANCH %bb.4
+
+  bb.1:
+    $scc = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.3, implicit $scc
+    S_BRANCH %bb.2
+
+  bb.2:
+    %phi:vgpr_32 = PHI %phisrc, %bb.1, %other:vgpr_32, %bb.4
+    S_ENDPGM 0, implicit %phi
+
+  bb.3:
+    S_ENDPGM 0, implicit %wide.sub0, implicit %phisrc
+
+  bb.4:
+    %other:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+    S_NOP 0, implicit %wide.sub1
+    S_BRANCH %bb.2
+...