[clang] [llvm] [X86] Replace SSE pmulhw/pmulhuw target intrinsics with generic smulh/umulh (PR #227663)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 05:02:11 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-codegen
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Fixes #<!-- -->223627
---
Patch is 98.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/227663.diff
31 Files Affected:
- (modified) clang/lib/CodeGen/TargetBuiltins/X86.cpp (+14)
- (modified) clang/test/CodeGen/X86/avx2-builtins.c (+2-2)
- (modified) clang/test/CodeGen/X86/avx512bw-builtins.c (+6-6)
- (modified) clang/test/CodeGen/X86/avx512vlbw-builtins.c (+8-8)
- (modified) clang/test/CodeGen/X86/mmx-builtins.c (+2-2)
- (modified) clang/test/CodeGen/X86/sse2-builtins.c (+2-2)
- (modified) llvm/include/llvm/IR/IntrinsicsX86.td (-18)
- (modified) llvm/lib/Analysis/ValueTracking.cpp (-14)
- (modified) llvm/lib/IR/AutoUpgrade.cpp (+22-18)
- (modified) llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp (+13-55)
- (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (-6)
- (modified) llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll (+22)
- (modified) llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll (-32)
- (modified) llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll (+63)
- (modified) llvm/test/CodeGen/X86/avx512bw-intrinsics.ll (-62)
- (modified) llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll (+90)
- (modified) llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll (-90)
- (modified) llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll (+42)
- (modified) llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll (-42)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll (+2-2)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll (+4-4)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics.ll (+4-4)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/msan_x86intrinsics.ll (+1-1)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/sse2-intrinsics-x86.ll (+2-2)
- (modified) llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll (+2-2)
- (modified) llvm/test/Instrumentation/MemorySanitizer/i386/msan_i386intrinsics.ll (+2-2)
- (modified) llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-i386.ll (+2-2)
- (removed) llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll (-272)
- (removed) llvm/test/Transforms/InstCombine/X86/x86-pmulhu.ll (-266)
``````````diff
diff --git a/clang/lib/CodeGen/TargetBuiltins/X86.cpp b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
index 5771f10da1d5f..e9b7e28eba31c 100644
--- a/clang/lib/CodeGen/TargetBuiltins/X86.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
@@ -2362,6 +2362,20 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
}
}
+ case X86::BI__builtin_ia32_pmulhw128:
+ case X86::BI__builtin_ia32_pmulhw256:
+ case X86::BI__builtin_ia32_pmulhw512: {
+ Function *F = CGM.getIntrinsic(Intrinsic::smulh, Ops[0]->getType());
+ return Builder.CreateCall(F, {Ops[0], Ops[1]});
+ }
+
+ case X86::BI__builtin_ia32_pmulhuw128:
+ case X86::BI__builtin_ia32_pmulhuw256:
+ case X86::BI__builtin_ia32_pmulhuw512: {
+ Function *F = CGM.getIntrinsic(Intrinsic::umulh, Ops[0]->getType());
+ return Builder.CreateCall(F, {Ops[0], Ops[1]});
+ }
+
case X86::BI__builtin_ia32_pmuludq128:
case X86::BI__builtin_ia32_pmuludq256:
case X86::BI__builtin_ia32_pmuludq512:
diff --git a/clang/test/CodeGen/X86/avx2-builtins.c b/clang/test/CodeGen/X86/avx2-builtins.c
index a8df1a279ec37..1e6a5eb47fcd4 100644
--- a/clang/test/CodeGen/X86/avx2-builtins.c
+++ b/clang/test/CodeGen/X86/avx2-builtins.c
@@ -1051,14 +1051,14 @@ TEST_CONSTEXPR(match_m256i(_mm256_mul_epu32((__m256i)(__v8si){+1, -2, +3, -4, +5
__m256i test_mm256_mulhi_epu16(__m256i a, __m256i b) {
// CHECK-LABEL: test_mm256_mulhi_epu16
- // CHECK: call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
+ // CHECK: call <16 x i16> @llvm.umulh.v16i16(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
return _mm256_mulhi_epu16(a, b);
}
TEST_CONSTEXPR(match_v16hi(_mm256_mulhi_epu16((__m256i)(__v16hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16}, (__m256i)(__v16hi){-32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), 0, -32, 0, 25, 4, -28, 0, 17, 8, -24, 0, 9, 12, 5, 14, 1));
__m256i test_mm256_mulhi_epi16(__m256i a, __m256i b) {
// CHECK-LABEL: test_mm256_mulhi_epi16
- // CHECK: call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
+ // CHECK: call <16 x i16> @llvm.smulh.v16i16(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
return _mm256_mulhi_epi16(a, b);
}
TEST_CONSTEXPR(match_v16hi(_mm256_mulhi_epi16((__m256i)(__v16hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16}, (__m256i)(__v16hi){-32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, -1, -1, -1));
diff --git a/clang/test/CodeGen/X86/avx512bw-builtins.c b/clang/test/CodeGen/X86/avx512bw-builtins.c
index 427efbbb99af8..26136602c968b 100644
--- a/clang/test/CodeGen/X86/avx512bw-builtins.c
+++ b/clang/test/CodeGen/X86/avx512bw-builtins.c
@@ -1959,14 +1959,14 @@ TEST_CONSTEXPR(match_v32hi(_mm512_maskz_mulhrs_epi16(0x0000FFFF, (__m512i)(__v32
__m512i test_mm512_mulhi_epi16(__m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
return _mm512_mulhi_epi16(__A,__B);
}
TEST_CONSTEXPR(match_v32hi(_mm512_mulhi_epi16((__m512i)(__v32hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16, +17, -18, +19, -20, +21, -22, +23, -24, +25, -26, +27, -28, +29, -30, +31, -32}, (__m512i)(__v32hi){-64, -62, +60, +58, -56, -54, +52, +50, -48, -46, +44, +42, -40, -38, +36, +34, -32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, -1, -1, -1));
__m512i test_mm512_mask_mulhi_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mask_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_mask_mulhi_epi16(__W,__U,__A,__B);
}
@@ -1974,7 +1974,7 @@ TEST_CONSTEXPR(match_v32hi(_mm512_mask_mulhi_epi16(_mm512_set1_epi16(1), 0xF00FF
__m512i test_mm512_maskz_mulhi_epi16(__mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_maskz_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_maskz_mulhi_epi16(__U,__A,__B);
}
@@ -1982,14 +1982,14 @@ TEST_CONSTEXPR(match_v32hi(_mm512_maskz_mulhi_epi16(0x0FF00FF0, (__m512i)(__v32h
__m512i test_mm512_mulhi_epu16(__m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
return _mm512_mulhi_epu16(__A,__B);
}
TEST_CONSTEXPR(match_v32hi(_mm512_mulhi_epu16((__m512i)(__v32hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16, +17, -18, +19, -20, +21, -22, +23, -24, +25, -26, +27, -28, +29, -30, +31, -32}, (__m512i)(__v32hi){-64, -62, +60, +58, -56, -54, +52, +50, -48, -46, +44, +42, -40, -38, +36, +34, -32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), 0, -64, 0, 57, 4, -60, 0, 49, 8, -56, 0, 41, 12, -52, 0, 33, 16, -48, 0, 25, 20, -44, 0, 17, 24, -40, 0, 9, 28, 5, 30, 1));
__m512i test_mm512_mask_mulhi_epu16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mask_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_mask_mulhi_epu16(__W,__U,__A,__B);
}
@@ -1997,7 +1997,7 @@ TEST_CONSTEXPR(match_v32hi(_mm512_mask_mulhi_epu16(_mm512_set1_epi16(1), 0x0FF00
__m512i test_mm512_maskz_mulhi_epu16(__mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_maskz_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_maskz_mulhi_epu16(__U,__A,__B);
}
diff --git a/clang/test/CodeGen/X86/avx512vlbw-builtins.c b/clang/test/CodeGen/X86/avx512vlbw-builtins.c
index 048a424f8ac2b..f8ac120752bf1 100644
--- a/clang/test/CodeGen/X86/avx512vlbw-builtins.c
+++ b/clang/test/CodeGen/X86/avx512vlbw-builtins.c
@@ -2223,7 +2223,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_maskz_mulhrs_epi16(0xF00F, (__m256i)(__v16hi){
__m128i test_mm_mask_mulhi_epu16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_mask_mulhi_epu16
- // CHECK: @llvm.x86.sse2.pmulhu.w
+ // CHECK: @llvm.umulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_mulhi_epu16(__W, __U, __A, __B);
}
@@ -2231,7 +2231,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_mask_mulhi_epu16(_mm_set1_epi16(1), 0x3C, (__m128i
__m128i test_mm_maskz_mulhi_epu16(__mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_maskz_mulhi_epu16
- // CHECK: @llvm.x86.sse2.pmulhu.w
+ // CHECK: @llvm.umulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_maskz_mulhi_epu16(__U, __A, __B);
}
@@ -2239,7 +2239,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_maskz_mulhi_epu16(0x87, (__m128i)(__v8hi){+1, -2,
__m256i test_mm256_mask_mulhi_epu16(__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_mask_mulhi_epu16
- // CHECK: @llvm.x86.avx2.pmulhu.w
+ // CHECK: @llvm.umulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_mulhi_epu16(__W, __U, __A, __B);
}
@@ -2247,7 +2247,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_mask_mulhi_epu16(_mm256_set1_epi16(1), 0xF00F,
__m256i test_mm256_maskz_mulhi_epu16(__mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_maskz_mulhi_epu16
- // CHECK: @llvm.x86.avx2.pmulhu.w
+ // CHECK: @llvm.umulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_maskz_mulhi_epu16(__U, __A, __B);
}
@@ -2255,7 +2255,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_maskz_mulhi_epu16(0x0FF0, (__m256i)(__v16hi){+
__m128i test_mm_mask_mulhi_epi16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_mask_mulhi_epi16
- // CHECK: @llvm.x86.sse2.pmulh.w
+ // CHECK: @llvm.smulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_mulhi_epi16(__W, __U, __A, __B);
}
@@ -2263,7 +2263,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_mask_mulhi_epu16(_mm_set1_epi16(1), 0x78, (__m128i
__m128i test_mm_maskz_mulhi_epi16(__mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_maskz_mulhi_epi16
- // CHECK: @llvm.x86.sse2.pmulh.w
+ // CHECK: @llvm.smulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_maskz_mulhi_epi16(__U, __A, __B);
}
@@ -2271,7 +2271,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_maskz_mulhi_epi16(0xC3, (__m128i)(__v8hi){+1, -2,
__m256i test_mm256_mask_mulhi_epi16(__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_mask_mulhi_epi16
- // CHECK: @llvm.x86.avx2.pmulh.w
+ // CHECK: @llvm.smulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_mulhi_epi16(__W, __U, __A, __B);
}
@@ -2279,7 +2279,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_mask_mulhi_epi16(_mm256_set1_epi16(1), 0x0FF0,
__m256i test_mm256_maskz_mulhi_epi16(__mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_maskz_mulhi_epi16
- // CHECK: @llvm.x86.avx2.pmulh.w
+ // CHECK: @llvm.smulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_maskz_mulhi_epi16(__U, __A, __B);
}
diff --git a/clang/test/CodeGen/X86/mmx-builtins.c b/clang/test/CodeGen/X86/mmx-builtins.c
index 3cae57b6500c8..8ede0eb962a1d 100644
--- a/clang/test/CodeGen/X86/mmx-builtins.c
+++ b/clang/test/CodeGen/X86/mmx-builtins.c
@@ -434,14 +434,14 @@ TEST_CONSTEXPR(match_m64(_mm_mul_su32((__m64)(__v2si){+1, -2}, (__m64)(__v2si){-
__m64 test_mm_mulhi_pi16(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_mulhi_pi16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(
+ // CHECK: call <8 x i16> @llvm.smulh.v8i16(
return _mm_mulhi_pi16(a, b);
}
TEST_CONSTEXPR(match_v4hi(_mm_mulhi_pi16((__m64)(__v4hi){+1, -2, +3, -4}, (__m64)(__v4hi){-10, +8, +6, -4}), -1, -1, 0, 0));
__m64 test_mm_mulhi_pu16(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_mulhi_pu16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulhu.w(
+ // CHECK: call <8 x i16> @llvm.umulh.v8i16(
return _mm_mulhi_pu16(a, b);
}
TEST_CONSTEXPR(match_v4hi(_mm_mulhi_pu16((__m64)(__v4hi){+1, -2, +3, -4}, (__m64)(__v4hi){-10, +8, +6, -4}), 0, 7, 0, -8));
diff --git a/clang/test/CodeGen/X86/sse2-builtins.c b/clang/test/CodeGen/X86/sse2-builtins.c
index c0c4acf2daea5..5f5adbfd59542 100644
--- a/clang/test/CodeGen/X86/sse2-builtins.c
+++ b/clang/test/CodeGen/X86/sse2-builtins.c
@@ -1020,14 +1020,14 @@ TEST_CONSTEXPR(match_m128d(_mm_mul_sd((__m128d){+1.0, -3.0}, (__m128d){+5.0, -5.
__m128i test_mm_mulhi_epi16(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_mulhi_epi16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
+ // CHECK: call <8 x i16> @llvm.smulh.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
return _mm_mulhi_epi16(A, B);
}
TEST_CONSTEXPR(match_v8hi(_mm_mulhi_epi16((__m128i)(__v8hi){+1, -2, +3, -4, +5, -6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, -1, -1, -1));
__m128i test_mm_mulhi_epu16(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_mulhi_epu16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
+ // CHECK: call <8 x i16> @llvm.umulh.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
return _mm_mulhi_epu16(A, B);
}
TEST_CONSTEXPR(match_v8hi(_mm_mulhi_epu16((__m128i)(__v8hi){+1, -2, +3, -4, +5, -6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -8, +6, -4, +2}), 0, -16, 0, 9, 4, 5, 6, 1));
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index a315b234a39cf..3617008d2ee8e 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -329,12 +329,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_sse2_pmulhu_w : ClangBuiltin<"__builtin_ia32_pmulhuw128">,
- DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_sse2_pmulh_w : ClangBuiltin<"__builtin_ia32_pmulhw128">,
- DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty], [IntrNoMem, Commutative]>;
def int_x86_sse2_pmadd_wd : ClangBuiltin<"__builtin_ia32_pmaddwd128">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
@@ -1336,12 +1330,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_avx2_pmulhu_w : ClangBuiltin<"__builtin_ia32_pmulhuw256">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
- llvm_v16i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_avx2_pmulh_w : ClangBuiltin<"__builtin_ia32_pmulhw256">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
- llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmadd_wd : ClangBuiltin<"__builtin_ia32_pmaddwd256">,
DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
@@ -3760,12 +3748,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
}
// Integer arithmetic ops
let TargetPrefix = "x86" in {
- def int_x86_avx512_pmulhu_w_512 : ClangBuiltin<"__builtin_ia32_pmulhuw512">,
- DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty],
- [IntrNoMem, Commutative]>;
- def int_x86_avx512_pmulh_w_512 : ClangBuiltin<"__builtin_ia32_pmulhw512">,
- DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty],
- [IntrNoMem, Commutative]>;
def int_x86_avx512_pavg_b_512 : ClangBuiltin<"__builtin_ia32_pavgb512">,
DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty, llvm_v64i8_ty],
[IntrNoMem]>;
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index e9c1b9fa95376..aebbd278cdcf9 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -2297,20 +2297,6 @@ static void computeKnownBitsFromOperator(const Operator *I,
Known &= Known2.anyextOrTrunc(BitWidth);
break;
}
- case Intrinsic::x86_sse2_pmulh_w:
- case Intrinsic::x86_avx2_pmulh_w:
- case Intrinsic::x86_avx512_pmulh_w_512:
- computeKnownBits(I->getOperand(0), DemandedElts, Known, Q, Depth + 1);
- computeKnownBits(I->getOperand(1), DemandedElts, Known2, Q, Depth + 1);
- Known = KnownBits::mulhs(Known, Known2);
- break;
- case Intrinsic::x86_sse2_pmulhu_w:
- case Intrinsic::x86_avx2_pmulhu_w:
- case Intrinsic::x86_avx512_pmulhu_w_512:
- computeKnownBits(I->getOperand(0), DemandedElts, Known, Q, Depth + 1);
- computeKnownBits(I->getOperand(1), DemandedElts, Known2, Q, Depth + 1);
- Known = KnownBits::mulhu(Known, Known2);
- break;
case Intrinsic::x86_sse42_crc32_64_64:
Known.Zero.setBitsFrom(32);
break;
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 9d42f940becd8..e5fb708a56453 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -212,6 +212,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name.starts_with("pmin") || // Added in 3.9
Name.starts_with("pmovsx") || // Added in 3.9
Name.starts_with("pmovzx") || // Added in 3.9
+ Name.starts_with("pmulh.w") || // Added in 24.0
+ Name.starts_with("pmulhu.w") || // Added in 24.0
Name == "pmul.dq" || // Added in 7.0
Name == "pmulu.dq" || // Added in 7.0
Name.starts_with("psll.dq") || // Added in 3.7
@@ -438,6 +440,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name == "kxor.w" || // Added in 7.0
Name.starts_with("padds.") || // Added in 8.0
Name.starts_with("pbroadcast") || // Added in 3.9
+ Name.starts_with("pmulh.w") || // Added in 24.0
+ Name.starts_with("pmulhu.w") || // Added in 24.0
Name.starts_with("prol") || // Added in 8.0
Name.starts_with("pror") || // Added in 8.0
Name.starts_with("psll.dq") || // Added in 3.9
@@ -490,6 +494,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name == "pmaxu.b" || // Added in 3.9
Name == "pmins.w" || // Added in 3.9
Name == "pminu.b" || // Added in 3.9
+ Name == "pmulh.w" || // Added in 24.0
+ Name == "pmulhu.w" || // Added in 24.0
Name == "pmulu.dq" || // Added in 7.0
Name.starts_with("pshuf") || // Added in 3.9
Name.starts_with("psll.dq") || // Added in 3.7
@@ -3057,24 +3063,16 @@ static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder,
IID = Intrinsic::x86_avx512_pmul_hr_sw_512;
else
llvm_unreachable("Unexpected intrinsic");
- } else if (Name.starts_with("pmulh.w.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse2_pmulh_w;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmulh_w;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmulh_w_512;
- else
- llvm_unreachable("Unexpected intrinsic");
- } else if (Name.starts_with("pmulhu.w.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse2_pmulhu_w;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmulhu_w;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmulhu_w_512;
- else
- llvm_unreachable("Unexpected intrinsic");
+ } else if (Name.starts_with("pmulh.w")) {
+ assert((VecWidth == 128 || VecWidth == 256 || VecWidth == 512) &&
+ "Unexpected intrinsic");
+ Rep = upgradeX86BinaryIntrinsics(Builder, CI, Intrinsic::smulh);
+ return true;
+ } else if (Name.starts_with("pmulhu.w")) {
+ assert((VecWidth == 128 || VecWidth == 256 || VecWidth == 512) &&
+ "Unexpected intrinsic");
+ Rep = upgradeX86BinaryIntrinsics(Builder, CI, Intrinsic::umulh);
+ return true;
} else if (Name.starts_with("pmaddw.d.")) {
if (VecWidth == 128)
IID = Intrinsic::x86_sse2_pmadd_wd;
@@ -3773,6 +3771,12 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F,
Name == "sse41.pminud" || Name.starts_with("avx2.pminu") ||
Name.starts_with("avx512.mask.pminu")) {
Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umin);
+ } else if (Name == "sse2.pmulh.w" || Name.starts_with("avx2.pmulh.w") ||
+ Name.starts_with("avx512.pmulh.w")) {
+ Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smulh);
+ } else if (Name == "sse2.pmulhu.w" || Name.starts_with("avx2.pmulhu.w") ||
+ Name.starts_with("avx512.pmulhu.w")) {
+ Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umulh);
} else if (Name == "sse2.pmulu.dq" || Name == "avx2.pmulu.dq" ||
Name == "avx512.pmulu.dq.512" ||
Name.starts_with("avx512.mask.pmulu.dq.")) {
diff --git a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
index 55d67084b7513..07fa36594c37e 100644
--- a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/X86/X86InstCo...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/227663
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