[llvm] a04805e - SLP: Remove artificial shifts from min-bitwidth test (NFC) (#222634)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 05:02:00 PDT 2026
Author: Hari Limaye
Date: 2026-10-01T13:01:50+01:00
New Revision: a04805eff3ccd42bf8cd6056d6c75f63f42a2522
URL: https://github.com/llvm/llvm-project/commit/a04805eff3ccd42bf8cd6056d6c75f63f42a2522
DIFF: https://github.com/llvm/llvm-project/commit/a04805eff3ccd42bf8cd6056d6c75f63f42a2522.diff
LOG: SLP: Remove artificial shifts from min-bitwidth test (NFC) (#222634)
Replace shifts by zero with zero constants, using a slightly negative
threshold to preserve the test signal. This allows a future update to
the cost of foldable shifts.
Added:
Modified:
llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
index f18bc72a124a3..ae6aede2273d9 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
@@ -1,47 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
-; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-8 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
-define void @h(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o) {
+define void @h(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i32 %arg) {
; CHECK-LABEL: define void @h(
-; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i16 [[C:%.*]], i16 [[D:%.*]], i16 [[E:%.*]], i16 [[F:%.*]], i16 [[G:%.*]], i16 [[H:%.*]], i16 [[I:%.*]], i16 [[J:%.*]], i16 [[K:%.*]], i16 [[L:%.*]], i16 [[M:%.*]], i16 [[N:%.*]], i16 [[O:%.*]]) {
+; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i16 [[C:%.*]], i16 [[D:%.*]], i16 [[E:%.*]], i16 [[F:%.*]], i16 [[G:%.*]], i16 [[H:%.*]], i16 [[I:%.*]], i16 [[J:%.*]], i16 [[K:%.*]], i16 [[L:%.*]], i16 [[M:%.*]], i16 [[N:%.*]], i16 [[O:%.*]], i32 [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV9:%.*]] = zext i16 [[A]] to i32
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
-; CHECK-NEXT: [[CONV310:%.*]] = zext i16 [[B]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> poison, i16 [[D]], i64 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[G]], i64 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[K]], i64 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[O]], i64 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[C]], i64 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[F]], i64 5
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[J]], i64 6
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[N]], i64 7
-; CHECK-NEXT: [[CONV3_112:%.*]] = zext i16 [[E]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i16> poison, i16 [[H]], i64 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP8]], i16 [[L]], i64 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i16> poison, i16 [[I]], i64 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i16> [[TMP10]], i16 [[M]], i64 1
-; CHECK-NEXT: [[SUB39_3:%.*]] = or i32 [[CONV310]], [[CONV9]]
-; CHECK-NEXT: [[SUB39_2:%.*]] = or i32 [[CONV9]], [[CONV310]]
-; CHECK-NEXT: [[ADD4_1:%.*]] = or i32 [[CONV3_112]], 0
-; CHECK-NEXT: [[SUB44_2:%.*]] = or i32 0, [[CONV3_112]]
-; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> zeroinitializer, [[TMP7]]
-; CHECK-NEXT: [[CONV40_2:%.*]] = trunc i32 [[SUB39_2]] to i16
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> poison, i16 [[CONV40_2]], i64 0
-; CHECK-NEXT: [[CONV45_2:%.*]] = trunc i32 [[SUB44_2]] to i16
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[CONV45_2]], i64 1
-; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i16> zeroinitializer, [[TMP11]]
-; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i16> [[TMP17]], <2 x i16> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <8 x i16> [[TMP16]], <8 x i16> [[TMP18]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[CONV40_3:%.*]] = trunc i32 [[SUB39_3]] to i16
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <8 x i16> [[TMP19]], i16 [[CONV40_3]], i64 4
-; CHECK-NEXT: [[TMP22:%.*]] = trunc i32 [[ADD4_1]] to i16
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <8 x i16> [[TMP21]], i16 [[TMP22]], i64 5
-; CHECK-NEXT: [[TMP24:%.*]] = or <2 x i16> zeroinitializer, [[TMP9]]
-; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i16> [[TMP24]], <2 x i16> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <8 x i16> [[TMP23]], <8 x i16> [[TMP25]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
-; CHECK-NEXT: [[TMP27:%.*]] = or <8 x i16> [[TMP26]], [[TMP12]]
-; CHECK-NEXT: store <8 x i16> [[TMP27]], ptr [[ARRAYIDX2]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[I]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[M]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> poison, i16 [[D]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[G]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[K]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[O]], i64 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[C]], i64 4
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[F]], i64 5
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP10]], i16 [[J]], i64 6
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[N]], i64 7
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> poison, i32 [[ARG]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i32> [[TMP13]], <8 x i32> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP15:%.*]] = ashr <8 x i32> [[TMP14]], splat (i32 5)
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x i16> poison, i16 [[H]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x i16> [[TMP16]], i16 [[L]], i64 1
+; CHECK-NEXT: [[TMP18:%.*]] = zext <2 x i16> [[TMP17]] to <2 x i32>
+; CHECK-NEXT: [[TMP19:%.*]] = trunc <8 x i32> [[TMP15]] to <8 x i16>
+; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i16> [[TMP19]], [[TMP12]]
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[CONV9]], i64 0
+; CHECK-NEXT: [[TMP22:%.*]] = or <4 x i32> [[TMP21]], [[TMP4]]
+; CHECK-NEXT: [[TMP23:%.*]] = trunc <4 x i32> [[TMP22]] to <4 x i16>
+; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i16> [[TMP23]], <4 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i32> [[TMP18]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP25]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT: [[TMP27:%.*]] = or <4 x i32> [[TMP26]], [[TMP21]]
+; CHECK-NEXT: [[TMP28:%.*]] = trunc <4 x i32> [[TMP27]] to <4 x i16>
+; CHECK-NEXT: [[TMP29:%.*]] = shufflevector <4 x i16> [[TMP28]], <4 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <8 x i16> [[TMP24]], <8 x i16> [[TMP29]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+; CHECK-NEXT: [[TMP31:%.*]] = or <8 x i16> [[TMP30]], [[TMP20]]
+; CHECK-NEXT: store <8 x i16> [[TMP31]], ptr [[ARRAYIDX2]], align 2
; CHECK-NEXT: ret void
;
entry:
@@ -51,11 +49,11 @@ entry:
%add4 = or i32 %conv310, %conv9
%sub = or i32 %conv9, %conv310
%conv15 = sext i16 %c to i32
- %shr = ashr i32 0, 0
+ %shr = ashr i32 %arg, 5
%arrayidx18 = getelementptr i8, ptr null, i64 24
%conv19 = sext i16 %d to i32
%sub20 = or i32 %shr, %conv19
- %shr29 = ashr i32 0, 0
+ %shr29 = ashr i32 %arg, 5
%add30 = or i32 %shr29, %conv15
%sub39 = or i32 %sub, %sub20
%conv40 = trunc i32 %sub39 to i16
@@ -68,11 +66,11 @@ entry:
%add4.1 = or i32 %conv3.112, 0
%sub.1 = or i32 0, %conv3.112
%conv15.1 = sext i16 %f to i32
- %shr.1 = ashr i32 0, 0
+ %shr.1 = ashr i32 %arg, 5
%arrayidx18.1 = getelementptr i8, ptr null, i64 26
%conv19.1 = sext i16 %g to i32
%sub20.1 = or i32 %shr.1, %conv19.1
- %shr29.1 = ashr i32 0, 0
+ %shr29.1 = ashr i32 %arg, 5
%add30.1 = or i32 %shr29.1, %conv15.1
%sub39.1 = or i32 %sub.1, %sub20.1
%conv40.1 = trunc i32 %sub39.1 to i16
@@ -86,11 +84,11 @@ entry:
%add4.2 = or i32 0, %conv.213
%sub.2 = or i32 0, %conv3.214
%conv15.2 = sext i16 %j to i32
- %shr.2 = ashr i32 0, 0
+ %shr.2 = ashr i32 %arg, 5
%arrayidx18.2 = getelementptr i8, ptr null, i64 28
%conv19.2 = sext i16 %k to i32
%sub20.2 = or i32 %shr.2, %conv19.2
- %shr29.2 = ashr i32 0, 0
+ %shr29.2 = ashr i32 %arg, 5
%add30.2 = or i32 %shr29.2, %conv15.2
%sub39.2 = or i32 %sub.2, %sub20.2
%conv40.2 = trunc i32 %sub39.2 to i16
@@ -104,11 +102,11 @@ entry:
%add4.3 = or i32 0, %conv.315
%sub.3 = or i32 0, %conv3.316
%conv15.3 = sext i16 %n to i32
- %shr.3 = ashr i32 0, 0
+ %shr.3 = ashr i32 %arg, 5
%arrayidx18.3 = getelementptr i8, ptr null, i64 30
%conv19.3 = sext i16 %o to i32
%sub20.3 = or i32 %shr.3, %conv19.3
- %shr29.3 = ashr i32 0, 0
+ %shr29.3 = ashr i32 %arg, 5
%add30.3 = or i32 %shr29.3, %conv15.3
%sub39.3 = or i32 %sub.3, %sub20.3
%conv40.3 = trunc i32 %sub39.3 to i16
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