Author: Arseniy Obolenskiy
Date: 2026-10-01T13:42:09+02:00
New Revision: 0704576db68c95ec1835771965824ba4ed4924cb
URL: https://github.com/llvm/llvm-project/commit/0704576db68c95ec1835771965824ba4ed4924cb
DIFF: https://github.com/llvm/llvm-project/commit/0704576db68c95ec1835771965824ba4ed4924cb.diff
LOG: [AMDGPU] Reject 64-bit VOP1 DPP on gfx8/gfx9 (#220834)
64-bit DPP needs FeatureDPALU_DPP (gfx90a+), but HasDPALU_DPP is missing
GCN3Encoding gate that HasDPP has
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOPInstructions.td
llvm/test/MC/AMDGPU/dpp-err.s
llvm/test/MC/AMDGPU/gfx9-asm-err.s
llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 26997261a4922..daaf20bb6fab0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -3198,6 +3198,10 @@ def HasSDWA10 :
def HasDPP : Predicate<"Subtarget->hasDPP()">,
AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
+def HasGCN3DPALU_DPP :
+ Predicate<"Subtarget->isGCN3Encoding() && Subtarget->hasDPALU_DPP()">,
+ AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPALU_DPP)>;
+
def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index f343e58309ba7..2d794a45a25ac 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -1647,9 +1647,7 @@ multiclass VOP1_Real_vi <bits<10> op> {
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
def _dpp_vi :
VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
- VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")> {
- let AssemblerPredicate = isGFX8GFX9;
- }
+ VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;
}
defm V_NOP : VOP1_Real_vi <0x0>;
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index ee02bdcc3975f..4e5b01c92334c 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1033,7 +1033,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
string AsmOperands = asmOps;
let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", "");
- let AssemblerPredicate = !if(P.HasExt64BitDPP, HasDPALU_DPP, HasDPP);
+ let AssemblerPredicate = !if(P.HasExt64BitDPP, HasGCN3DPALU_DPP, HasDPP);
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
AMDGPUAsmVariants.Disable);
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
diff --git a/llvm/test/MC/AMDGPU/dpp-err.s b/llvm/test/MC/AMDGPU/dpp-err.s
index 16fdf5cef0e4e..29533bc69f1a6 100644
--- a/llvm/test/MC/AMDGPU/dpp-err.s
+++ b/llvm/test/MC/AMDGPU/dpp-err.s
@@ -36,3 +36,17 @@ v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1
v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1
// GFX89: v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x43,0x01,0x11]
// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
+
+// DPP with a 64-bit VGPR operand requires gfx90a+ (FeatureDPALU_DPP).
+
+v_cvt_f64_i32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+
+v_cvt_f64_u32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+
+v_cvt_f64_f32_dpp v[0:1], v2 quad_perm:[2,3,0,1] row_mask:0x1 bank_mask:0x1
+// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
+// GFX10-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
index cef5e7d8fc6e6..2fcf793befbe3 100644
--- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s
+++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
@@ -38,7 +38,7 @@ v_cvt_f16_u16_e64 v5, 0.6
// GFX9ERR: :[[@LINE-1]]:23: error: literal operands are not supported
v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf
-// GFX9ERR: :[[@LINE-1]]:19: error: invalid operand for instruction
+// GFX9ERR: :[[@LINE-1]]:26: error: not a valid operand.
v_subrev_u16_e64 v5, v1, -4.2
// GFX9ERR: :[[@LINE-1]]:26: error: literal operands are not supported
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
index 6f35752b8e492..6a1f9e577a40d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
@@ -22,3 +22,10 @@
0xf9,0x04,0x00,0x02,0x01,0x06,0x06,0x07
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# v_cvt_f64_i32_dpp and v_ceil_f64_dpp: 64-bit VGPR DPP needs gfx90a+.
+0xfa,0x08,0x00,0x7e,0x02,0x4e,0x00,0xff
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xfa,0x30,0x00,0x7e,0x02,0x4e,0x00,0xff
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding