[llvm] AArch64: Mark the dead status flag clobbers in the SME ABI pass (PR #228042)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 04:23:46 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/228042
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
>From 1b6934af99262dc239546cd0e33863a581839b11 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 29 Sep 2026 02:57:45 +0200
Subject: [PATCH] AArch64: Mark the dead status flag clobbers in the SME ABI
pass
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
---
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 37 +++++++++-----
.../AArch64/aarch64-sme-za-call-lowering.ll | 8 +--
.../AArch64/machine-sme-abi-dead-nzcv.ll | 20 ++++++++
.../machine-sme-abi-find-insert-pt.mir | 16 +++---
.../AArch64/machine-sme-abi-live-nzcv.mir | 51 +++++++++++++++++++
.../machine-sme-abi-skip-debug-inst.mir | 4 +-
.../CodeGen/AArch64/sme-abi-eh-liveins.mir | 8 +--
.../AArch64/sme-lazy-sve-nzcv-live.mir | 4 +-
8 files changed, 115 insertions(+), 33 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/machine-sme-abi-dead-nzcv.ll
create mode 100644 llvm/test/CodeGen/AArch64/machine-sme-abi-live-nzcv.mir
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index 5dd62d1d66278a5..7c38d6cf1a517ea 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -326,7 +326,7 @@ struct MachineSMEABI : public MachineFunctionPass {
void emitAllocateLazySaveBuffer(EmitContext &, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
void emitZAMode(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- bool ClearTPIDR2, bool On);
+ bool ClearTPIDR2, bool On, LiveRegs PhysLiveRegs);
// Emission routines for agnostic ZA functions.
void emitSetupFullZASave(MachineBasicBlock &MBB,
@@ -767,7 +767,8 @@ PhysRegSave MachineSMEABI::createPhysRegSave(LiveRegs PhysLiveRegs,
RegSave.StatusFlags = MRI->createVirtualRegister(&AArch64::GPR64RegClass);
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MRS), RegSave.StatusFlags)
.addImm(AArch64SysReg::NZCV)
- .addReg(AArch64::NZCV, RegState::Implicit);
+ .addReg(AArch64::NZCV, RegState::Implicit)
+ .setOperandDead(2); // implicit-def $nzcv
}
// Note: Preserving X0 is "free" as this is before register allocation, so
// the register allocator is still able to optimize these copies.
@@ -825,10 +826,12 @@ void MachineSMEABI::emitRestoreLazySave(EmitContext &Context,
// Enable ZA.
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MSRpstatesvcrImm1))
.addImm(AArch64SVCR::SVCRZA)
- .addImm(1);
+ .addImm(1)
+ .setOperandDead(2); // implicit-def $nzcv
// Get current TPIDR2_EL0.
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MRS), TPIDR2EL0)
- .addImm(AArch64SysReg::TPIDR2_EL0);
+ .addImm(AArch64SysReg::TPIDR2_EL0)
+ .setOperandDead(2); // implicit-def $nzcv
// Get pointer to TPIDR2 block.
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ADDXri), TPIDR2)
.addFrameIndex(Context.getTPIDR2Block(*MF))
@@ -851,7 +854,8 @@ void MachineSMEABI::emitRestoreLazySave(EmitContext &Context,
void MachineSMEABI::emitZAMode(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- bool ClearTPIDR2, bool On) {
+ bool ClearTPIDR2, bool On,
+ LiveRegs PhysLiveRegs) {
DebugLoc DL = getDebugLoc(MBB, MBBI);
if (ClearTPIDR2)
@@ -860,9 +864,12 @@ void MachineSMEABI::emitZAMode(MachineBasicBlock &MBB,
.addReg(AArch64::XZR);
// Disable ZA.
- BuildMI(MBB, MBBI, DL, TII->get(AArch64::MSRpstatesvcrImm1))
- .addImm(AArch64SVCR::SVCRZA)
- .addImm(On ? 1 : 0);
+ MachineInstrBuilder ZAMode =
+ BuildMI(MBB, MBBI, DL, TII->get(AArch64::MSRpstatesvcrImm1))
+ .addImm(AArch64SVCR::SVCRZA)
+ .addImm(On ? 1 : 0);
+ if (!(PhysLiveRegs & LiveRegs::NZCV))
+ ZAMode.setOperandDead(2); // implicit-def $nzcv
}
void MachineSMEABI::emitAllocateLazySaveBuffer(
@@ -933,7 +940,8 @@ void MachineSMEABI::emitSMEPrologue(MachineBasicBlock &MBB,
Register TPIDR2EL0 = MRI->createVirtualRegister(&AArch64::GPR64RegClass);
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MRS))
.addReg(TPIDR2EL0, RegState::Define)
- .addImm(AArch64SysReg::TPIDR2_EL0);
+ .addImm(AArch64SysReg::TPIDR2_EL0)
+ .setOperandDead(2); // implicit-def $nzcv
// If TPIDR2_EL0 is non-zero, commit the lazy save.
// NOTE: Functions that only use ZT0 don't need to zero ZA.
auto CommitZASave =
@@ -951,7 +959,8 @@ void MachineSMEABI::emitSMEPrologue(MachineBasicBlock &MBB,
// Enable ZA (as ZA could have previously been in the OFF state).
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MSRpstatesvcrImm1))
.addImm(AArch64SVCR::SVCRZA)
- .addImm(1);
+ .addImm(1)
+ .setOperandDead(2); // implicit-def $nzcv
} else if (AFI->getSMEFnAttrs().hasSharedZAInterface()) {
if (ZeroZA)
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ZERO_M))
@@ -1130,7 +1139,8 @@ void MachineSMEABI::emitStateChange(EmitContext &Context,
// only possible when we _don't_ have ZA state.
assert(HasZT0State && !HasZAState && "Expect to only have ZT0 state.");
emitZT0SaveRestore(Context, MBB, InsertPt, /*IsSave=*/true);
- emitZAMode(MBB, InsertPt, /*ClearTPIDR2=*/false, /*On=*/false);
+ emitZAMode(MBB, InsertPt, /*ClearTPIDR2=*/false, /*On=*/false,
+ PhysLiveRegs);
break;
// This section handles: LOCAL_COMMITTED -> (OFF|LOCAL_SAVED)
@@ -1147,7 +1157,8 @@ void MachineSMEABI::emitStateChange(EmitContext &Context,
if (HasZAState)
emitZARestore(Context, MBB, InsertPt, PhysLiveRegs);
else
- emitZAMode(MBB, InsertPt, /*ClearTPIDR2=*/false, /*On=*/true);
+ emitZAMode(MBB, InsertPt, /*ClearTPIDR2=*/false, /*On=*/true,
+ PhysLiveRegs);
if (HasZT0State && To == ZAState::ACTIVE)
emitZT0SaveRestore(Context, MBB, InsertPt, /*IsSave=*/false);
break;
@@ -1159,7 +1170,7 @@ void MachineSMEABI::emitStateChange(EmitContext &Context,
assert(SMEFnAttrs.hasPrivateZAInterface() &&
"Did not expect to turn ZA off in shared/agnostic ZA function");
emitZAMode(MBB, InsertPt, /*ClearTPIDR2=*/From == ZAState::LOCAL_SAVED,
- /*On=*/false);
+ /*On=*/false, PhysLiveRegs);
break;
default:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
index d956a231ba92234..d383c43689da5a8 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
@@ -30,8 +30,8 @@ define void @requires_za_save() nounwind "aarch64_inout_za" {
; CHECK-AFTER-SMEABI-NEXT: RequiresZASavePseudo
; CHECK-AFTER-SMEABI-NEXT: BL @private_za_callee, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-AFTER-SMEABI-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-AFTER-SMEABI-NEXT: MSR 56965, $xzr
@@ -68,8 +68,8 @@ define void @requires_za_save_streaming_mode_change() nounwind "aarch64_inout_za
; CHECK-AFTER-SMEABI-NEXT: BL @private_za_callee, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
- ; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-AFTER-SMEABI-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-AFTER-SMEABI-NEXT: MSR 56965, $xzr
diff --git a/llvm/test/CodeGen/AArch64/machine-sme-abi-dead-nzcv.ll b/llvm/test/CodeGen/AArch64/machine-sme-abi-dead-nzcv.ll
new file mode 100644
index 000000000000000..2f4553eae1eaccf
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-sme-abi-dead-nzcv.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sme -stop-after=aarch64-machine-sme-abi < %s | FileCheck %s
+
+declare void @shared_za_callee() "aarch64_inout_za"
+
+define void @private_za() "aarch64_new_za" {
+ ; CHECK-LABEL: name: private_za
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
+ ; CHECK-NEXT: CommitZASavePseudo [[MRS]], 1, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: InOutZAUsePseudo
+ ; CHECK-NEXT: BL @shared_za_callee, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 0, implicit-def dead $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ call void @shared_za_callee()
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir b/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
index ed768dec779989a..cb3378e8726e83f 100644
--- a/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
+++ b/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
@@ -38,8 +38,8 @@ body: |
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
@@ -79,8 +79,8 @@ body: |
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
@@ -121,7 +121,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $sp
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: $zab0 = IMPLICIT_DEF
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def dead $nzcv, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[COPY1]]
; CHECK-NEXT: BL &__arm_sme_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x1, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: MSR 55824, [[MRS]], implicit-def $nzcv
@@ -199,9 +199,9 @@ body: |
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def $nzcv, implicit $nzcv
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
diff --git a/llvm/test/CodeGen/AArch64/machine-sme-abi-live-nzcv.mir b/llvm/test/CodeGen/AArch64/machine-sme-abi-live-nzcv.mir
new file mode 100644
index 000000000000000..3be5d41a9d236f9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-sme-abi-live-nzcv.mir
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -mattr=+sme -run-pass=aarch64-machine-sme-abi %s -o - | FileCheck %s
+
+# The ZA mode change clobbers the status flags, so the def is not dead if they
+# are live at the insertion point.
+
+--- |
+ define void @zt0_nzcv_live() "aarch64_new_zt0" {
+ call void @clobber()
+ ret void
+ }
+
+ declare void @clobber()
+...
+---
+name: zt0_nzcv_live
+tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
+ hasCalls: true
+machineFunctionInfo: {}
+body: |
+ bb.0 (%ir-block.0):
+ ; CHECK-LABEL: name: zt0_nzcv_live
+ ; CHECK: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
+ ; CHECK-NEXT: CommitZASavePseudo [[MRS]], 0, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zt0
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
+ ; CHECK-NEXT: STR_TX $zt0, [[ADDXri]]
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 0, implicit-def dead $nzcv
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: RequiresZT0SavePseudo
+ ; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+ ; CHECK-NEXT: $nzcv = IMPLICIT_DEF
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
+ ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
+ ; CHECK-NEXT: $zt0 = LDR_TX [[ADDXri1]]
+ ; CHECK-NEXT: $zt0 = IMPLICIT_DEF
+ ; CHECK-NEXT: FAKE_USE $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 0, implicit-def dead $nzcv
+ ; CHECK-NEXT: RET_ReallyLR
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ RequiresZT0SavePseudo
+ BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+ $nzcv = IMPLICIT_DEF
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $zt0 = IMPLICIT_DEF
+ FAKE_USE $nzcv
+ RET_ReallyLR
+...
diff --git a/llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir b/llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir
index 3ceca8eb10e4761..ee2fee63b47144d 100644
--- a/llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir
+++ b/llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir
@@ -50,8 +50,8 @@ body: |
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
diff --git a/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir b/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
index 711745e528bbfe1..bba78b3d3b4694d 100644
--- a/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
+++ b/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
@@ -35,8 +35,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
@@ -46,8 +46,8 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
diff --git a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
index 9a2811bc1abef10..f12b455ed3b3301 100644
--- a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
+++ b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
@@ -62,8 +62,8 @@ body: |
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
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