[llvm] [AMDGPU] Remove dead check lines from tests (NFC) (PR #228002)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 03:14:09 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/228002
>From c56864d530ce1f2e61b18ffc803c502a9921bf23 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 11:06:53 +0200
Subject: [PATCH 1/2] [AMDGPU] Remove dead check lines from tests (NFC)
---
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 3 ---
llvm/test/CodeGen/AMDGPU/and_or.ll | 1 -
llvm/test/CodeGen/AMDGPU/cc-update.ll | 19 -------------
.../AMDGPU/fp-min-max-buffer-ptr-atomics.ll | 1 -
.../CodeGen/AMDGPU/function-args-inreg.ll | 27 -------------------
.../CodeGen/AMDGPU/implicit-arg-v5-opt.ll | 1 -
.../llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll | 1 -
.../si-optimize-vgpr-live-range-dbg-instr.mir | 1 -
llvm/test/MC/AMDGPU/gfx12_asm_sop2.s | 2 --
.../AMDGPU/gfx11_dasm_vop1_dpp8.txt | 6 -----
.../AtomicExpand/AMDGPU/expand-atomic-i8.ll | 1 -
11 files changed, 63 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 18ed68396fa4fa5..2b77ec04cf2b6a8 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -165,9 +165,6 @@ define amdgpu_kernel void @use_flat_to_group_addrspacecast(ptr %ptr) #0 {
; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
; HSA: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]]
-; CI-DAG v_cmp_ne_u64_e64 vcc, s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
-; CI-DAG v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
-; CI-DAG v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
; CI-DAG: v_cmp_ne_u64_e64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
; CI-DAG: s_and_b64 s{{[[0-9]+:[0-9]+]}}, s[[[CMP_LO]]:[[CMP_HI]]], exec
; CI-DAG: s_cselect_b32 [[CASTPTR:s[0-9]+]], s[[PTR_LO]], -1
diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 369676fbb3ed075..696adcbde4c0f20 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -372,7 +372,6 @@ define <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DAG: s_movk_i32 [[SR0:s[0-9]+]], 0x808
; GFX10-DAG: s_movk_i32 [[SR1:s[0-9]+]], 0x809
-; GFX10-CHECK-NOT: {{.}}
; GFX10-DAG: v_and_or_b32 v0, v0, [[SR0]], 0x81
; GFX10-DAG: v_and_or_b32 v1, v1, [[SR1]], 0x101
%x = and <2 x i32> %a, <i32 2056, i32 2057>
diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll
index 1bc5423f50e84b1..a00625770e32799 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll
@@ -397,25 +397,6 @@ define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
; GFX1100-NEXT: s_mov_b32 s32, 0
; GFX1100-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX1100-NEXT: s_endpgm
-; GFX1010-NEXT s_add_u32 s12, s12, s17
-; GFX1010-NEXT s_mov_b32 s33, 0
-; GFX1010-NEXT s_mov_b32 s32, 0
-; GFX1010-NEXT s_addc_u32 s13, s13, 0
-; GFX1010-NEXT s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; GFX1010-NEXT s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
-; GFX1010-NEXT v_lshlrev_b32_e32 v2, 20, v2
-; GFX1010-NEXT v_lshlrev_b32_e32 v1, 10, v1
-; GFX1010-NEXT s_add_u32 s0, s0, s17
-; GFX1010-NEXT s_addc_u32 s1, s1, 0
-; GFX1010-NEXT s_mov_b32 s12, s14
-; GFX1010-NEXT s_mov_b32 s13, s15
-; GFX1010-NEXT v_or3_b32 v31, v0, v1, v2
-; GFX1010-NEXT s_mov_b32 s14, s16
-; GFX1010-NEXT s_getpc_b64 s[18:19]
-; GFX1010-NEXT s_add_u32 s18, s18, ex at rel32@lo+4
-; GFX1010-NEXT s_addc_u32 s19, s19, ex at rel32@hi+12
-; GFX1010-NEXT s_swappc_b64 s[30:31], s[18:19]
-; GFX1010-NEXT s_endpgm
entry:
tail call void @ex() #2
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
index 768b1d5cfdbda02..d0a0583cccfebdb 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
@@ -416,7 +416,6 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f32_off4_slc(ptr addrsp
; G_GFX1310-NEXT: s_wait_loadcnt 0x0
; G_GFX1310-NEXT: ds_store_b32 v1, v0
; G_GFX1310-NEXT: s_endpgm
-; GFX1010-LABEL: raw_ptr_buffer_atomic_min_rtn_f32_off4_slc:
main_body:
%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f32(float %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
store float %ret, ptr addrspace(3) %out, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index 38eee088d0902b0..236ee76c77c2f3e 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -2104,33 +2104,6 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr
; GFX11-NEXT: s_mov_b32 s33, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT s_mov_b32 s3, s33
-; GFX11-NEXT s_mov_b32 s33, s32
-; GFX11-NEXT s_or_saveexec_b32 s4, -1
-; GFX11-NEXT scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT s_mov_b32 exec_lo, s4
-; GFX11-NEXT s_add_i32 s32, s32, 16
-; GFX11-NEXT s_getpc_b64 s[4:5]
-; GFX11-NEXT s_add_u32 s4, s4, caller_void_func_i32_v2float_inreg at gotpcrel32@lo+4
-; GFX11-NEXT s_addc_u32 s5, s5, caller_void_func_i32_v2float_inreg at gotpcrel32@hi+12
-; GFX11-NEXT v_writelane_b32 v40, s3, 2
-; GFX11-NEXT s_load_b64 s[4:5], s[4:5], 0x0
-; GFX11-NEXT v_writelane_b32 v40, s30, 0
-; GFX11-NEXT v_writelane_b32 v40, s31, 1
-; GFX11-NEXT s_waitcnt lgkmcnt(0)
-; GFX11-NEXT s_swappc_b64 s[30:31], s[4:5]
-; GFX11-NEXT s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT v_readlane_b32 s31, v40, 1
-; GFX11-NEXT v_readlane_b32 s30, v40, 0
-; GFX11-NEXT v_readlane_b32 s0, v40, 2
-; GFX11-NEXT s_or_saveexec_b32 s1, -1
-; GFX11-NEXT scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT s_mov_b32 exec_lo, s1
-; GFX11-NEXT s_add_i32 s32, s32, -16
-; GFX11-NEXT s_mov_b32 s33, s0
-; GFX11-NEXT s_waitcnt vmcnt(0)
-; GFX11-NEXT s_setpc_b64 s[30:31]
call void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inreg %arg1)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll b/llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
index f1ee94828089e9b..a482711ae6a8860 100644
--- a/llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
@@ -306,7 +306,6 @@ define i16 @get_grid_dims_i16() #2 {
; Ignore wrong type
define half @get_grid_dims_f16() #2 {
-; GCN-half: @get_grid_dims_i16(
; GCN-LABEL: @get_grid_dims_f16(
; GCN-NEXT: [[IMPLICITARG_PTR:%.*]] = tail call dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; GCN-NEXT: [[GEP_GRID_DIMS:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 64
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
index d21852ef60f9a14..64e243f959cf5ab 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
@@ -10,7 +10,6 @@ declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, fl
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)
define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {
-; GFX1210-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
diff --git a/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir b/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
index 7e4caed398a9107..8974ae94a8358db 100644
--- a/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
@@ -70,7 +70,6 @@ body: |
; GCN-NEXT: SI_END_CF [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: DBG_VALUE_LIST !4, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 2712, DW_OP_mul, DW_OP_plus, DW_OP_plus_uconst, 2680, DW_OP_stack_value), [[GLOBAL_LOAD_DWORDX2_]], 0, debug-location !DILocation(line: 0, scope: !5)
; GCN-NEXT: SI_RETURN
- ; GCN-NEXT-SAME: %9
bb.0:
successors: %bb.3(0x40000000), %bb.1(0x40000000)
liveins: $vgpr0
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
index 302bf8e5fc80546..b8a80bc675d6911 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
@@ -680,11 +680,9 @@ s_fmamk_f32 s5, s1, 0x11213141, s105
s_fmamk_f32 s5, 0x11213141, 0x11213141, s105
// GFX12: s_fmamk_f32 s5, 0x11213141, 0x11213141, s105 ; encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11]
-// GFX12 encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11]
s_fmamk_f32 s5, s105, 0x11213141, 0x11213141
// GFX12: s_fmamk_f32 s5, s105, 0x11213141, 0x11213141 ; encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11]
-// GFX12 encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11]
s_fmaak_f32 s5, s1, s2, 0x11213141
// GFX12: s_fmaak_f32 s5, s1, s2, 0x11213141 ; encoding: [0x01,0x02,0x85,0xa2,0x41,0x31,0x21,0x11]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
index 7ee605289fd9cbc..cb60e7a0914bf72 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
@@ -397,23 +397,17 @@
# GFX11-FAKE16: v_frexp_mant_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
-# GFX11-FAKE16-REAL16: v_frexp_mant_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
-# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05
# GFX11: v_frexp_mant_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05]
-# GFX11-FAKE16-REAL16: v_frexp_mant_f16_dpp v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
-# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05
# GFX11-FAKE16: v_frexp_mant_f16_dpp v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
-# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05
# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
index cb19293cbcd5559..440f860771584dc 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
@@ -2284,7 +2284,6 @@ define i8 @test_atomicrmw_usub_cond_i8_flat_agent_align2(ptr %ptr, i8 %value) {
; R600-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i8
; R600-NEXT: ret i8 [[EXTRACTED3]]
;
-; R600NEXT: [[PTRLSB:%.*]] = and i32 [[TMP1]], 3
%res = atomicrmw usub_cond ptr %ptr, i8 %value syncscope("agent") seq_cst, align 2
ret i8 %res
}
>From 5fd214b0ab8dfcce0dd99642e444953859b7c11f Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 12:13:51 +0200
Subject: [PATCH 2/2] and_or
---
llvm/test/CodeGen/AMDGPU/and_or.ll | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 696adcbde4c0f20..e5dc088e219e9dd 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -374,6 +374,7 @@ define <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
; GFX10-DAG: s_movk_i32 [[SR1:s[0-9]+]], 0x809
; GFX10-DAG: v_and_or_b32 v0, v0, [[SR0]], 0x81
; GFX10-DAG: v_and_or_b32 v1, v1, [[SR1]], 0x101
+; GFX10-NEXT: s_setpc_b64 s[30:31]
%x = and <2 x i32> %a, <i32 2056, i32 2057>
%result = or <2 x i32> %x, <i32 129, i32 257>
ret <2 x i32> %result
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