[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -84,74 +103,76 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
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FlyGoat wrote:

> `$r2` would make it more annoying to debug. We would rather print an ABI name, we are just trying to understand how this can be implemented, and were wondering whether you had any ideas already.

I just pushed my draft local implementation: https://github.com/llvm/llvm-project/pull/228017

https://github.com/llvm/llvm-project/pull/224284