[llvm] [Mips] Print ABI register names in MIR (PR #228017)

[Jiaxun Yang via llvm-commits]

https://github.com/FlyGoat created https://github.com/llvm/llvm-project/pull/228017

## Summary

- Add a `TargetRegisterInfo` hook for physical register names in MIR and use it for both printing and parsing.
- Select MIPS GPR names from the subtarget ABI, keeping `_64` suffixes to distinguish register widths.

This is a draft implementation of the approach discussed in #224284. Existing MIR test fixtures have not been migrated.

## Validation

- Built `llc` with MIPS enabled.
- `git diff --check` passed.


>From 52f8098996d72cc4f6147998d91d9f56c7d1bcb1 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: Thu, 1 Oct 2026 11:06:29 +0100
Subject: [PATCH] [Mips] Print ABI register names in MIR

---
 llvm/include/llvm/CodeGen/TargetRegisterInfo.h |  6 ++++++
 llvm/lib/CodeGen/MIRParser/MIParser.cpp        |  2 +-
 llvm/lib/CodeGen/TargetRegisterInfo.cpp        |  2 +-
 llvm/lib/Target/Mips/MipsRegisterInfo.cpp      | 18 ++++++++++++++++++
 llvm/lib/Target/Mips/MipsRegisterInfo.h        |  5 +++++
 5 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 4678773607377..ae0f5dc4d42c7 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1044,6 +1044,12 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
     return StringRef(getName(Reg));
   }
 
+  /// Return the name used to serialize a physical register in MIR. Targets
+  /// with ABI-dependent register names may override this for each subtarget.
+  virtual StringRef getMIRRegName(MCRegister Reg) const {
+    return getName(Reg);
+  }
+
   //===--------------------------------------------------------------------===//
   /// Subtarget Hooks
 
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 7b45d028efdd7..3fac33fc172e2 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -109,7 +109,7 @@ void PerTargetMIParsingState::initNames2Regs() {
 
   for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
     bool WasInserted =
-        Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
+        Names2Regs.insert(std::make_pair(TRI->getMIRRegName(I).lower(), I))
             .second;
     (void)WasInserted;
     assert(WasInserted && "Expected registers to be unique case-insensitively");
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 79b01d27d91a5..bfe31e1f2b9ad 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -122,7 +122,7 @@ Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,
       OS << '$' << "physreg" << Reg.id();
     else if (Reg < TRI->getNumRegs()) {
       OS << '$';
-      printLowerCase(TRI->getName(Reg), OS);
+      printLowerCase(TRI->getMIRRegName(Reg), OS);
     } else
       llvm_unreachable("Register kind is unsupported.");
 
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index d68ab86dd0efe..0785aa1bb7906 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -12,6 +12,7 @@
 
 #include "MipsRegisterInfo.h"
 #include "MCTargetDesc/MipsABIInfo.h"
+#include "MCTargetDesc/MipsInstPrinter.h"
 #include "Mips.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
@@ -40,6 +41,23 @@ using namespace llvm;
 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
     : MipsGenRegisterInfo(Mips::RA), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
   MIPS_MC::initLLVMToCVRegMapping(this);
+  MIRRegNames.resize(getNumRegs());
+  const auto &GPR32 = *getRegClass(Mips::GPR32RegClassID);
+  const auto &GPR64 = *getRegClass(Mips::GPR64RegClassID);
+  for (unsigned I = 1; I < getNumRegs(); ++I) {
+    if (GPR32.contains(I) || GPR64.contains(I)) {
+      MIRRegNames[I] = MipsInstPrinter::getRegisterName(
+          I, STI.getABI().getRegAltNameIndex());
+      if (GPR64.contains(I))
+        MIRRegNames[I] += "_64";
+    }
+  }
+}
+
+StringRef MipsRegisterInfo::getMIRRegName(MCRegister Reg) const {
+  if (!MIRRegNames[Reg.id()].empty())
+    return MIRRegNames[Reg.id()];
+  return getName(Reg);
 }
 
 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.h b/llvm/lib/Target/Mips/MipsRegisterInfo.h
index 80ba23d173cbc..0096b239dd8ff 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.h
@@ -16,6 +16,8 @@
 #include "Mips.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include <cstdint>
+#include <string>
+#include <vector>
 
 #define GET_REGINFO_HEADER
 #include "MipsGenRegisterInfo.inc"
@@ -28,10 +30,13 @@ using TargetRegisterClass = MCRegisterClass;
 class MipsRegisterInfo : public MipsGenRegisterInfo {
 private:
   const bool ArePtrs64bit;
+  std::vector<std::string> MIRRegNames;
 
 public:
   explicit MipsRegisterInfo(const MipsSubtarget &STI);
 
+  StringRef getMIRRegName(MCRegister Reg) const override;
+
   /// Get PIC indirect call register
   static unsigned getPICCallReg();