[llvm] c6afcd0 - [AArch64][NeoverseV1/V2] Fix FMULX scalar latency (#224540)

[via llvm-commits]

Author: Julien Villette
Date: 2026-10-01T10:05:58Z
New Revision: c6afcd0b4ab5f089572bb8a2f8a9134fc5c59fc5

URL: https://github.com/llvm/llvm-project/commit/c6afcd0b4ab5f089572bb8a2f8a9134fc5c59fc5
DIFF: https://github.com/llvm/llvm-project/commit/c6afcd0b4ab5f089572bb8a2f8a9134fc5c59fc5.diff

LOG: [AArch64][NeoverseV1/V2] Fix FMULX scalar latency (#224540)

The "ASIMD FP multiply" InstRW regex required a "v" suffix, so the
scalar register-register forms FMULX16, FMULX32 and FMULX64 fell back to
a generic class with latency 2.

Measured on Neoverse V1 and V2 hardware with a single dependency chain:
3 cycles, the same as the vector forms and as FMUL, matching the SOG
row.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
    llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 9ad17b9c91e0a..eb9f8f8c04bff 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -1042,7 +1042,7 @@ def : InstRW<[V1Write_4c_1V], (instregex "^FCADD(v[48]f16|v[24]f32|v2f64)$")>;
 def : InstRW<[V1Wr_FCMA, V1Rd_FCMA], (instregex "^FCMLAv")>;
 
 // ASIMD FP multiply
-def : InstRW<[V1Wr_FPM], (instregex "^FMULX?v")>;
+def : InstRW<[V1Wr_FPM], (instregex "^FMULX?v", "^FMULX(16|32|64)$")>;
 
 // ASIMD FP multiply accumulate
 def : InstRW<[V1Wr_FPMA, V1Rd_FPMA], (instregex "^FML[AS]v")>;

diff  --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 22e672bd11d04..1e16cfbef8bd0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -1646,7 +1646,7 @@ def : InstRW<[V2Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
 def : InstRW<[V2Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
 
 // ASIMD FP multiply
-def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>;
+def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv", "^FMULX(16|32|64)$")>;
 
 // ASIMD FP multiply accumulate
 def : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>;

diff  --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
index 11712dec26341..2f9ed8660f5b9 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
@@ -378,10 +378,10 @@
 # CHECK-NEXT:  1      3     0.25                        fmul	s0, s1, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmul	v0.2s, v0.2s, v0.2s
 # CHECK-NEXT:  1      3     0.25                        fmulx	d0, d4, v0.d[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	d23, d11, d1
-# CHECK-NEXT:  1      2     0.25                        fmulx	s20, s22, s15
+# CHECK-NEXT:  1      3     0.25                        fmulx	d23, d11, d1
+# CHECK-NEXT:  1      3     0.25                        fmulx	s20, s22, s15
 # CHECK-NEXT:  1      3     0.25                        fmulx	h18, h17, v7.h[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	h20, h25, h0
+# CHECK-NEXT:  1      3     0.25                        fmulx	h20, h25, h0
 # CHECK-NEXT:  1      3     0.25                        fmulx	s3, s5, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmulx	v0.2d, v0.2d, v0.2d
 # CHECK-NEXT:  1      3     0.25                        fmulx	v28.4h, v25.4h, v15.h[1]

diff  --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
index 2076ac1ba7581..82f2714d58186 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
@@ -378,10 +378,10 @@
 # CHECK-NEXT:  1      3     0.25                        fmul	s0, s1, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmul	v0.2s, v0.2s, v0.2s
 # CHECK-NEXT:  1      3     0.25                        fmulx	d0, d4, v0.d[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	d23, d11, d1
-# CHECK-NEXT:  1      2     0.25                        fmulx	s20, s22, s15
+# CHECK-NEXT:  1      3     0.25                        fmulx	d23, d11, d1
+# CHECK-NEXT:  1      3     0.25                        fmulx	s20, s22, s15
 # CHECK-NEXT:  1      3     0.25                        fmulx	h18, h17, v7.h[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	h20, h25, h0
+# CHECK-NEXT:  1      3     0.25                        fmulx	h20, h25, h0
 # CHECK-NEXT:  1      3     0.25                        fmulx	s3, s5, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmulx	v0.2d, v0.2d, v0.2d
 # CHECK-NEXT:  1      3     0.25                        fmulx	v28.4h, v25.4h, v15.h[1]