[llvm] [AMDGPU] Fix misspelled FileCheck prefixes and suffixes in tests (NFC) (PR #228001)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 03:03:51 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/228001
>From a76b74b8af9e742452b726c51e001cdfbc240809 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 11:05:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Fix misspelled FileCheck prefixes and suffixes
in tests (NFC)
FileCheck ignores these directives, so the checks never ran
---
.../test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll | 2 +-
.../AMDGPU/irreducible/branch-outside.ll | 4 ++--
.../AMDGPU/irreducible/exit-divergence.ll | 2 +-
.../AMDGPU/irreducible/reducible-headers.ll | 4 ++--
.../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll | 6 +++---
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 2 +-
llvm/test/CodeGen/AMDGPU/default-fp-mode.ll | 2 +-
llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir | 2 +-
llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll | 2 +-
llvm/test/CodeGen/AMDGPU/internalize.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll | 6 +++---
llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll | 4 ++--
llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll | 2 +-
llvm/test/CodeGen/AMDGPU/shift-select.ll | 6 +++---
.../test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll | 8 ++++----
.../AMDGPU/triv-disjoint-mem-access-neg-offset.mir | 2 +-
llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll | 2 +-
18 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
index 3b26ec5de67df..c0969d744f49a 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
@@ -340,7 +340,7 @@ bb:
ret void
}
-; CHRCK: DIVERGENT: %tmp0 = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.f16.v8f32.v16f16.v32f16.i16(i1 false, <16 x half> %A, i1 false, <32 x half> %B, <8 x float> %C, i16 %Index, i1 false, i1 false)
+; CHECK: DIVERGENT: %tmp0 = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.f16.v8f32.v16f16.v32f16.i16(i1 false, <16 x half> %A, i1 false, <32 x half> %B, <8 x float> %C, i16 %Index, i1 false, i1 false)
define amdgpu_ps void @swmmac_f32_16x16x64_f16(<16 x half> %A, <32 x half> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
%tmp0 = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.f16.v8f32.v16f16.v32f16.i16(i1 0, <16 x half> %A, i1 0, <32 x half> %B, <8 x float> %C, i16 %Index, i1 false, i1 false)
store <8 x float> %tmp0, ptr addrspace(1) %out
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
index 4221bc9ad5583..fc8ccfb080a91 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
@@ -1,6 +1,6 @@
; RUN: opt %s -mtriple amdgpu7.00-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s
-; CHECK=LABEL: UniformityInfo for function 'basic':
+; CHECK-LABEL: UniformityInfo for function 'basic':
; CHECK: CYCLES ASSUMED DIVERGENT:
; CHECK: depth=1: entries(P T) Q
define amdgpu_kernel void @basic(i32 %a, i32 %b, i32 %c) {
@@ -37,7 +37,7 @@ exit:
ret void
}
-; CHECK=LABEL: UniformityInfo for function 'nested':
+; CHECK-LABEL: UniformityInfo for function 'nested':
; CHECK: CYCLES ASSUMED DIVERGENT:
; CHECK: depth=1: entries(P T) Q A B C
define amdgpu_kernel void @nested(i32 %a, i32 %b, i32 %c) {
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
index fe4c7e1ebebc8..7b98ccb03af4c 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
@@ -1,6 +1,6 @@
; RUN: opt %s -mtriple amdgpu7.00-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s
-; CHECK=LABEL: UniformityInfo for function 'basic':
+; CHECK-LABEL: UniformityInfo for function 'basic':
; CHECK-NOT: CYCLES ASSUMED DIVERGENT:
; CHECK: CYCLES WITH DIVERGENT EXIT:
; CHECK: depth=1: entries(P T) Q
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
index f3d585ae2a879..7adbbfcb7c9f9 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
@@ -31,7 +31,7 @@
; at P should not be marked divergent.
define amdgpu_kernel void @nested_irreducible(i32 %a, i32 %b, i32 %c) {
-; CHECK=LABEL: UniformityInfo for function 'nested_irreducible':
+; CHECK-LABEL: UniformityInfo for function 'nested_irreducible':
; CHECK-NOT: CYCLES ASSUMED DIVERGENT:
; CHECK: CYCLES WITH DIVERGENT EXIT:
; CHECK-DAG: depth=2: entries(P T) Q R
@@ -118,7 +118,7 @@ exit:
; Thus, any PHI at P should not be marked divergent.
define amdgpu_kernel void @header_label_1(i32 %a, i32 %b, i32 %c) {
-; CHECK=LABEL: UniformityInfo for function 'header_label_1':
+; CHECK-LABEL: UniformityInfo for function 'header_label_1':
; CHECK-NOT: CYCLES ASSUMED DIVERGENT:
; CHECK: CYCLES WITH DIVERGENT EXIT:
; CHECK: depth=1: entries(H) P Q T U R
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
index 160a5990747e9..2f132f657146d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
@@ -28,7 +28,7 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
@@ -55,7 +55,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
@@ -90,7 +90,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
index 2a70f3e8f60d3..8b35a1dee2552 100644
--- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
+++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
@@ -630,7 +630,7 @@ done:
; OPT-LABEL: @test_sink_global_small_min_scratch_global_offset(
; OPT-SICIVI: %in.gep = getelementptr i8, ptr addrspace(1) %in, i64 -4096
-; OPT-SICIV: br
+; OPT-SICIVI: br
; OPT-SICIVI: %tmp1 = load i8, ptr addrspace(1) %in.gep
; OPT-GFX9: br
diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
index 505eb46284890..d210a43d54a0a 100644
--- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
@@ -20,7 +20,7 @@ define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrsp
}
; GCN-LABEL: {{^}}test_f32_denormals:
-; GCNL: FloatMode: 48
+; GCN: FloatMode: 240
; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #1 {
store float 0.0, ptr addrspace(1) %out0
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
index 0d42d342fcfda..673d0f7708373 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
@@ -7,7 +7,7 @@
---
# V_MOV_B16_t16_e64_dpp is unsupported to combine
-# GCN-label: name: vop3_u16
+# GCN-LABEL: name: vop3_u16
# GCN: %4:vgpr_16 = V_MOV_B16_t16_e64_dpp %3, 0, %1, 0, 1, 15, 15, 1, implicit $exec
# GCN: %6:vgpr_16 = V_MOV_B16_t16_e64_dpp %3, 0, %5, 0, 1, 15, 15, 1, implicit $exec
name: vop3_u16
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
index ed766385e9430..df80d7e20a268 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
@@ -179,7 +179,7 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0
; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1_fast:
-; VI-NANN: v_max_f32_e64 v0, -v0, 1.0
+; VI: v_max_f32_e64 v0, -v0, 1.0
define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1_fast(float %a, float %b) #0 {
%fneg.a = fneg float %a
%cmp.a = fcmp olt float %a, -1.0
diff --git a/llvm/test/CodeGen/AMDGPU/internalize.ll b/llvm/test/CodeGen/AMDGPU/internalize.ll
index 4e1f697743630..a411c9f7359bd 100644
--- a/llvm/test/CodeGen/AMDGPU/internalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/internalize.ll
@@ -11,7 +11,7 @@
@gvar_used = addrspace(1) global i32 poison, align 4
; OPT: define internal fastcc void @func_used_noinline(
-; OPT-NONE: define fastcc void @func_used_noinline(
+; OPTNONE: define fastcc void @func_used_noinline(
define fastcc void @func_used_noinline(ptr addrspace(1) %out, i32 %tid) #1 {
entry:
store volatile i32 %tid, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
index a333b11a69ca2..106c637343b55 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
@@ -30,7 +30,7 @@ entry:
; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp
; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
; GFX10: v_dot4c_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
-; GF11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} neg_lo:[1,1,0]{{$}}
+; GFX11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,1,0]{{$}}
define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp(
ptr addrspace(1) %r,
ptr addrspace(1) %a,
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
index daa3fb58fc563..d3e5798e346a7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
@@ -28,7 +28,7 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
@@ -55,7 +55,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
@@ -90,7 +90,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; UNKNOWN-OS: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
diff --git a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
index 17f85f02e7333..13e71642218b3 100644
--- a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
@@ -253,7 +253,7 @@ define amdgpu_ps <2 x i32> @lshl_add_u64_sss_and_4(i32 inreg %v, i32 inreg %a, i
define amdgpu_ps <2 x i32> @lshl_add_u64_svs_and_4(i32 inreg %v, i64 %a, i32 inreg %s) {
; GCN-LABEL: lshl_add_u64_svs_and_4
; GFX-1250: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}, s{{[0-9:]+}}, v[{{[0-9:]+}}]
-; GFX-942: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]
+; GFX942: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]
; GISEL-LABEL: lshl_add_u64_svs_and_4
; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}}
; GFX-1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
@@ -271,7 +271,7 @@ define amdgpu_ps <2 x i32> @lshl_add_u64_vvs_and_4(i64 %v, i64 %a, i32 inreg %s)
; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
; GISEL-LABEL: lshl_add_u64_vvs_and_4
; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}}
-; GFX-1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
+; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
%and = and i32 %s, 4
%zext_and = zext i32 %and to i64
%shl = shl i64 %v, %zext_and
diff --git a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
index 93f1c901acc2d..cde56914a90d7 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
+++ b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
@@ -8,7 +8,7 @@
; to follow a base one.
; GCN-LABEL: {{^}}out_of_order_merge:
-; GCN-COUNT2: ds_read2_b64
+; GCN-COUNT-2: ds_read2_b64
; GCN-COUNT3: ds_write_b64
define amdgpu_kernel void @out_of_order_merge() {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/shift-select.ll b/llvm/test/CodeGen/AMDGPU/shift-select.ll
index 69786d0a16786..d72e2b5a6f8b7 100644
--- a/llvm/test/CodeGen/AMDGPU/shift-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/shift-select.ll
@@ -76,7 +76,7 @@ define amdgpu_kernel void @s_shl_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs)
; GCN-LABEL: name: v_shl_i64
; GFX6: V_LSHL_B64
-; GFX8: V_LSHLREV_B64
+; GFX8PLUS: V_LSHLREV_B64
define amdgpu_kernel void @v_shl_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%idx = zext i32 %tid to i64
@@ -98,7 +98,7 @@ define amdgpu_kernel void @s_lshr_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs)
; GCN-LABEL: name: v_lshr_i64
; GFX6: V_LSHR_B64
-; GFX8: V_LSHRREV_B64
+; GFX8PLUS: V_LSHRREV_B64
define amdgpu_kernel void @v_lshr_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%idx = zext i32 %tid to i64
@@ -120,7 +120,7 @@ define amdgpu_kernel void @s_ashr_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs)
; GCN-LABEL: name: v_ashr_i64
; GFX6: V_ASHR_I64
-; GFX8: V_ASHRREV_I64
+; GFX8PLUS: V_ASHRREV_I64
define amdgpu_kernel void @v_ashr_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%idx = zext i32 %tid to i64
diff --git a/llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll b/llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
index d2e2092906a31..112347b163faf 100644
--- a/llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
@@ -4,8 +4,8 @@
; GCN-LABEL: {{^}}token_factor_inline_limit_test:
-; GCN-TFLID: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
-; GCN-TFLID: buffer_store_dword [[REG7]], {{.*$}}
+; GCN-TFILD: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
+; GCN-TFILD: buffer_store_dword [[REG7]], {{.*$}}
; GCN-TFILD: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
; GCN-TFILD: buffer_store_dword [[REG8]], {{.*}} offset:4
; GCN-TFILD: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
@@ -39,8 +39,8 @@
; GCN-TFIL7: buffer_store_dword [[REG9]], {{.*}} offset:8
; GCN-TFIL7: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
; GCN-TFIL7: buffer_store_dword [[REG8]], {{.*}} offset:4
-; GCN-TFLL7: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
-; GCN-TFLL7: buffer_store_dword [[REG7]], {{.*$}}
+; GCN-TFIL7: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
+; GCN-TFIL7: buffer_store_dword [[REG7]], {{.*$}}
; GCN: s_getpc
define void @token_factor_inline_limit_test() {
diff --git a/llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir b/llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
index 9cbaded288577..03bb765e20829 100644
--- a/llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
+++ b/llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
@@ -4,7 +4,7 @@
# Make sure handling of unsigned immediate values interpreted as negative values
# still works for SIInstrInfo::areMemAccessesTriviallyDisjoint.
-# LABEL: {{^}}no_reorder_flat_load_local_store_local_load:
+# CHECK-LABEL: {{^}}no_reorder_flat_load_local_store_local_load:
# CHECK: SU(5): %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# CHECK: SU(6): DS_WRITE_B128_gfx9 %5:vgpr_32, %4:vreg_128, 512, 0, implicit $exec
# CHECK: SU(7): %6:vreg_64 = DS_READ2_B32_gfx9 %5:vgpr_32, -127, -126, 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
index 1f802306d386b..15f702dbf4a48 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
@@ -258,7 +258,7 @@ bb13: ; preds = %.preheader
; OPT: store i32 %0, ptr addrspace(1) %out, align 4
; GCN-LABEL: {{^}}vector_read_alloca_bitcast_assume:
-; GCN-COUNT: buffer_store_dword
+; GCN-ALLOCA-COUNT-4: buffer_store_dword
define amdgpu_kernel void @vector_read_alloca_bitcast_assume(ptr addrspace(1) %out, i32 %index) {
entry:
>From 92278b61841c7493990bbf51a15cec3c4aaa11b5 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 12:03:26 +0200
Subject: [PATCH 2/2] address comments
---
llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll | 4 ++--
llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
index 13e71642218b3..1de1a414971b0 100644
--- a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
@@ -252,11 +252,11 @@ define amdgpu_ps <2 x i32> @lshl_add_u64_sss_and_4(i32 inreg %v, i32 inreg %a, i
define amdgpu_ps <2 x i32> @lshl_add_u64_svs_and_4(i32 inreg %v, i64 %a, i32 inreg %s) {
; GCN-LABEL: lshl_add_u64_svs_and_4
-; GFX-1250: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}, s{{[0-9:]+}}, v[{{[0-9:]+}}]
+; GFX1250: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
; GFX942: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]
; GISEL-LABEL: lshl_add_u64_svs_and_4
; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}}
-; GFX-1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}]
+; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v[{{[0-9:]+}}]
%and = and i32 %s, 4
%zext_and = zext i32 %and to i64
%zext_v = zext i32 %and to i64
diff --git a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
index cde56914a90d7..42c652188221f 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
+++ b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
@@ -9,7 +9,8 @@
; GCN-LABEL: {{^}}out_of_order_merge:
; GCN-COUNT-2: ds_read2_b64
-; GCN-COUNT3: ds_write_b64
+; GCN: ds_write_b128
+; GCN: ds_write_b64
define amdgpu_kernel void @out_of_order_merge() {
entry:
%gep2 = getelementptr inbounds [96 x double], ptr addrspace(3) @Ldisp, i32 0, i32 1
More information about the llvm-commits
mailing list