[llvm] c7e8403 - Revert "[AArch64] Add CSEL for canCreateUndefOrPoisonForTargetNode (#226946)" (#227992)

[via llvm-commits]

Author: David Green
Date: 2026-10-01T09:14:55Z
New Revision: c7e84033591028fe0e205157955e3e6c5c8f228e

URL: https://github.com/llvm/llvm-project/commit/c7e84033591028fe0e205157955e3e6c5c8f228e
DIFF: https://github.com/llvm/llvm-project/commit/c7e84033591028fe0e205157955e3e6c5c8f228e.diff

LOG: Revert "[AArch64] Add CSEL for canCreateUndefOrPoisonForTargetNode (#226946)" (#227992)

This reverts commit 1e8550c234507ef5b70d508f18b98f9bb0ebc07b due to
buildbot / bootstrap failures not seen in other testing.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 40930af9856ab..9885dfc854d11 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -36219,10 +36219,6 @@ bool AArch64TargetLowering::canCreateUndefOrPoisonForTargetNode(
   case AArch64ISD::VASHR:
   case AArch64ISD::VLSHR:
   case AArch64ISD::VSHL:
-  case AArch64ISD::CSEL:
-  case AArch64ISD::CSNEG:
-  case AArch64ISD::CSINC:
-  case AArch64ISD::CSINV:
     return false;
   }
   return TargetLowering::canCreateUndefOrPoisonForTargetNode(

diff  --git a/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll b/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
index 290a3e3b63b44..26eda6c60a1b1 100644
--- a/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
@@ -268,7 +268,8 @@ define i64 @test_or_select_fast (float %a, float %b) {
 ; CHECK-SD-NEXT:    fcmp s0, #0.0
 ; CHECK-SD-NEXT:    cset w8, ne
 ; CHECK-SD-NEXT:    fcmp s1, #0.0
-; CHECK-SD-NEXT:    csinc w8, w8, wzr, eq
+; CHECK-SD-NEXT:    cset w9, ne
+; CHECK-SD-NEXT:    orr w8, w8, w9
 ; CHECK-SD-NEXT:    tbz w8, #0, .LBB5_2
 ; CHECK-SD-NEXT:  // %bb.1:
 ; CHECK-SD-NEXT:    mov x0, xzr
@@ -370,7 +371,8 @@ define i64 @test_and_select_fast(float %a, float %b) {
 ; CHECK-SD-NEXT:    fcmp s0, #0.0
 ; CHECK-SD-NEXT:    cset w8, eq
 ; CHECK-SD-NEXT:    fcmp s1, #0.0
-; CHECK-SD-NEXT:    csel w8, wzr, w8, ne
+; CHECK-SD-NEXT:    cset w9, eq
+; CHECK-SD-NEXT:    and w8, w8, w9
 ; CHECK-SD-NEXT:    tbz w8, #0, .LBB7_2
 ; CHECK-SD-NEXT:  // %bb.1: // %bb4
 ; CHECK-SD-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill