[llvm] [AMDGPU] Add missing colons to FileCheck directives in tests (NFC) (PR #227999)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 02:03:22 PDT 2026
https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/227999
None
>From 34960889058f2bd4491257c941ad6112e5216c9b Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 11:02:02 +0200
Subject: [PATCH] [AMDGPU] Add missing colons to FileCheck directives in tests
(NFC)
---
llvm/test/Analysis/CostModel/AMDGPU/fsub.ll | 2 +-
.../UniformityAnalysis/AMDGPU/phi_div_loop.ll | 2 +-
.../CodeGen/AMDGPU/hsa-metadata-agpr-small.ll | 16 ++++++++--------
llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll | 4 ++--
llvm/test/CodeGen/AMDGPU/set-wave-priority.ll | 2 +-
llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s | 4 ++--
7 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll b/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
index 8a6462165e52665..1bba906cab228cd 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
@@ -6,7 +6,7 @@
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.0a-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FASTF16-SIZE,GFX90A-FASTF64-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,FASTF16-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu6.01-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,SLOWF64-SIZE %s
-; RUN opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu12.50-unknown-amdhsa < %s | FileCheck -check-prefixes=GFX1250-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu12.50-unknown-amdhsa < %s | FileCheck -check-prefixes=GFX1250-SIZE %s
; END.
define amdgpu_kernel void @fsub_f32() #0 {
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll
index ae3e360397b22ea..c5ac6f5881df3d1 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll
@@ -24,7 +24,7 @@
; CHECK: %uni_a = phi i32 [ %a1, %B2 ], [ %a, %Entry ]
; CHECK-LABEL: BLOCK B5
; CHECK: %uni.a3 = phi i32 [ %a2, %B4 ], [ %uni_a3, %B5 ]
-; CHECK-LABEL BLOCK B6
+; CHECK-LABEL: BLOCK B6
; CHECK: DIVERGENT: %div_a = phi i32 [ %uni_a, %B3 ], [ %uni_a3, %B5 ]
;
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
index 231adad3e73c725..0321f4e0af4e83c 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
@@ -5,23 +5,23 @@
; COM: Comments for each kernel
; CHECK: kernel_32_agprs
; GFX908: ; NumVgprs: 9
-; GFX908 ; NumAgprs: 32
-; GFX908 ; TotalNumVgprs: 32
+; GFX908: ; NumAgprs: 32
+; GFX908: ; TotalNumVgprs: 32
; GFX90A: ; NumVgprs: 9
-; GFX90A ; NumAgprs: 32
-; GFX90A ; TotalNumVgprs: 44
+; GFX90A: ; NumAgprs: 32
+; GFX90A: ; TotalNumVgprs: 44
; GFX801: ; NumVgprs: 9
; CHECK: kernel_40_vgprs
; GFX908: ; NumVgprs: 40
-; GFX908 ; NumAgprs: 16
-; GFX908 ; TotalNumVgprs: 40
+; GFX908: ; NumAgprs: 16
+; GFX908: ; TotalNumVgprs: 40
; GFX90A: ; NumVgprs: 40
-; GFX90A ; NumAgprs: 16
-; GFX90A ; TotalNumVgprs: 56
+; GFX90A: ; NumAgprs: 16
+; GFX90A: ; TotalNumVgprs: 56
; GFX801: ; NumVgprs: 40
diff --git a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
index 17f85f02e73334c..755bb54580a202e 100644
--- a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
@@ -225,7 +225,7 @@ define <4 x i64> @lshl_add_u64_vvv_and_2_v4(<4 x i64> %v, <4 x i64> %a, <4 x i64
; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND2:v[0-9:]+]], 2, v{{[0-9:]+}}
; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND1:v[0-9:]+]], 3, v{{[0-9:]+}}
; GFX1250-GISEL-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND1]], v[{{[0-9:]+}}]
-; GFX1250-GISEL-DAG v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND2]], v[{{[0-9:]+}}]
+; GFX1250-GISEL-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND2]], v[{{[0-9:]+}}]
; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
%and = and <4 x i64> %s, <i64 1, i64 2, i64 3, i64 5>
%shl = shl <4 x i64> %v, %and
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
index 262f1d11fdf8bb0..dbe4743d7759a5a 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
@@ -139,13 +139,13 @@ define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr:
; SICIVI: {{buffer|flat}}_load_dword [[VADDR:v[0-9]+]],
; SICIVI: v_lshlrev_b32_e32 [[ADDR:v[0-9]+]], 2, [[VADDR]]
-; SICIVI-NOT [[ADDR]]
+; SICIVI-NOT: [[ADDR]]
; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR]]
; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
; GFX9: global_load_dword [[VADDR:v[0-9]+]],
; GFX9: v_lshl_add_u32 [[ADDR:v[0-9]+]], [[VADDR]], 2, s{{[0-9]+}}
-; GFX9-NOT [[ADDR]]
+; GFX9-NOT: [[ADDR]]
; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen offset:32
define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
index d1958e2957df3ad..bca4b8457b205d3 100644
--- a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
+++ b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
@@ -126,7 +126,7 @@ exit:
; CHECK: [[LOOP:.*]]: ; %loop
; CHECK-NOT: s_setprio
; CHECK: s_cbranch_scc1 [[LOOP]]
-; CHECK {{.*}}: ; %exit
+; CHECK: {{.*}}: ; %exit
; CHECK-NOT: s_setprio
; CHECK: s_branch [[RET:.*]]
; CHECK: [[ANOTHER_LOAD]]: ; %another_load
diff --git a/llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s b/llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
index dcb34714f7096f1..fc8f7530c41b7fc 100644
--- a/llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
+++ b/llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
@@ -1012,10 +1012,10 @@ s_fmamk_f32 s5, s1, 0x11213141, s105
// GFX1150: encoding: [0x01,0x69,0x05,0xa3,0x41,0x31,0x21,0x11]
s_fmamk_f32 s5, 0x11213141, 0x11213141, s105
-// GFX1150 encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11]
+// GFX1150: encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11]
s_fmamk_f32 s5, s105, 0x11213141, 0x11213141
-// GFX1150 encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11]
+// GFX1150: encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11]
s_fmaak_f32 s5, s1, s2, 0x11213141
// GFX1150: encoding: [0x01,0x02,0x85,0xa2,0x41,0x31,0x21,0x11]
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