[llvm] Revert "[AArch64] Add CSEL for canCreateUndefOrPoisonForTargetNode (#226946)" (PR #227992)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/227992

This reverts commit 1e8550c234507ef5b70d508f18b98f9bb0ebc07b due to
buildbot / bootstrap failures not seen in other testing.

>From 3f1ba6f4d42fb7211b67e844cdd4ffa5eaddc5a1 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 1 Oct 2026 09:24:47 +0100
Subject: [PATCH] Revert "[AArch64] Add CSEL for
 canCreateUndefOrPoisonForTargetNode (#226946)"

This reverts commit 1e8550c234507ef5b70d508f18b98f9bb0ebc07b due to
buildbot / bootstrap failures not seen in other testing.
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp     | 4 ----
 llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll | 6 ++++--
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 40930af9856ab..9885dfc854d11 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -36219,10 +36219,6 @@ bool AArch64TargetLowering::canCreateUndefOrPoisonForTargetNode(
   case AArch64ISD::VASHR:
   case AArch64ISD::VLSHR:
   case AArch64ISD::VSHL:
-  case AArch64ISD::CSEL:
-  case AArch64ISD::CSNEG:
-  case AArch64ISD::CSINC:
-  case AArch64ISD::CSINV:
     return false;
   }
   return TargetLowering::canCreateUndefOrPoisonForTargetNode(
diff --git a/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll b/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
index 290a3e3b63b44..26eda6c60a1b1 100644
--- a/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
@@ -268,7 +268,8 @@ define i64 @test_or_select_fast (float %a, float %b) {
 ; CHECK-SD-NEXT:    fcmp s0, #0.0
 ; CHECK-SD-NEXT:    cset w8, ne
 ; CHECK-SD-NEXT:    fcmp s1, #0.0
-; CHECK-SD-NEXT:    csinc w8, w8, wzr, eq
+; CHECK-SD-NEXT:    cset w9, ne
+; CHECK-SD-NEXT:    orr w8, w8, w9
 ; CHECK-SD-NEXT:    tbz w8, #0, .LBB5_2
 ; CHECK-SD-NEXT:  // %bb.1:
 ; CHECK-SD-NEXT:    mov x0, xzr
@@ -370,7 +371,8 @@ define i64 @test_and_select_fast(float %a, float %b) {
 ; CHECK-SD-NEXT:    fcmp s0, #0.0
 ; CHECK-SD-NEXT:    cset w8, eq
 ; CHECK-SD-NEXT:    fcmp s1, #0.0
-; CHECK-SD-NEXT:    csel w8, wzr, w8, ne
+; CHECK-SD-NEXT:    cset w9, eq
+; CHECK-SD-NEXT:    and w8, w8, w9
 ; CHECK-SD-NEXT:    tbz w8, #0, .LBB7_2
 ; CHECK-SD-NEXT:  // %bb.1: // %bb4
 ; CHECK-SD-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill