[llvm] [RISCV] Fixed redundant add instructions generated during the fold of vscale add in rvv. (PR #225266)

[Kamlesh Kumar via llvm-commits]

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@@ -4771,6 +4771,14 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
     return true;
   }
 
+  /// fold (A + vscale(C1)) + vscale(C2) -> A + vscale(C1+C2)
+  /// If (A + vscale(C1)) is used multiple times, the fold results in a
+  /// redundant addition instruction on the RISC-V architecture, whereas it
+  /// does not have this effect on other architectures (e.g. AArch64).
+  /// By default, it returns true. In RISC-V architecture, returns
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kamleshbhalui wrote:

Last sentence can be removed.

https://github.com/llvm/llvm-project/pull/225266