[llvm] [RISCV] Eliminate redundant materializations after register comparison (PR #227673)
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Wed Sep 30 23:12:04 PDT 2026
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You can test this locally with the following command:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp --diff_from_common_commit
``````````
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index 327c2104b..ccf9fc2b0 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -122,13 +122,11 @@ getRegImmediateBeforeTerminator(MachineBasicBlock &MBB, Register Reg,
continue;
// The last modification must define Reg itself to a known immediate.
if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(0).isReg() &&
- MI.getOperand(0).getReg() == Reg &&
- MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0 &&
- MI.getOperand(2).isImm())
+ MI.getOperand(0).getReg() == Reg && MI.getOperand(1).isReg() &&
+ MI.getOperand(1).getReg() == RISCV::X0 && MI.getOperand(2).isImm())
return MI.getOperand(2).getImm();
if (MI.getOpcode() == RISCV::QC_LI && MI.getOperand(0).isReg() &&
- MI.getOperand(0).getReg() == Reg &&
- MI.getOperand(1).isImm())
+ MI.getOperand(0).getReg() == Reg && MI.getOperand(1).isImm())
return MI.getOperand(1).getImm();
return std::nullopt;
}
@@ -158,8 +156,7 @@ bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
return false;
bool IsZeroCopy = guaranteesZeroRegInBlock(MBB, Cond, TBB);
- bool IsImmCopy =
- !IsZeroCopy && guaranteesRegEqualsImmInBlock(MBB, Cond, TBB);
+ bool IsImmCopy = !IsZeroCopy && guaranteesRegEqualsImmInBlock(MBB, Cond, TBB);
int64_t CompareImm = IsImmCopy ? Cond[2].getImm() : 0;
if (!IsZeroCopy && !IsImmCopy && Cond.size() == 3 &&
(Cond[0].getImm() == RISCV::BEQ || Cond[0].getImm() == RISCV::BNE) &&
``````````
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https://github.com/llvm/llvm-project/pull/227673
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