[llvm] [ARM][FastISel] Fix soft-float f64 register pair order on big endian (PR #227172)

[dong jianqiang via llvm-commits]

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@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armebv7-linux-gnueabi -mattr=+vfp3 | FileCheck %s
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dongjianqiang2 wrote:

Thanks — added -fast-isel=0/1 runs; the two ISel paths now emit identical code (modulo the frame pointer setup FastISel inserts at -O0), and dropped -fast-isel-abort=1. 

https://github.com/llvm/llvm-project/pull/227172