[llvm] 640e1c6 - [RISCV][P-ext] Remove riscv_pmulh(u)intrinsics. (#227846)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 20:13:01 PDT 2026
Author: Craig Topper
Date: 2026-10-01T03:12:51Z
New Revision: 640e1c693814b0607ccde86745c963b2cf89fcb8
URL: https://github.com/llvm/llvm-project/commit/640e1c693814b0607ccde86745c963b2cf89fcb8
DIFF: https://github.com/llvm/llvm-project/commit/640e1c693814b0607ccde86745c963b2cf89fcb8.diff
LOG: [RISCV][P-ext] Remove riscv_pmulh(u)intrinsics. (#227846)
These are redundant with the llvm.smulh/umulh intrinsics that were added
recently.
Strangely we don't have clang IRgen tests for these intrinsics/builtins,
but we do have a cross-project test for assembly.
Added:
Modified:
clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvp-simd-32.ll
llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 20ec751018685..474a0aa577734 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1479,7 +1479,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pmulh_i16x2:
case RISCV::BI__builtin_riscv_pmulh_i16x4:
case RISCV::BI__builtin_riscv_pmulh_i32x2:
- ID = Intrinsic::riscv_pmulh;
+ ID = Intrinsic::smulh;
break;
case RISCV::BI__builtin_riscv_pmulhr_i16x2:
case RISCV::BI__builtin_riscv_pmulhr_i16x4:
@@ -1489,7 +1489,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pmulhu_u16x2:
case RISCV::BI__builtin_riscv_pmulhu_u16x4:
case RISCV::BI__builtin_riscv_pmulhu_u32x2:
- ID = Intrinsic::riscv_pmulhu;
+ ID = Intrinsic::umulh;
break;
case RISCV::BI__builtin_riscv_pmulhru_u16x2:
case RISCV::BI__builtin_riscv_pmulhru_u16x4:
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 8cac40c2dc535..b2e9bbba3ad6f 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2132,9 +2132,7 @@ class RVPBinaryIntrinsic
def int_riscv_pzext_h : RVPExtIntrinsic;
// Packed Multiply High.
- def int_riscv_pmulh : RVPBinaryIntrinsic;
def int_riscv_pmulhr : RVPBinaryIntrinsic;
- def int_riscv_pmulhu : RVPBinaryIntrinsic;
def int_riscv_pmulhru : RVPBinaryIntrinsic;
def int_riscv_pmulhsu : RVPBinaryIntrinsic;
def int_riscv_pmulhrsu : RVPBinaryIntrinsic;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bd994fc36a704..7730a52a2e26d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12304,12 +12304,8 @@ static unsigned getRVPMulHighOpcode(unsigned IntNo) {
switch (IntNo) {
default:
llvm_unreachable("Unexpected RISC-V packed multiply high intrinsic");
- case Intrinsic::riscv_pmulh:
- return ISD::MULHS;
case Intrinsic::riscv_pmulhr:
return RISCVISD::MULHR;
- case Intrinsic::riscv_pmulhu:
- return ISD::MULHU;
case Intrinsic::riscv_pmulhru:
return RISCVISD::MULHRU;
case Intrinsic::riscv_pmulhsu:
@@ -13243,9 +13239,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, AbdsumauId, Lo,
Rs1Hi, Rs2Hi);
}
- case Intrinsic::riscv_pmulh:
case Intrinsic::riscv_pmulhr:
- case Intrinsic::riscv_pmulhu:
case Intrinsic::riscv_pmulhru:
case Intrinsic::riscv_pmulhsu:
case Intrinsic::riscv_pmulhrsu: {
@@ -17815,9 +17809,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case Intrinsic::riscv_pmerge:
case Intrinsic::riscv_pmulq:
case Intrinsic::riscv_pmulqr:
- case Intrinsic::riscv_pmulh:
case Intrinsic::riscv_pmulhr:
- case Intrinsic::riscv_pmulhu:
case Intrinsic::riscv_pmulhru:
case Intrinsic::riscv_pmulhsu:
case Intrinsic::riscv_pmulhrsu:
@@ -17857,9 +17849,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case Intrinsic::riscv_pmulqr:
Opc = RISCVISD::MULQR;
break;
- case Intrinsic::riscv_pmulh:
case Intrinsic::riscv_pmulhr:
- case Intrinsic::riscv_pmulhu:
case Intrinsic::riscv_pmulhru:
case Intrinsic::riscv_pmulhsu:
case Intrinsic::riscv_pmulhrsu:
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 2149266271707..e947cebb90a91 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -3142,7 +3142,7 @@ define <2 x i16> @test_pmulh_v2i16(<2 x i16> %rs1, <2 x i16> %rs2) {
; CHECK: # %bb.0:
; CHECK-NEXT: pmulh.h a0, a0, a1
; CHECK-NEXT: ret
- %res = call <2 x i16> @llvm.riscv.pmulh.v2i16(<2 x i16> %rs1, <2 x i16> %rs2)
+ %res = call <2 x i16> @llvm.smulh.v2i16(<2 x i16> %rs1, <2 x i16> %rs2)
ret <2 x i16> %res
}
@@ -3160,7 +3160,7 @@ define <2 x i16> @test_pmulhu_v2i16(<2 x i16> %rs1, <2 x i16> %rs2) {
; CHECK: # %bb.0:
; CHECK-NEXT: pmulhu.h a0, a0, a1
; CHECK-NEXT: ret
- %res = call <2 x i16> @llvm.riscv.pmulhu.v2i16(<2 x i16> %rs1, <2 x i16> %rs2)
+ %res = call <2 x i16> @llvm.umulh.v2i16(<2 x i16> %rs1, <2 x i16> %rs2)
ret <2 x i16> %res
}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 63c22512edc6b..77376296bfbdf 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -6226,7 +6226,7 @@ define <4 x i16> @test_pmulh_v4i16(<4 x i16> %rs1, <4 x i16> %rs2) {
; RV64: # %bb.0:
; RV64-NEXT: pmulh.h a0, a0, a1
; RV64-NEXT: ret
- %res = call <4 x i16> @llvm.riscv.pmulh.v4i16(<4 x i16> %rs1, <4 x i16> %rs2)
+ %res = call <4 x i16> @llvm.smulh.v4i16(<4 x i16> %rs1, <4 x i16> %rs2)
ret <4 x i16> %res
}
@@ -6256,7 +6256,7 @@ define <4 x i16> @test_pmulhu_v4i16(<4 x i16> %rs1, <4 x i16> %rs2) {
; RV64: # %bb.0:
; RV64-NEXT: pmulhu.h a0, a0, a1
; RV64-NEXT: ret
- %res = call <4 x i16> @llvm.riscv.pmulhu.v4i16(<4 x i16> %rs1, <4 x i16> %rs2)
+ %res = call <4 x i16> @llvm.umulh.v4i16(<4 x i16> %rs1, <4 x i16> %rs2)
ret <4 x i16> %res
}
@@ -6316,7 +6316,7 @@ define <2 x i32> @test_pmulh_v2i32(<2 x i32> %rs1, <2 x i32> %rs2) {
; RV64: # %bb.0:
; RV64-NEXT: pmulh.w a0, a0, a1
; RV64-NEXT: ret
- %res = call <2 x i32> @llvm.riscv.pmulh.v2i32(<2 x i32> %rs1, <2 x i32> %rs2)
+ %res = call <2 x i32> @llvm.smulh.v2i32(<2 x i32> %rs1, <2 x i32> %rs2)
ret <2 x i32> %res
}
@@ -6346,7 +6346,7 @@ define <2 x i32> @test_pmulhu_v2i32(<2 x i32> %rs1, <2 x i32> %rs2) {
; RV64: # %bb.0:
; RV64-NEXT: pmulhu.w a0, a0, a1
; RV64-NEXT: ret
- %res = call <2 x i32> @llvm.riscv.pmulhu.v2i32(<2 x i32> %rs1, <2 x i32> %rs2)
+ %res = call <2 x i32> @llvm.umulh.v2i32(<2 x i32> %rs1, <2 x i32> %rs2)
ret <2 x i32> %res
}
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