[llvm] [AMDGPU] op_sel[0] must be zero for v_cvt_sr_fp8/bf8_f16 (PR #227413)

[Changpeng Fang via llvm-commits]

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@@ -896,6 +896,16 @@ class Cvt_SR_F8_ByteSel_Pat<SDPatternOperator node, VOP3_Pseudo inst, ValueType
     (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $old, (as_i32timm $byte_sel))
 >;
 
+// Copy a VGPR_16 source into the low half of a VGPR_32, because op_sel[0] must
+// be zero for v_cvt_sr_fp8/bf8_f16.
+class Cvt_SR_F8_F16_ByteSel_Lo16_Pat<SDPatternOperator node, VOP3_Pseudo inst> : GCNPat<
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changpeng wrote:

> Should instruction get an RC with only lo16 instead?

Do you mean we need to define a new register class like  VGPR_16_Lo (and SGPR_16_Lo)?
It looks much complicated to me.

https://github.com/llvm/llvm-project/pull/227413