[llvm] Loopunrollpass updates scev directly (PR #227913)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 17:03:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Ryunosuke (Rick) Yanashita (ryanashita)
<details>
<summary>Changes</summary>
This fixes an issue present in the ```LoopUnrollPass```, where the ScalarEvolution analysis (```SCEV```) produced by runtime unrolling leaves out no-wrap flag information, stripping the resulting IR of the ```nuw nsw``` flags.
Following the suggested fix, ```SCEVAddRecExpr``` is updated after creation --and after the unrolled loop is simplified and internally optimized with constprop and dce-- with the existing ScalarEvolution::setNoWrapFlags.
For the testcase from #<!-- -->220816, the IR after unrolling is now
```
$ opt -S -passes='loop-unroll' test.ll | grep '%add.4 = '
%add.4 = add nuw nsw i32 %i.06, 5
$ opt -S -passes='loop-unroll,loop(indvars)' test.ll | grep '%add.4 = '
%add.4 = add nuw nsw i32 %i.06, 5
$ opt -S -passes='loop-unroll,loop(loop-reduce)' test.ll | grep '%add.4 = '
%add.4 = add nuw nsw i32 %i.06, 5
$ opt -S -passes='loop-unroll,invalidate<scalar-evolution>,loop(indvars)' test.ll | grep '%add.4 = '
%add.4 = add nuw nsw i32 %i.06, 5
```
and the ordering dependence mentioned in #<!-- -->220816 is resolved.
I implemented tests for this fix in ```/llvm/test/Transforms/LoopUnroll/runtime-unroll-preserve-scev-nowrap.ll```
Assisted by llm browser chatbot for testing.
Fixes #<!-- -->220816.
---
Patch is 39.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/227913.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Utils/LoopUnroll.cpp (+31)
- (added) llvm/test/Transforms/LoopUnroll/runtime-unroll-preserve-scev-nowrap.ll (+539)
``````````diff
diff --git a/llvm/lib/Transforms/Utils/LoopUnroll.cpp b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
index 65bb586d922fe..1c4f841383560 100644
--- a/llvm/lib/Transforms/Utils/LoopUnroll.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
@@ -34,6 +34,8 @@
#include "llvm/Analysis/MemorySSA.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/Analysis/ScalarEvolution.h"
+#include "llvm/Analysis/ScalarEvolutionExpressions.h"
+#include "llvm/Analysis/ValueTracking.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CFG.h"
#include "llvm/IR/Constants.h"
@@ -414,6 +416,35 @@ void llvm::simplifyLoopAfterUnroll(Loop *L, bool SimplifyIVs, LoopInfo *LI,
Inst.setHasNoSignedWrap(Inst.hasNoSignedWrap() &&
InnerOBO->hasNoSignedWrap() &&
!SignedOverflow);
+ // Update SCEV add recurrence with existing no wrap flag information,
+ // requiring no recomputation to keep nuw/nsw information in the IR
+ if (SE) {
+ if (auto *PN = dyn_cast<PHINode>(X)) {
+ Loop *IVLoop = LI->getLoopFor(PN->getParent());
+ BasicBlock *Latch = IVLoop ? IVLoop->getLoopLatch() : nullptr;
+ if (Latch && PN->getParent() == IVLoop->getHeader() &&
+ PN->getIncomingValueForBlock(Latch) == &Inst &&
+ programUndefinedIfPoison(&Inst)) {
+ SCEV::NoWrapFlags Flags = SCEV::FlagAnyWrap;
+ if (Inst.hasNoUnsignedWrap())
+ Flags = ScalarEvolution::setFlags(Flags, SCEV::FlagNUW);
+ if (Inst.hasNoSignedWrap())
+ Flags = ScalarEvolution::setFlags(Flags, SCEV::FlagNSW);
+ if (Flags != SCEV::FlagAnyWrap) {
+ auto SetFlags = [&](Value *V) {
+ if (auto *AR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(V))) {
+ if (AR->getLoop() == IVLoop)
+ SE->setNoWrapFlags(const_cast<SCEVAddRecExpr *>(AR),
+ Flags);
+ }
+ };
+ SetFlags(PN);
+ SE->forgetValue(&Inst);
+ SetFlags(&Inst);
+ }
+ }
+ }
+ }
if (InnerI && isInstructionTriviallyDead(InnerI))
DeadInsts.emplace_back(InnerI);
}
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-preserve-scev-nowrap.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-preserve-scev-nowrap.ll
new file mode 100644
index 0000000000000..a1add1e9761e0
--- /dev/null
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-preserve-scev-nowrap.ll
@@ -0,0 +1,539 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes='loop-unroll,loop(indvars)' -verify-scev < %s | FileCheck %s --check-prefix=INDVARS
+; RUN: opt -S -passes='loop-unroll,loop(loop-reduce)' -verify-scev < %s | FileCheck %s --check-prefix=LSR
+; RUN: opt -S -passes='loop-unroll,invalidate<scalar-evolution>,loop(indvars)' < %s | FileCheck %s --check-prefix=RECOMPUTE
+
+; Updating ScalarEvolutionAnalysis add recurrence with existing no wrap flag information, requiring no recomputation to keep nuw/nsw information in the IR.
+
+%struct.HIP_vector_type = type { %union.anon }
+%union.anon = type { <2 x float> }
+
+define void @runtime_unroll_preserve-nowrap(ptr %queue, i32 %num_elements) {
+; INDVARS-LABEL: define void @runtime_unroll_preserve-nowrap(
+; INDVARS-SAME: ptr [[QUEUE:%.*]], i32 [[NUM_ELEMENTS:%.*]]) {
+; INDVARS-NEXT: [[ENTRY:.*:]]
+; INDVARS-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[NUM_ELEMENTS]], 0
+; INDVARS-NEXT: br i1 [[CMP5]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]
+; INDVARS: [[FOR_BODY_PREHEADER]]:
+; INDVARS-NEXT: [[TMP0:%.*]] = add i32 [[NUM_ELEMENTS]], -1
+; INDVARS-NEXT: [[TMP1:%.*]] = urem i32 [[TMP0]], 5
+; INDVARS-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
+; INDVARS-NEXT: [[XTRAITER:%.*]] = urem i32 [[TMP2]], 5
+; INDVARS-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP0]], 4
+; INDVARS-NEXT: br i1 [[TMP3]], label %[[FOR_BODY_EPIL_PREHEADER:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
+; INDVARS: [[FOR_BODY_PREHEADER_NEW]]:
+; INDVARS-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[NUM_ELEMENTS]], [[XTRAITER]]
+; INDVARS-NEXT: br label %[[FOR_BODY:.*]]
+; INDVARS: [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:.*]]:
+; INDVARS-NEXT: [[I_06_UNR:%.*]] = phi i32 [ [[ADD_4:%.*]], %[[FOR_BODY]] ]
+; INDVARS-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; INDVARS-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY_EPIL_PREHEADER]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
+; INDVARS: [[FOR_BODY_EPIL_PREHEADER]]:
+; INDVARS-NEXT: [[I_06_EPIL_INIT:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[I_06_UNR]], %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
+; INDVARS-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; INDVARS-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
+; INDVARS-NEXT: br label %[[FOR_BODY_EPIL:.*]]
+; INDVARS: [[FOR_BODY_EPIL]]:
+; INDVARS-NEXT: [[I_06_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], %[[FOR_BODY_EPIL]] ], [ [[I_06_EPIL_INIT]], %[[FOR_BODY_EPIL_PREHEADER]] ]
+; INDVARS-NEXT: [[EPIL_ITER:%.*]] = phi i32 [ 0, %[[FOR_BODY_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[FOR_BODY_EPIL]] ]
+; INDVARS-NEXT: [[ADD_EPIL]] = add nuw nsw i32 [[I_06_EPIL]], 1
+; INDVARS-NEXT: [[IDXPROM_EPIL:%.*]] = zext i32 [[ADD_EPIL]] to i64
+; INDVARS-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE:%.*]], ptr [[QUEUE]], i64 [[IDXPROM_EPIL]]
+; INDVARS-NEXT: [[IDXPROM1_EPIL:%.*]] = zext i32 [[I_06_EPIL]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_EPIL]]
+; INDVARS-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARRAYIDX_EPIL]], align 8
+; INDVARS-NEXT: store i64 [[TMP4]], ptr [[ARRAYIDX2_EPIL]], align 8
+; INDVARS-NEXT: [[EPIL_ITER_NEXT]] = add nuw i32 [[EPIL_ITER]], 1
+; INDVARS-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 [[EPIL_ITER_NEXT]], [[XTRAITER]]
+; INDVARS-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_BODY_EPIL]], label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]
+; INDVARS: [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]:
+; INDVARS-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT]]
+; INDVARS: [[FOR_COND_CLEANUP_LOOPEXIT]]:
+; INDVARS-NEXT: br label %[[FOR_COND_CLEANUP]]
+; INDVARS: [[FOR_COND_CLEANUP]]:
+; INDVARS-NEXT: ret void
+; INDVARS: [[FOR_BODY]]:
+; INDVARS-NEXT: [[I_06:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[ADD_4]], %[[FOR_BODY]] ]
+; INDVARS-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I_06]], 1
+; INDVARS-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD]] to i64
+; INDVARS-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM]]
+; INDVARS-NEXT: [[IDXPROM1:%.*]] = zext i32 [[I_06]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1]]
+; INDVARS-NEXT: [[TMP5:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
+; INDVARS-NEXT: store i64 [[TMP5]], ptr [[ARRAYIDX2]], align 8
+; INDVARS-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I_06]], 2
+; INDVARS-NEXT: [[IDXPROM_1:%.*]] = zext i32 [[ADD_1]] to i64
+; INDVARS-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_1]]
+; INDVARS-NEXT: [[IDXPROM1_1:%.*]] = zext i32 [[ADD]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_1]]
+; INDVARS-NEXT: [[TMP6:%.*]] = load i64, ptr [[ARRAYIDX_1]], align 8
+; INDVARS-NEXT: store i64 [[TMP6]], ptr [[ARRAYIDX2_1]], align 8
+; INDVARS-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I_06]], 3
+; INDVARS-NEXT: [[IDXPROM_2:%.*]] = zext i32 [[ADD_2]] to i64
+; INDVARS-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_2]]
+; INDVARS-NEXT: [[IDXPROM1_2:%.*]] = zext i32 [[ADD_1]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_2]]
+; INDVARS-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX_2]], align 8
+; INDVARS-NEXT: store i64 [[TMP7]], ptr [[ARRAYIDX2_2]], align 8
+; INDVARS-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[I_06]], 4
+; INDVARS-NEXT: [[IDXPROM_3:%.*]] = zext i32 [[ADD_3]] to i64
+; INDVARS-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_3]]
+; INDVARS-NEXT: [[IDXPROM1_3:%.*]] = zext i32 [[ADD_2]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_3]]
+; INDVARS-NEXT: [[TMP8:%.*]] = load i64, ptr [[ARRAYIDX_3]], align 8
+; INDVARS-NEXT: store i64 [[TMP8]], ptr [[ARRAYIDX2_3]], align 8
+; INDVARS-NEXT: [[ADD_4]] = add nuw nsw i32 [[I_06]], 5
+; INDVARS-NEXT: [[IDXPROM_4:%.*]] = zext i32 [[ADD_4]] to i64
+; INDVARS-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_4]]
+; INDVARS-NEXT: [[IDXPROM1_4:%.*]] = zext i32 [[ADD_3]] to i64
+; INDVARS-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_4]]
+; INDVARS-NEXT: [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX_4]], align 8
+; INDVARS-NEXT: store i64 [[TMP9]], ptr [[ARRAYIDX2_4]], align 8
+; INDVARS-NEXT: [[NITER_NCMP_4:%.*]] = icmp ne i32 [[ADD_4]], [[UNROLL_ITER]]
+; INDVARS-NEXT: br i1 [[NITER_NCMP_4]], label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], !llvm.loop [[LOOP2:![0-9]+]]
+;
+; LSR-LABEL: define void @runtime_unroll_preserve-nowrap(
+; LSR-SAME: ptr [[QUEUE:%.*]], i32 [[NUM_ELEMENTS:%.*]]) {
+; LSR-NEXT: [[ENTRY:.*:]]
+; LSR-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[NUM_ELEMENTS]], 0
+; LSR-NEXT: br i1 [[CMP5]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]
+; LSR: [[FOR_BODY_PREHEADER]]:
+; LSR-NEXT: [[TMP0:%.*]] = add i32 [[NUM_ELEMENTS]], -1
+; LSR-NEXT: [[TMP1:%.*]] = urem i32 [[TMP0]], 5
+; LSR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
+; LSR-NEXT: [[XTRAITER:%.*]] = urem i32 [[TMP2]], 5
+; LSR-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP0]], 4
+; LSR-NEXT: br i1 [[TMP3]], label %[[FOR_BODY_EPIL_PREHEADER:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
+; LSR: [[FOR_BODY_PREHEADER_NEW]]:
+; LSR-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[NUM_ELEMENTS]], [[XTRAITER]]
+; LSR-NEXT: br label %[[FOR_BODY:.*]]
+; LSR: [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:.*]]:
+; LSR-NEXT: [[I_06_UNR:%.*]] = phi i32 [ [[ADD_4:%.*]], %[[FOR_BODY]] ]
+; LSR-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; LSR-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY_EPIL_PREHEADER]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
+; LSR: [[FOR_BODY_EPIL_PREHEADER]]:
+; LSR-NEXT: [[I_06_EPIL_INIT:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[I_06_UNR]], %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
+; LSR-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; LSR-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
+; LSR-NEXT: br label %[[FOR_BODY_EPIL:.*]]
+; LSR: [[FOR_BODY_EPIL]]:
+; LSR-NEXT: [[I_06_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], %[[FOR_BODY_EPIL]] ], [ [[I_06_EPIL_INIT]], %[[FOR_BODY_EPIL_PREHEADER]] ]
+; LSR-NEXT: [[EPIL_ITER:%.*]] = phi i32 [ 0, %[[FOR_BODY_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[FOR_BODY_EPIL]] ]
+; LSR-NEXT: [[ADD_EPIL]] = add nuw nsw i32 [[I_06_EPIL]], 1
+; LSR-NEXT: [[IDXPROM_EPIL:%.*]] = zext i32 [[ADD_EPIL]] to i64
+; LSR-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE:%.*]], ptr [[QUEUE]], i64 [[IDXPROM_EPIL]]
+; LSR-NEXT: [[IDXPROM1_EPIL:%.*]] = zext i32 [[I_06_EPIL]] to i64
+; LSR-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_EPIL]]
+; LSR-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARRAYIDX_EPIL]], align 8
+; LSR-NEXT: store i64 [[TMP4]], ptr [[ARRAYIDX2_EPIL]], align 8
+; LSR-NEXT: [[EXITCOND_EPIL:%.*]] = icmp ne i32 [[ADD_EPIL]], [[NUM_ELEMENTS]]
+; LSR-NEXT: [[EPIL_ITER_NEXT]] = add i32 [[EPIL_ITER]], 1
+; LSR-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 [[EPIL_ITER_NEXT]], [[XTRAITER]]
+; LSR-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_BODY_EPIL]], label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]
+; LSR: [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]:
+; LSR-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT]]
+; LSR: [[FOR_COND_CLEANUP_LOOPEXIT]]:
+; LSR-NEXT: br label %[[FOR_COND_CLEANUP]]
+; LSR: [[FOR_COND_CLEANUP]]:
+; LSR-NEXT: ret void
+; LSR: [[FOR_BODY]]:
+; LSR-NEXT: [[I_06:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[ADD_4]], %[[FOR_BODY]] ]
+; LSR-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I_06]], 1
+; LSR-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD]] to i64
+; LSR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM]]
+; LSR-NEXT: [[IDXPROM1:%.*]] = zext i32 [[I_06]] to i64
+; LSR-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1]]
+; LSR-NEXT: [[TMP5:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
+; LSR-NEXT: store i64 [[TMP5]], ptr [[ARRAYIDX2]], align 8
+; LSR-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I_06]], 2
+; LSR-NEXT: [[IDXPROM_1:%.*]] = zext i32 [[ADD_1]] to i64
+; LSR-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_1]]
+; LSR-NEXT: [[IDXPROM1_1:%.*]] = zext i32 [[ADD]] to i64
+; LSR-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_1]]
+; LSR-NEXT: [[TMP6:%.*]] = load i64, ptr [[ARRAYIDX_1]], align 8
+; LSR-NEXT: store i64 [[TMP6]], ptr [[ARRAYIDX2_1]], align 8
+; LSR-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I_06]], 3
+; LSR-NEXT: [[IDXPROM_2:%.*]] = zext i32 [[ADD_2]] to i64
+; LSR-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_2]]
+; LSR-NEXT: [[IDXPROM1_2:%.*]] = zext i32 [[ADD_1]] to i64
+; LSR-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_2]]
+; LSR-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX_2]], align 8
+; LSR-NEXT: store i64 [[TMP7]], ptr [[ARRAYIDX2_2]], align 8
+; LSR-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[I_06]], 4
+; LSR-NEXT: [[IDXPROM_3:%.*]] = zext i32 [[ADD_3]] to i64
+; LSR-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_3]]
+; LSR-NEXT: [[IDXPROM1_3:%.*]] = zext i32 [[ADD_2]] to i64
+; LSR-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_3]]
+; LSR-NEXT: [[TMP8:%.*]] = load i64, ptr [[ARRAYIDX_3]], align 8
+; LSR-NEXT: store i64 [[TMP8]], ptr [[ARRAYIDX2_3]], align 8
+; LSR-NEXT: [[ADD_4]] = add nuw nsw i32 [[I_06]], 5
+; LSR-NEXT: [[IDXPROM_4:%.*]] = zext i32 [[ADD_4]] to i64
+; LSR-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM_4]]
+; LSR-NEXT: [[IDXPROM1_4:%.*]] = zext i32 [[ADD_3]] to i64
+; LSR-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_4]]
+; LSR-NEXT: [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX_4]], align 8
+; LSR-NEXT: store i64 [[TMP9]], ptr [[ARRAYIDX2_4]], align 8
+; LSR-NEXT: [[NITER_NCMP_4:%.*]] = icmp ne i32 [[ADD_4]], [[UNROLL_ITER]]
+; LSR-NEXT: br i1 [[NITER_NCMP_4]], label %[[FOR_BODY]], label %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], !llvm.loop [[LOOP2:![0-9]+]]
+;
+; RECOMPUTE-LABEL: define void @runtime_unroll_preserve-nowrap(
+; RECOMPUTE-SAME: ptr [[QUEUE:%.*]], i32 [[NUM_ELEMENTS:%.*]]) {
+; RECOMPUTE-NEXT: [[ENTRY:.*:]]
+; RECOMPUTE-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[NUM_ELEMENTS]], 0
+; RECOMPUTE-NEXT: br i1 [[CMP5]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]
+; RECOMPUTE: [[FOR_BODY_PREHEADER]]:
+; RECOMPUTE-NEXT: [[TMP0:%.*]] = add i32 [[NUM_ELEMENTS]], -1
+; RECOMPUTE-NEXT: [[TMP1:%.*]] = urem i32 [[TMP0]], 5
+; RECOMPUTE-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
+; RECOMPUTE-NEXT: [[XTRAITER:%.*]] = urem i32 [[TMP2]], 5
+; RECOMPUTE-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP0]], 4
+; RECOMPUTE-NEXT: br i1 [[TMP3]], label %[[FOR_BODY_EPIL_PREHEADER:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
+; RECOMPUTE: [[FOR_BODY_PREHEADER_NEW]]:
+; RECOMPUTE-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[NUM_ELEMENTS]], [[XTRAITER]]
+; RECOMPUTE-NEXT: br label %[[FOR_BODY:.*]]
+; RECOMPUTE: [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:.*]]:
+; RECOMPUTE-NEXT: [[I_06_UNR:%.*]] = phi i32 [ [[ADD_4:%.*]], %[[FOR_BODY]] ]
+; RECOMPUTE-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; RECOMPUTE-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_BODY_EPIL_PREHEADER]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]]
+; RECOMPUTE: [[FOR_BODY_EPIL_PREHEADER]]:
+; RECOMPUTE-NEXT: [[I_06_EPIL_INIT:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[I_06_UNR]], %[[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
+; RECOMPUTE-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
+; RECOMPUTE-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
+; RECOMPUTE-NEXT: br label %[[FOR_BODY_EPIL:.*]]
+; RECOMPUTE: [[FOR_BODY_EPIL]]:
+; RECOMPUTE-NEXT: [[I_06_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], %[[FOR_BODY_EPIL]] ], [ [[I_06_EPIL_INIT]], %[[FOR_BODY_EPIL_PREHEADER]] ]
+; RECOMPUTE-NEXT: [[EPIL_ITER:%.*]] = phi i32 [ 0, %[[FOR_BODY_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], %[[FOR_BODY_EPIL]] ]
+; RECOMPUTE-NEXT: [[ADD_EPIL]] = add nuw nsw i32 [[I_06_EPIL]], 1
+; RECOMPUTE-NEXT: [[IDXPROM_EPIL:%.*]] = zext i32 [[ADD_EPIL]] to i64
+; RECOMPUTE-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE:%.*]], ptr [[QUEUE]], i64 [[IDXPROM_EPIL]]
+; RECOMPUTE-NEXT: [[IDXPROM1_EPIL:%.*]] = zext i32 [[I_06_EPIL]] to i64
+; RECOMPUTE-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1_EPIL]]
+; RECOMPUTE-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARRAYIDX_EPIL]], align 8
+; RECOMPUTE-NEXT: store i64 [[TMP4]], ptr [[ARRAYIDX2_EPIL]], align 8
+; RECOMPUTE-NEXT: [[EPIL_ITER_NEXT]] = add nuw i32 [[EPIL_ITER]], 1
+; RECOMPUTE-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 [[EPIL_ITER_NEXT]], [[XTRAITER]]
+; RECOMPUTE-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_BODY_EPIL]], label %[[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:.*]], !llvm.loop [[LOOP0:![0-9]+]]
+; RECOMPUTE: [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]:
+; RECOMPUTE-NEXT: br label %[[FOR_COND_CLEANUP_LOOPEXIT]]
+; RECOMPUTE: [[FOR_COND_CLEANUP_LOOPEXIT]]:
+; RECOMPUTE-NEXT: br label %[[FOR_COND_CLEANUP]]
+; RECOMPUTE: [[FOR_COND_CLEANUP]]:
+; RECOMPUTE-NEXT: ret void
+; RECOMPUTE: [[FOR_BODY]]:
+; RECOMPUTE-NEXT: [[I_06:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[ADD_4]], %[[FOR_BODY]] ]
+; RECOMPUTE-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I_06]], 1
+; RECOMPUTE-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD]] to i64
+; RECOMPUTE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM]]
+; RECOMPUTE-NEXT: [[IDXPROM1:%.*]] = zext i32 [[I_06]] to i64
+; RECOMPUTE-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]], i64 [[IDXPROM1]]
+; RECOMPUTE-NEXT: [[TMP5:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
+; RECOMPUTE-NEXT: store i64 [[TMP5]], ptr [[ARRAYIDX2]], align 8
+; RECOMPUTE-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I_06]], 2
+; RECOMPUTE-NEXT: [[IDXPROM_1:%.*]] = zext i32 [[ADD_1]] to i64
+; RECOMPUTE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds [[STRUCT_HIP_VECTOR_TYPE]], ptr [[QUEUE]]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/227913
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