[llvm] [AMDGPU] Use isGFX125xOnly as the assembler predicate for tensor load/store (PR #227887)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Changpeng Fang (changpeng)

<details>
<summary>Changes</summary>

…/store

The VIMAGE_TENSOR gfx1250 real instructions are only available on GFX125x, so predicate the assembler on isGFX125xOnly rather than on the HasTDMInsts feature.

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Full diff: https://github.com/llvm/llvm-project/pull/227887.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/MIMGInstructions.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index f32ecdb200c96..f863e10e2b0cf 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -2346,7 +2346,7 @@ class VIMAGE_TENSOR_Real <bits<8> op, VIMAGE_TENSOR_Pseudo ps, string opName = p
 }
 
 multiclass VIMAGE_TENSOR_Real_gfx1250<bits<8> op> {
-  let AssemblerPredicate = HasTDMInsts, DecoderNamespace = "GFX1250" in {
+  let AssemblerPredicate = isGFX125xOnly, DecoderNamespace = "GFX1250" in {
     foreach DSuffix = ["_d2", "_d4"] in {
       defvar ps = !cast<VIMAGE_TENSOR_Pseudo>(NAME # DSuffix);
       def DSuffix # _gfx1250 : VIMAGE_TENSOR_Real<op, ps, ps.Mnemonic>,

``````````

</details>


https://github.com/llvm/llvm-project/pull/227887