[llvm] b60c46d - [VPlan] Add epilogue VPlan print tests with AnyOf and FindIV (NFC) (#227827)

[via llvm-commits]

Author: Florian Hahn
Date: 2026-09-30T19:49:56Z
New Revision: b60c46d11bd399f3bc9d4f1215ecc18ddae06484

URL: https://github.com/llvm/llvm-project/commit/b60c46d11bd399f3bc9d4f1215ecc18ddae06484
DIFF: https://github.com/llvm/llvm-project/commit/b60c46d11bd399f3bc9d4f1215ecc18ddae06484.diff

LOG: [VPlan] Add epilogue VPlan print tests with AnyOf and FindIV (NFC) (#227827)

Add printing tests with epilogue loops with AnyOf and FindIV reductions.

They need special handling for their resume values, which is not
yet modeled in VPlan.

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll
index 9faf0974d8ca0..e477b32265026 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll
@@ -929,3 +929,64 @@ bail:
 done:
   ret i32 0
 }
+
+; AnyOf and FindIV reductions adjust the resume value of the main loop in the
+; preheader of the epilogue vector loop.
+define i32 @any_of_resume(ptr noalias %src, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'any_of_resume'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK:       vec.epilog.ph:
+; CHECK-NEXT:    EMIT vp<[[VP3:%[0-9]+]]> = and ir<%n>, ir<3>
+; CHECK-NEXT:    EMIT vp<%n.vec> = sub ir<%n>, vp<[[VP3]]>
+; CHECK-NEXT:    EMIT vp<[[VP4:%[0-9]+]]> = broadcast ir<[[ADJ:%.+]]>
+; CHECK-NEXT:  Successor(s): vec.epilog.vector.body
+; CHECK-EMPTY:
+; CHECK-NEXT:  vec.epilog.vector.body:
+; CHECK-NEXT:    EMIT-SCALAR vp<%index> = phi [ ir<%vec.epilog.resume.val>, vec.epilog.ph ], [ vp<%index.next>, vec.epilog.vector.body ]
+; CHECK-NEXT:    WIDEN-REDUCTION-PHI ir<%rdx> = phi (any-of) vp<[[VP4]]>, vp<{{.+}}>
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %rdx = phi i32 [ 0, %entry ], [ %sel, %loop ]
+  %gep = getelementptr inbounds i8, ptr %src, i64 %iv
+  %l = load i8, ptr %gep
+  %c = icmp eq i8 %l, 0
+  %sel = select i1 %c, i32 1, i32 %rdx
+  %iv.next = add i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, %n
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i32 %sel
+}
+
+define i64 @find_iv_resume(ptr noalias %a, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'find_iv_resume'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK:       vec.epilog.ph:
+; CHECK-NEXT:    EMIT vp<[[VP3:%[0-9]+]]> = and ir<%n>, ir<3>
+; CHECK-NEXT:    EMIT vp<%n.vec> = sub ir<%n>, vp<[[VP3]]>
+; CHECK-NEXT:    EMIT vp<[[VP4:%[0-9]+]]> = broadcast ir<[[ADJ:%.+]]>
+; CHECK:       vec.epilog.vector.body:
+; CHECK:         WIDEN-REDUCTION-PHI ir<%rdx> = phi (find-iv) vp<[[VP4]]>, ir<%sel>
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %rdx = phi i64 [ 3, %entry ], [ %sel, %loop ]
+  %gep = getelementptr inbounds i64, ptr %a, i64 %iv
+  %l = load i64, ptr %gep
+  %c = icmp eq i64 %l, 3
+  %sel = select i1 %c, i64 %iv, i64 %rdx
+  %iv.next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, %n
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i64 %sel
+}