[llvm] [AMDGPU][GlobalISel] Fold neg/abs modifiers when mad-mix selects the low half (PR #223535)
Domenic Nutile via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 11:48:55 PDT 2026
https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/223535
>From 809b724992b54714f861ae2f8ffe87d73c226548 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Mon, 14 Sep 2026 17:03:29 -0400
Subject: [PATCH 1/2] [AMDGPU][GlobalISel] Fold neg/abs modifiers when mad-mix
selects the low half
selectVOP3PMadMixModsImpl re-runs the fneg/fabs match after rewriting Src
to the 32-bit register the 16-bit value is a half of, but only did so on
the isExtractHiElt path, not for isExtractLoElt.
The two halves are not symmetric. An fneg/fabs of a 32-bit float only
touches bit 31, which is the sign bit of the high half, so folding it
into a modifier on the selected high half is correct. The low half's sign
bit is bit 15, which such an fneg/fabs leaves alone, so only a modifier
that acts on each 16-bit element can be folded there. So the source must be
a 2 x 16-bit vector to fold it.
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 15 +-
.../GlobalISel/combine-fma-sub-ext-neg-mul.ll | 26 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 42 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 503 ++++----
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 1062 ++++++++++++++++-
5 files changed, 1305 insertions(+), 343 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 831f3e3e44816..c48d2b1c242cb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7222,13 +7222,16 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
// Src is now the 32-bit source and op_sel picks its high half.
Mods |= SISrcMods::OP_SEL_0;
CheckAbsNeg();
- } else {
- // op_sel already picks the low half, so use the 32-bit source directly if
- // the 16-bit value is the low half of one. Otherwise Src is genuinely 16
- // bits wide and widenSrcIfVGPR16 widens it when the operand is
- // rendered.
- isExtractLoElt(*MRI, Src, Src);
+ } else if (isExtractLoElt(*MRI, Src, Src)) {
+ // op_sel already picks the low half, so the 32-bit source can be used
+ // directly. Unlike the high half, only an fneg/fabs that acts on each
+ // 16-bit element can be folded here: one that acts on the 32-bit value
+ // touches bit 31 and leaves the low half alone.
+ if (MRI->getType(Src) == LLT::fixed_vector(2, 16))
+ CheckAbsNeg();
}
+ // Otherwise Src is genuinely 16 bits wide and widenSrcIfVGPR16 widens it
+ // when the operand is rendered.
Matched = true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
index feee19e641d7f..b90285d75c28a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
@@ -93,12 +93,11 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul(<4 x half> %x,
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v0, -v2, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, -v3, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v4
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
@@ -123,12 +122,11 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul(<4 x half> %x,
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v0, -v2, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, -v3, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v4
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
@@ -154,12 +152,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul2(<4 x float> %
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, -v6, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, -v7, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
@@ -183,12 +179,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul2(<4 x float> %
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
-; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, -v6, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, -v7, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0]
-; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 6a76113ac3817..3b1642c37ec72 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -2200,11 +2200,11 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX9-FLUSH-NEXT: v_mov_b32_e32 v5, 1.0
; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v4
-; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v2, v5 op_sel_hi:[1,0,0]
+; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -|v0|, v2, v5 op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -|v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v2, v2
; GFX9-FLUSH-NEXT: v_mad_f32 v7, v7, v4, v4
-; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
+; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -|v0|, v6, v5 op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v2
; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v4
@@ -2226,7 +2226,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4
-; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -|v0|, v3, neg(0) op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -|v0|, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6
@@ -2234,7 +2234,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v5, v3
; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -|v0|, v5, neg(0) op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_fma_mix_f32 v0, -|v0|, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX10-IEEE-NEXT: v_add_f32_e32 v0, 1.0, v0
@@ -2286,19 +2286,18 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-NEXT: v_mov_b32_e32 v5, 1.0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_fma_mix_f32 v6, -|v0|, v3, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v7, -|v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-NEXT: v_fma_f32 v6, v6, v3, v3
; GFX11-NEXT: v_fma_f32 v7, v7, v4, v4
+; GFX11-NEXT: v_fma_mix_f32 v8, -|v0|, v6, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_fma_mix_f32 v6, -v1, v3, v5 op_sel_hi:[1,0,0]
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT: v_fma_f32 v6, v6, v3, v3
-; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v7 op_sel_hi:[0,1,0]
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
-; GFX11-NEXT: v_mul_f32_e32 v3, v8, v3
+; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_and_b32 v0, 0xff800000, v0
; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v7 op_sel_hi:[0,1,0]
; GFX11-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v6 op_sel_hi:[0,1,0]
+; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2497,11 +2496,11 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX9-FLUSH-NEXT: v_mov_b32_e32 v5, -1.0
; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v4
-; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, v1, v2, v5 op_sel_hi:[1,0,0]
+; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, |v0|, v2, v5 op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, |v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v2, -v2
; GFX9-FLUSH-NEXT: v_mad_f32 v7, v7, v4, -v4
-; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
+; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -|v0|, v6, v5 op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mad_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v2
; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v4
@@ -2523,7 +2522,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4
-; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v1, v3, neg(0) op_sel_hi:[1,0,0]
+; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, |v0|, v3, neg(0) op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, |v0|, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_add_f32_e32 v5, -1.0, v5
; GFX10-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6
@@ -2531,7 +2530,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
; GFX10-IEEE-NEXT: v_sub_f32_e32 v5, v5, v3
; GFX10-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0]
+; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -|v0|, v5, neg(0) op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_fma_mix_f32 v0, -|v0|, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7
; GFX10-IEEE-NEXT: v_add_f32_e32 v0, -1.0, v0
@@ -2583,19 +2582,18 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-NEXT: v_mov_b32_e32 v5, -1.0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_fma_mix_f32 v6, |v0|, v3, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v7, |v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v3
; GFX11-NEXT: v_fma_f32 v7, v7, v4, -v4
+; GFX11-NEXT: v_fma_mix_f32 v8, -|v0|, v6, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v5 op_sel_hi:[1,0,0]
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v3
-; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v7 op_sel_hi:[0,1,0]
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
-; GFX11-NEXT: v_mul_f32_e32 v3, v8, v3
+; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_and_b32 v0, 0xff800000, v0
; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v7 op_sel_hi:[0,1,0]
; GFX11-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v6 op_sel_hi:[0,1,0]
+; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index c6bab22bf2641..529caae821fa7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -1987,63 +1987,63 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
-; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_trunc_f32_e32 v12, v8
; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX10-NEXT: v_log_f32_e32 v3, v3
; GFX10-NEXT: v_log_f32_e32 v4, v4
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_mov_b32_e32 v6, 0.5
; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
-; GFX10-NEXT: v_trunc_f32_e32 v13, v6
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v10, -v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v2
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v13, v6
-; GFX10-NEXT: v_trunc_f32_e32 v12, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v12, v5
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v9
+; GFX10-NEXT: v_trunc_f32_e32 v6, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v10
+; GFX10-NEXT: v_trunc_f32_e32 v6, v5
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v2
; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v0
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_trunc_f32_e32 v10, v8
-; GFX10-NEXT: v_exp_f32_e32 v2, v3
-; GFX10-NEXT: v_trunc_f32_e32 v3, v1
-; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v10, v8
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s4
+; GFX10-NEXT: v_exp_f32_e32 v3, v3
+; GFX10-NEXT: v_exp_f32_e32 v2, v4
+; GFX10-NEXT: v_trunc_f32_e32 v4, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v12, v8
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v6, v5
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v4, v1
+; GFX10-NEXT: s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v3, v3, v11
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: v_ldexp_f32 v1, v4, v11
-; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo
-; GFX10-NEXT: s_and_b32 s5, s8, s10
-; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
-; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4
; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: s_and_b32 s4, s9, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
-; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v7
+; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10-NEXT: s_and_b32 vcc_lo, s6, s5
+; GFX10-NEXT: s_and_b32 s5, s8, s10
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_rhs:
@@ -2055,78 +2055,75 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.h
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
-; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v9 :: v_dual_and_b32 v9, 0x80000000, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0x80000000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v3, v3, v6 :: v_dual_mov_b32 v6, 0.5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v12, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v13, v6
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v13, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v8
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v10, v8
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, -v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0x80000000, v2
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v6, v5
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v4, v1
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v2, v0
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v4, v11
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v11
+; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
-; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7
-; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_rhs:
@@ -2135,85 +2132,83 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v7
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v8, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v5
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v11, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_sub_f32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v7
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v12, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0x7fffffff, v3, v8
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v10
-; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v9
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v12, v7
+; GFX11-FAKE16-NEXT: v_and_or_b32 v7, 0x7fffffff, v3, v8
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v10, v5
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0x80000000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v5, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v13
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%y.fneg = fneg <2 x half> %y
@@ -2464,15 +2459,17 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2|
; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0|
-; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v2
; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24
+; GFX10-NEXT: v_trunc_f32_e32 v11, v5
; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5
+; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v11, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3
@@ -2480,49 +2477,47 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX10-NEXT: v_log_f32_e32 v3, v3
; GFX10-NEXT: v_log_f32_e32 v4, v4
; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7
-; GFX10-NEXT: v_mov_b32_e32 v7, 0.5
+; GFX10-NEXT: v_mov_b32_e32 v6, 0.5
; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3
-; GFX10-NEXT: v_trunc_f32_e32 v12, v6
-; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4
-; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_fma_mix_f32 v10, -v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v12, v6
; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4
+; GFX10-NEXT: v_trunc_f32_e32 v6, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4
+; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v6, v10
+; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX10-NEXT: v_add_f32_e32 v4, v4, v9
; GFX10-NEXT: v_trunc_f32_e32 v7, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s4
-; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s4
; GFX10-NEXT: v_trunc_f32_e32 v9, v8
-; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
-; GFX10-NEXT: v_trunc_f32_e32 v10, v5
-; GFX10-NEXT: v_and_b32_e32 v1, 0x80000000, v0
; GFX10-NEXT: v_exp_f32_e32 v3, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v8
; GFX10-NEXT: v_exp_f32_e32 v4, v4
-; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v10, v5
+; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v8
; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo
; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo
+; GFX10-NEXT: v_ldexp_f32 v1, v3, v10
+; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0
+; GFX10-NEXT: v_ldexp_f32 v2, v4, v2
; GFX10-NEXT: s_and_b32 s4, s4, s5
; GFX10-NEXT: s_and_b32 s5, s8, s10
-; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v4, v13
-; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11
-; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v3, s4
+; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v6
+; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v0, s4
; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX10-NEXT: s_and_b32 s4, s9, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4
-; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4
; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
+; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -2533,80 +2528,83 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v5
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v7
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, v4, v9 :: v_dual_sub_f32 v3, v3, v6
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v8
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x80000000, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, -v1, v6, neg(0) op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v6, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v10, v5
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, v2
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v13
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v3, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
+; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v6
+; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, v3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v1, v0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
@@ -2614,78 +2612,75 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v8, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0x80000000, v2
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1
+; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_sub_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, s0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v6
-; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v9
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, v11, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0x80000000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0x7fffffff, v3, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v5
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v10
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v10, 0x7fffffff, v3, v12
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index d1d84083df1e2..5021b3fb5b413 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -2417,6 +2417,91 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
ret float %result
}
+define float @v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SDAG-GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SDAG-VI-NEXT: v_mad_f32 v0, -v0, v1, v2
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v3, -v0
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-VI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_f16lo_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fneg = fneg <2 x half> %src0.arg.bc
+ %src0 = extractelement <2 x half> %fneg, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %src2.ext = fpext half %src2 to float
+ %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
+ ret float %result
+}
+
define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GFX1100: ; %bb.0:
@@ -2504,6 +2589,91 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
ret float %result
}
+define float @v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
+; SDAG-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; SDAG-VI-NEXT: v_mac_f32_e32 v0, v3, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-VI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_f16lo_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %src0 = extractelement <2 x half> %fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %src2.ext = fpext half %src2 to float
+ %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
+ ret float %result
+}
+
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GFX1100: ; %bb.0:
@@ -2592,6 +2762,92 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg,
ret float %result
}
+define float @v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SDAG-GFX9GEN-NEXT: v_mad_f32 v0, -v0, v1, v2
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SDAG-VI-NEXT: v_mad_f32 v0, -v0, v1, v2
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v3, -|v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-GFX9GEN-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-VI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_f16lo_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GISEL-CI-NEXT: v_mac_f32_e32 v0, v3, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %fneg.fabs = fneg <2 x half> %fabs
+ %src0 = extractelement <2 x half> %fneg.fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %src2.ext = fpext half %src2 to float
+ %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
+ ret float %result
+}
+
define float @v_mad_mix_f32_f16lo_add_f16lo(half %src0, half %src1) {
; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
; GFX1100: ; %bb.0:
@@ -3974,71 +4230,160 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
ret float %result
}
-define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+define float @v_mad_mix_f32_preextractfneg_f16lo_add_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; SDAG-GFX900: ; %bb.0:
; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; GFX906: ; %bb.0:
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; SDAG-GFX9GEN: ; %bb.0:
; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; SDAG-VI: ; %bb.0:
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
;
-; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; SDAG-CI: ; %bb.0:
; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0
; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
-; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GISEL-GFX900-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
-; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_add_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fneg = fneg <2 x half> %src0.arg.bc
+ %src0 = extractelement <2 x half> %fneg, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fadd float %src0.ext, %src1.ext
+ ret float %result
+}
+
+define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
@@ -4065,6 +4410,95 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
ret float %result
}
+define float @v_mad_mix_f32_preextractfabs_f16lo_add_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_add_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %src0 = extractelement <2 x half> %fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fadd float %src0.ext, %src1.ext
+ ret float %result
+}
+
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; GFX1100: ; %bb.0:
@@ -4129,28 +4563,298 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
-; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %fneg.fabs = fneg <2 x half> %fabs
+ %src0 = extractelement <2 x half> %fneg.fabs, i32 1
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fadd float %src0.ext, %src1.ext
+ ret float %result
+}
+
+define float @v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_add_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %fneg.fabs = fneg <2 x half> %fabs
+ %src0 = extractelement <2 x half> %fneg.fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fadd float %src0.ext, %src1.ext
+ ret float %result
+}
+
+; The fneg is on a 32-bit float, so it only flips bit 31. That is the sign bit
+; of the high half, so it can be folded into a neg modifier there, but it must
+; not be folded when the low half is selected.
+define float @v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo(float %src0.arg, half %src1) {
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-GFX906: ; %bb.0:
+; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-GFX906: ; %bb.0:
+; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractf32fneg_f16lo_add_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %fneg = fneg float %src0.arg
+ %fneg.bc = bitcast float %fneg to <2 x half>
+ %src0 = extractelement <2 x half> %fneg.bc, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fadd float %src0.ext, %src1.ext
+ ret float %result
+}
+
+define float @v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo(float %src0.arg, half %src1) {
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; GFX900: ; %bb.0:
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX900-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; SDAG-GFX906: ; %bb.0:
+; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9GEN-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; GFX9GEN: ; %bb.0:
+; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; CI-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GISEL-CI: ; %bb.0:
-; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
-; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1
-; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
- %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
- %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
- %fneg.fabs = fneg <2 x half> %fabs
- %src0 = extractelement <2 x half> %fneg.fabs, i32 1
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractf32fneg_f16hi_add_f16lo:
+; GISEL-GFX906: ; %bb.0:
+; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
+ %fneg = fneg float %src0.arg
+ %fneg.bc = bitcast float %fneg to <2 x half>
+ %src0 = extractelement <2 x half> %fneg.bc, i32 1
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = fadd float %src0.ext, %src1.ext
@@ -5476,6 +6180,95 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %
ret float %result
}
+define float @v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfneg_f16lo_mul_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fneg = fneg <2 x half> %src0.arg.bc
+ %src0 = extractelement <2 x half> %fneg, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fmul float %src0.ext, %src1.ext
+ ret float %result
+}
+
define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
; GFX1100: ; %bb.0:
@@ -5567,6 +6360,95 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %
ret float %result
}
+define float @v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabs_f16lo_mul_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %src0 = extractelement <2 x half> %fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fmul float %src0.ext, %src1.ext
+ ret float %result
+}
+
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
; GFX1100: ; %bb.0:
@@ -5659,6 +6541,96 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, ha
ret float %result
}
+define float @v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo(i32 %src0.arg, half %src1) {
+; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; SDAG-GFX900: ; %bb.0:
+; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
+; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GFX906: ; %bb.0:
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; SDAG-GFX9GEN: ; %bb.0:
+; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
+; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
+; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; SDAG-CI: ; %bb.0:
+; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
+; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GISEL-GFX900: ; %bb.0:
+; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX900-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GISEL-GFX9GEN: ; %bb.0:
+; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9GEN-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16lo_mul_f16lo:
+; GISEL-CI: ; %bb.0:
+; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
+ %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
+ %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
+ %fneg.fabs = fneg <2 x half> %fabs
+ %src0 = extractelement <2 x half> %fneg.fabs, i32 0
+ %src0.ext = fpext half %src0 to float
+ %src1.ext = fpext half %src1 to float
+ %result = fmul float %src0.ext, %src1.ext
+ ret float %result
+}
+
define float @v_mad_mix_f32_f16lo_sub_f16lo(half %src0, half %src1) {
; GFX1100-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
; GFX1100: ; %bb.0:
>From fd69de9788c49164fb66b0e2612e1f4548752618 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 29 Sep 2026 12:43:15 -0400
Subject: [PATCH 2/2] Use isFixedVector instead of LLT equality
---
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index c48d2b1c242cb..21adf311c3355 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7227,7 +7227,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
// directly. Unlike the high half, only an fneg/fabs that acts on each
// 16-bit element can be folded here: one that acts on the 32-bit value
// touches bit 31 and leaves the low half alone.
- if (MRI->getType(Src) == LLT::fixed_vector(2, 16))
+ if (MRI->getType(Src).isFixedVector(2, 16))
CheckAbsNeg();
}
// Otherwise Src is genuinely 16 bits wide and widenSrcIfVGPR16 widens it
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