[llvm] [CodeGen] Use SmallSetVectorImpl for getRegAllocationHints (PR #224472)
Nick Desaulniers via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 10:54:54 PDT 2026
https://github.com/nickdesaulniers updated https://github.com/llvm/llvm-project/pull/224472
>From 848dc43aa7912bccde90a8535be2643fd7b4a189 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers at google.com>
Date: Thu, 17 Sep 2026 14:47:48 -0700
Subject: [PATCH 1/2] [ADT] Default SmallSetVector N to 16 and add
initializer_list ctor
Give llvm::SmallSetVector<T, N> a default template parameter N = 16 and
update existing SmallSetVector<T, 16> uses in llvm/ to omit the explicit
size argument.
Also add a std::initializer_list<T> constructor to SetVector (inherited
by SmallSetVector).
Assisted-by: Gemini
Link: #219007
---
llvm/include/llvm/ADT/SetVector.h | 5 +++-
llvm/include/llvm/TableGen/SetTheory.h | 2 +-
llvm/include/llvm/Transforms/IPO/Attributor.h | 6 ++--
.../Transforms/Utils/InstructionWorklist.h | 2 +-
llvm/lib/Analysis/AliasAnalysisEvaluator.cpp | 2 +-
llvm/lib/Analysis/DemandedBits.cpp | 2 +-
llvm/lib/Analysis/InlineCost.cpp | 2 +-
llvm/lib/Analysis/MemorySSAUpdater.cpp | 2 +-
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 2 +-
llvm/lib/CodeGen/GlobalMerge.cpp | 2 +-
llvm/lib/CodeGen/InlineSpiller.cpp | 4 +--
llvm/lib/CodeGen/MachineBlockPlacement.cpp | 2 +-
llvm/lib/CodeGen/ProcessImplicitDefs.cpp | 2 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +--
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 ++--
.../CodeGen/SelectionDAG/LegalizeTypes.cpp | 11 +++----
.../SelectionDAG/StatepointLowering.cpp | 2 +-
llvm/lib/CodeGen/ShrinkWrap.cpp | 2 +-
llvm/lib/CodeGen/SjLjEHPrepare.cpp | 2 +-
llvm/lib/Linker/IRMover.cpp | 4 +--
.../Target/AMDGPU/AMDGPUCoExecSchedStrategy.h | 4 +--
.../Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp | 29 +++++++++----------
.../lib/Target/DirectX/DXILResourceAccess.cpp | 6 ++--
llvm/lib/Target/X86/X86LowerAMXType.cpp | 9 +++---
llvm/lib/Transforms/IPO/AlwaysInliner.cpp | 2 +-
llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 10 +++----
.../Instrumentation/MemorySanitizer.cpp | 2 +-
llvm/lib/Transforms/Scalar/ADCE.cpp | 2 +-
llvm/lib/Transforms/Scalar/DCE.cpp | 4 +--
.../Transforms/Scalar/DFAJumpThreading.cpp | 4 +--
llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 2 +-
.../Scalar/RewriteStatepointsForGC.cpp | 2 +-
llvm/lib/Transforms/Scalar/SROA.cpp | 6 ++--
.../Transforms/Scalar/SimpleLoopUnswitch.cpp | 2 +-
.../Transforms/Utils/BreakCriticalEdges.cpp | 2 +-
llvm/lib/Transforms/Utils/LCSSA.cpp | 2 +-
llvm/lib/Transforms/Utils/Local.cpp | 11 ++++---
llvm/lib/Transforms/Utils/ModuleUtils.cpp | 6 ++--
llvm/lib/Transforms/Utils/SCCPSolver.cpp | 2 +-
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 8 ++---
.../Transforms/Vectorize/SLPVectorizer.cpp | 2 +-
.../Transforms/Vectorize/VectorCombine.cpp | 2 +-
llvm/unittests/ADT/SetVectorTest.cpp | 10 +++++++
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 11 ++++---
44 files changed, 108 insertions(+), 98 deletions(-)
diff --git a/llvm/include/llvm/ADT/SetVector.h b/llvm/include/llvm/ADT/SetVector.h
index bc0ac2583327b..0a9f3c269fb88 100644
--- a/llvm/include/llvm/ADT/SetVector.h
+++ b/llvm/include/llvm/ADT/SetVector.h
@@ -28,6 +28,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Compiler.h"
#include <cassert>
+#include <initializer_list>
namespace llvm {
@@ -88,6 +89,8 @@ class SetVector {
SetVector(llvm::from_range_t, Range &&R)
: SetVector(adl_begin(R), adl_end(R)) {}
+ SetVector(std::initializer_list<T> IL) { insert(IL.begin(), IL.end()); }
+
[[nodiscard]] ArrayRef<value_type> getArrayRef() const { return vector_; }
/// Clear the SetVector and return the underlying vector.
@@ -341,7 +344,7 @@ class SetVector {
/// A SetVector that performs no allocations if smaller than
/// a certain size.
-template <typename T, unsigned N>
+template <typename T, unsigned N = 16>
class SmallSetVector : public SetVector<T, SmallVector<T, N>, DenseSet<T>, N> {
public:
using SetVector<T, SmallVector<T, N>, DenseSet<T>, N>::SetVector;
diff --git a/llvm/include/llvm/TableGen/SetTheory.h b/llvm/include/llvm/TableGen/SetTheory.h
index 23eb466407d73..3056cb40876cd 100644
--- a/llvm/include/llvm/TableGen/SetTheory.h
+++ b/llvm/include/llvm/TableGen/SetTheory.h
@@ -65,7 +65,7 @@ class Record;
class SetTheory {
public:
using RecVec = std::vector<const Record *>;
- using RecSet = SmallSetVector<const Record *, 16>;
+ using RecSet = SmallSetVector<const Record *>;
/// Operator - A callback representing a DAG operator.
class LLVM_ABI Operator {
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h
index 066883afafb95..604068385532a 100644
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
@@ -2570,10 +2570,10 @@ struct Attributor {
ToBeChangedValues;
/// Instructions we replace with `unreachable` insts after manifest is done.
- SmallSetVector<WeakVH, 16> ToBeChangedToUnreachableInsts;
+ SmallSetVector<WeakVH> ToBeChangedToUnreachableInsts;
/// Invoke instructions with at least a single dead successor block.
- SmallSetVector<WeakVH, 16> InvokeWithDeadSuccessor;
+ SmallSetVector<WeakVH> InvokeWithDeadSuccessor;
/// A flag that indicates which stage of the process we are in. Initially, the
/// phase is SEEDING. Phase is changed in `Attributor::run()`
@@ -2598,7 +2598,7 @@ struct Attributor {
/// Container with all the query AAs that requested an update via
/// registerForUpdate.
- SmallSetVector<AbstractAttribute *, 16> QueryAAsAwaitingUpdate;
+ SmallSetVector<AbstractAttribute *> QueryAAsAwaitingUpdate;
/// User provided configuration for this Attributor instance.
const AttributorConfig Configuration;
diff --git a/llvm/include/llvm/Transforms/Utils/InstructionWorklist.h b/llvm/include/llvm/Transforms/Utils/InstructionWorklist.h
index 5a46fff651336..84b49a8516617 100644
--- a/llvm/include/llvm/Transforms/Utils/InstructionWorklist.h
+++ b/llvm/include/llvm/Transforms/Utils/InstructionWorklist.h
@@ -28,7 +28,7 @@ class InstructionWorklist {
/// These instructions will be added in reverse order after the current
/// combine has finished. This means that these instructions will be visited
/// in the order they have been added.
- SmallSetVector<Instruction *, 16> Deferred;
+ SmallSetVector<Instruction *> Deferred;
public:
InstructionWorklist() = default;
diff --git a/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp b/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
index 4ba4abb668ded..7264ff607d020 100644
--- a/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
+++ b/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
@@ -105,7 +105,7 @@ void AAEvaluator::runInternal(Function &F, AAResults &AA) {
++FunctionCount;
SetVector<std::pair<const Value *, Type *>> Pointers;
- SmallSetVector<Instruction *, 16> OtherMemOps;
+ SmallSetVector<Instruction *> OtherMemOps;
SetVector<Value *> Loads;
SetVector<Value *> Stores;
diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp
index 35de778d9f093..01963db50786b 100644
--- a/llvm/lib/Analysis/DemandedBits.cpp
+++ b/llvm/lib/Analysis/DemandedBits.cpp
@@ -366,7 +366,7 @@ void DemandedBits::performAnalysis() {
AliveBits.clear();
DeadUses.clear();
- SmallSetVector<Instruction*, 16> Worklist;
+ SmallSetVector<Instruction *> Worklist;
// Collect the set of "root" instructions that are known live.
for (Instruction &I : instructions(F)) {
diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp
index 0a540c1b8fb67..f8e0cd55b39fa 100644
--- a/llvm/lib/Analysis/InlineCost.cpp
+++ b/llvm/lib/Analysis/InlineCost.cpp
@@ -2975,7 +2975,7 @@ InlineResult CallAnalyzer::analyze() {
// basic blocks in a breadth-first order as we insert live successors. To
// accomplish this, prioritizing for small iterations because we exit after
// crossing our threshold, we use a small-size optimized SetVector.
- typedef SmallSetVector<BasicBlock *, 16> BBSetVector;
+ typedef SmallSetVector<BasicBlock *> BBSetVector;
BBSetVector BBWorklist;
BBWorklist.insert(&F.getEntryBlock());
diff --git a/llvm/lib/Analysis/MemorySSAUpdater.cpp b/llvm/lib/Analysis/MemorySSAUpdater.cpp
index 37cea287284cd..5acaf5939aca8 100644
--- a/llvm/lib/Analysis/MemorySSAUpdater.cpp
+++ b/llvm/lib/Analysis/MemorySSAUpdater.cpp
@@ -776,7 +776,7 @@ void MemorySSAUpdater::updateForClonedLoop(const LoopBlocksRPO &LoopBlocks,
ArrayRef<BasicBlock *> ExitBlocks,
const ValueToValueMapTy &VMap,
bool IgnoreIncomingWithNoClones) {
- SmallSetVector<BasicBlock *, 16> Blocks(
+ SmallSetVector<BasicBlock *> Blocks(
llvm::from_range, concat<BasicBlock *const>(LoopBlocks, ExitBlocks));
auto IsInClonedRegion = [&](BasicBlock *BB) { return Blocks.contains(BB); };
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
index eb5ebd85d1b9e..1c72032e1a088 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
@@ -374,7 +374,7 @@ class DwarfDebug : public DebugHandlerBase {
/// This is a collection of subprogram MDNodes that are processed to
/// create DIEs.
- SmallSetVector<const DISubprogram *, 16> ProcessedSPNodes;
+ SmallSetVector<const DISubprogram *> ProcessedSPNodes;
/// Map function-local imported entities to their parent local scope
/// (either DILexicalBlock or DISubprogram) for a processed function
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index c2145da88e1d7..b4d3b3481ac9d 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -183,7 +183,7 @@ class GlobalMergeImpl {
void collectUsedGlobalVariables(Module &M, StringRef Name);
/// Keep track of the GlobalVariable that must not be merged away
- SmallSetVector<const GlobalVariable *, 16> MustKeepGlobalVariables;
+ SmallSetVector<const GlobalVariable *> MustKeepGlobalVariables;
public:
GlobalMergeImpl(const TargetMachine *TM, GlobalMergeOptions Opt)
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index f3682a2e24808..99cb1ce81e38d 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -106,7 +106,7 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
/// This is the map from original register to a set containing all its
/// siblings. To hoist a spill to another BB, we need to find out a live
/// sibling there and use it as the source of the new spill.
- DenseMap<Register, SmallSetVector<Register, 16>> Virt2SiblingsMap;
+ DenseMap<Register, SmallSetVector<Register>> Virt2SiblingsMap;
bool isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
MachineBasicBlock &BB, Register &LiveReg);
@@ -1536,7 +1536,7 @@ bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
return false;
}
Register OrigReg = OrigLI.reg();
- SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg];
+ SmallSetVector<Register> &Siblings = Virt2SiblingsMap[OrigReg];
assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI");
for (const Register &SibReg : Siblings) {
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index a748150d98c64..3f8127536ffa1 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -367,7 +367,7 @@ class BlockChain {
class MachineBlockPlacement {
/// A type for a block filter set.
- using BlockFilterSet = SmallSetVector<const MachineBasicBlock *, 16>;
+ using BlockFilterSet = SmallSetVector<const MachineBasicBlock *>;
/// Pair struct containing basic block and taildup profitability
struct BlockAndTailDupResult {
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 4cba3dceff134..5bb42fce60edc 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -46,7 +46,7 @@ class ProcessImplicitDefs {
const TargetRegisterInfo *TRI = nullptr;
MachineRegisterInfo *MRI = nullptr;
- SmallSetVector<MachineInstr *, 16> WorkList;
+ SmallSetVector<MachineInstr *> WorkList;
void processImplicitDef(MachineInstr *MI);
bool canTurnIntoImplicitDef(MachineInstr *MI);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f94c861200f20..32ac9a308994d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1818,7 +1818,7 @@ bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
if (!N->use_empty())
return false;
- SmallSetVector<SDNode *, 16> Nodes;
+ SmallSetVector<SDNode *> Nodes;
Nodes.insert(N);
do {
N = Nodes.pop_back_val();
@@ -1890,7 +1890,7 @@ void DAGCombiner::Run(CombineLevel AtLevel) {
// If this combine is running after legalizing the DAG, re-legalize any
// nodes pulled off the worklist.
if (LegalDAG) {
- SmallSetVector<SDNode *, 16> UpdatedNodes;
+ SmallSetVector<SDNode *> UpdatedNodes;
bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
for (SDNode *LN : UpdatedNodes)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 15d82359e8682..6c26f086c4a55 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -95,7 +95,7 @@ class SelectionDAGLegalize {
SmallPtrSetImpl<SDNode *> &LegalizedNodes;
/// A set of all the nodes updated during legalization.
- SmallSetVector<SDNode *, 16> *UpdatedNodes;
+ SmallSetVector<SDNode *> *UpdatedNodes;
EVT getSetCCResultType(EVT VT) const {
return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
@@ -106,7 +106,7 @@ class SelectionDAGLegalize {
public:
SelectionDAGLegalize(SelectionDAG &DAG,
SmallPtrSetImpl<SDNode *> &LegalizedNodes,
- SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
+ SmallSetVector<SDNode *> *UpdatedNodes = nullptr)
: TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
@@ -6348,7 +6348,7 @@ void SelectionDAG::Legalize() {
}
bool SelectionDAG::LegalizeOp(SDNode *N,
- SmallSetVector<SDNode *, 16> &UpdatedNodes) {
+ SmallSetVector<SDNode *> &UpdatedNodes) {
SmallPtrSet<SDNode *, 16> LegalizedNodes;
SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 4ed6d00416fe6..50e47685b0e70 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -589,12 +589,13 @@ namespace {
/// recomputes their ready state.
class NodeUpdateListener : public SelectionDAG::DAGUpdateListener {
DAGTypeLegalizer &DTL;
- SmallSetVector<SDNode*, 16> &NodesToAnalyze;
+ SmallSetVector<SDNode *> &NodesToAnalyze;
+
public:
explicit NodeUpdateListener(DAGTypeLegalizer &dtl,
- SmallSetVector<SDNode*, 16> &nta)
- : SelectionDAG::DAGUpdateListener(dtl.getDAG()),
- DTL(dtl), NodesToAnalyze(nta) {}
+ SmallSetVector<SDNode *> &nta)
+ : SelectionDAG::DAGUpdateListener(dtl.getDAG()), DTL(dtl),
+ NodesToAnalyze(nta) {}
void NodeDeleted(SDNode *N, SDNode *E) override {
assert(N->getNodeId() != DAGTypeLegalizer::ReadyToProcess &&
@@ -641,7 +642,7 @@ void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) {
// Anything that used the old node should now use the new one. Note that this
// can potentially cause recursive merging.
- SmallSetVector<SDNode*, 16> NodesToAnalyze;
+ SmallSetVector<SDNode *> NodesToAnalyze;
NodeUpdateListener NUL(*this, NodesToAnalyze);
do {
diff --git a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
index b7a9464c6661c..ee86f8ba3fdb2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
@@ -589,7 +589,7 @@ lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
LLVM_DEBUG(dbgs() << "Deciding how to lower GC Pointers:\n");
// List of unique lowered GC Pointer values.
- SmallSetVector<SDValue, 16> LoweredGCPtrs;
+ SmallSetVector<SDValue> LoweredGCPtrs;
// Map lowered GC Pointer value to the index in above vector
DenseMap<SDValue, unsigned> GCPtrIndexMap;
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 32cae27489c39..2e45067e24f6f 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -153,7 +153,7 @@ class ShrinkWrapImpl {
/// Entry block.
const MachineBasicBlock *Entry = nullptr;
- using SetOfRegs = SmallSetVector<unsigned, 16>;
+ using SetOfRegs = SmallSetVector<unsigned>;
/// Registers that need to be saved for the current function.
mutable SetOfRegs CurrentCSRs;
diff --git a/llvm/lib/CodeGen/SjLjEHPrepare.cpp b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
index 7e86a013b1779..59aaa3d9de0a4 100644
--- a/llvm/lib/CodeGen/SjLjEHPrepare.cpp
+++ b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
@@ -382,7 +382,7 @@ void SjLjEHPrepareImpl::lowerAcrossUnwindEdges(Function &F,
bool SjLjEHPrepareImpl::setupEntryBlockAndCallSites(Function &F) {
SmallVector<ReturnInst *, 16> Returns;
SmallVector<InvokeInst *, 16> Invokes;
- SmallSetVector<LandingPadInst *, 16> LPads;
+ SmallSetVector<LandingPadInst *> LPads;
// Look through the terminators of the basic blocks to find invokes.
for (BasicBlock &BB : F)
diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp
index d96c5d18a0ae3..8ab8c41ddb4d0 100644
--- a/llvm/lib/Linker/IRMover.cpp
+++ b/llvm/lib/Linker/IRMover.cpp
@@ -1187,7 +1187,7 @@ Error IRLinker::linkModuleFlagsMetadata() {
// First build a map of the existing module flags and requirements.
DenseMap<MDString *, std::pair<MDNode *, unsigned>> Flags;
- SmallSetVector<MDNode *, 16> Requirements;
+ SmallSetVector<MDNode *> Requirements;
SmallVector<unsigned, 0> Mins;
DenseSet<MDString *> SeenMin;
for (unsigned I = 0, E = DstModFlags->getNumOperands(); I != E; ++I) {
@@ -1382,7 +1382,7 @@ Error IRLinker::linkModuleFlagsMetadata() {
break;
}
case Module::AppendUnique: {
- SmallSetVector<Metadata *, 16> Elts;
+ SmallSetVector<Metadata *> Elts;
MDTuple *DstValue = ensureDistinctOp(cast<MDNode>(DstOp->getOperand(2)));
MDNode *SrcValue = cast<MDNode>(SrcOp->getOperand(2));
Elts.insert(DstValue->op_begin(), DstValue->op_end());
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
index 6ce5aaeda8c82..bc400d054a6d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
@@ -72,9 +72,9 @@ class HardwareUnitInfo {
/// the critical resource. This agreement results in shorter live ranges and
/// more regular HardwareUnit access patterns. SUs are prioritized based on
/// depth for top-down scheduling.
- SmallSetVector<SUnit *, 16> PrioritySUs;
+ SmallSetVector<SUnit *> PrioritySUs;
/// All the SUs in the region that consume this resource.
- SmallSetVector<SUnit *, 16> AllSUs;
+ SmallSetVector<SUnit *> AllSUs;
/// All the SUs for this HardwareUnit that have already been scheduled.
SmallVector<SUnit *, 16> ScheduledSUs;
/// The total number of busy cycles for this HardwareUnit for a given region.
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
index c72b40e14ee0e..96434240d7367 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
@@ -118,17 +118,17 @@ class SIOptimizeVGPRLiveRange {
void collectElseRegionBlocks(MachineBasicBlock *Flow,
MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &) const;
+ SmallSetVector<MachineBasicBlock *> &) const;
void
collectCandidateRegisters(MachineBasicBlock *If, MachineBasicBlock *Flow,
MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks,
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks,
SmallVectorImpl<Register> &CandidateRegs) const;
void collectWaterfallCandidateRegisters(
MachineBasicBlock *LoopHeader, MachineBasicBlock *LoopEnd,
- SmallSetVector<Register, 16> &CandidateRegs,
+ SmallSetVector<Register> &CandidateRegs,
SmallSetVector<MachineBasicBlock *, 2> &Blocks,
SmallVectorImpl<MachineInstr *> &Instructions) const;
@@ -141,12 +141,11 @@ class SIOptimizeVGPRLiveRange {
void updateLiveRangeInElseRegion(
Register Reg, Register NewReg, MachineBasicBlock *Flow,
MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks) const;
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks) const;
- void
- optimizeLiveRange(Register Reg, MachineBasicBlock *If,
- MachineBasicBlock *Flow, MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks) const;
+ void optimizeLiveRange(Register Reg, MachineBasicBlock *If,
+ MachineBasicBlock *Flow, MachineBasicBlock *Endif,
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks) const;
void optimizeWaterfallLiveRange(
Register Reg, MachineBasicBlock *LoopHeader,
@@ -219,7 +218,7 @@ bool SIOptimizeVGPRLiveRange::isLiveIntoMBB(
void SIOptimizeVGPRLiveRange::collectElseRegionBlocks(
MachineBasicBlock *Flow, MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &Blocks) const {
+ SmallSetVector<MachineBasicBlock *> &Blocks) const {
assert(Flow != Endif);
MachineBasicBlock *MBB = Endif;
@@ -259,7 +258,7 @@ void SIOptimizeVGPRLiveRange::findNonPHIUsesInBlock(
/// the whole THEN region.
void SIOptimizeVGPRLiveRange::collectCandidateRegisters(
MachineBasicBlock *If, MachineBasicBlock *Flow, MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks,
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks,
SmallVectorImpl<Register> &CandidateRegs) const {
SmallSet<Register, 8> KillsInElse;
@@ -363,7 +362,7 @@ void SIOptimizeVGPRLiveRange::collectCandidateRegisters(
/// before.
void SIOptimizeVGPRLiveRange::collectWaterfallCandidateRegisters(
MachineBasicBlock *LoopHeader, MachineBasicBlock *LoopEnd,
- SmallSetVector<Register, 16> &CandidateRegs,
+ SmallSetVector<Register> &CandidateRegs,
SmallSetVector<MachineBasicBlock *, 2> &Blocks,
SmallVectorImpl<MachineInstr *> &Instructions) const {
@@ -498,7 +497,7 @@ void SIOptimizeVGPRLiveRange::updateLiveRangeInThenRegion(
void SIOptimizeVGPRLiveRange::updateLiveRangeInElseRegion(
Register Reg, Register NewReg, MachineBasicBlock *Flow,
MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks) const {
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks) const {
LiveVariables::VarInfo &NewVarInfo = LV->getVarInfo(NewReg);
LiveVariables::VarInfo &OldVarInfo = LV->getVarInfo(Reg);
@@ -525,7 +524,7 @@ void SIOptimizeVGPRLiveRange::updateLiveRangeInElseRegion(
void SIOptimizeVGPRLiveRange::optimizeLiveRange(
Register Reg, MachineBasicBlock *If, MachineBasicBlock *Flow,
MachineBasicBlock *Endif,
- SmallSetVector<MachineBasicBlock *, 16> &ElseBlocks) const {
+ SmallSetVector<MachineBasicBlock *> &ElseBlocks) const {
// Insert a new PHI, marking the value from the THEN region being
// undef.
LLVM_DEBUG(dbgs() << "Optimizing " << printReg(Reg, TRI) << '\n');
@@ -740,7 +739,7 @@ bool SIOptimizeVGPRLiveRange::run(MachineFunction &MF) {
if (!MDT->dominates(&MBB, IfTarget) || !MDT->dominates(IfTarget, Endif))
continue;
- SmallSetVector<MachineBasicBlock *, 16> ElseBlocks;
+ SmallSetVector<MachineBasicBlock *> ElseBlocks;
SmallVector<Register> CandidateRegs;
LLVM_DEBUG(dbgs() << "Checking IF-ELSE-ENDIF: "
@@ -765,7 +764,7 @@ bool SIOptimizeVGPRLiveRange::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "Checking Waterfall loop: "
<< printMBBReference(*LoopHeader) << '\n');
- SmallSetVector<Register, 16> CandidateRegs;
+ SmallSetVector<Register> CandidateRegs;
SmallVector<MachineInstr *, 16> Instructions;
SmallSetVector<MachineBasicBlock *, 2> Blocks;
diff --git a/llvm/lib/Target/DirectX/DXILResourceAccess.cpp b/llvm/lib/Target/DirectX/DXILResourceAccess.cpp
index 70f5407aeadcf..a69a39ffc48aa 100644
--- a/llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+++ b/llvm/lib/Target/DirectX/DXILResourceAccess.cpp
@@ -975,7 +975,7 @@ struct AccessIndices {
// - GetPtrIdx is the index of dx.resource.getpointer
// - HandleIdx is the index of dx.resource.handlefrom.*
static AccessIndices
-getAccessIndices(Instruction *I, SmallSetVector<Instruction *, 16> &DeadInsts,
+getAccessIndices(Instruction *I, SmallSetVector<Instruction *> &DeadInsts,
SmallDenseMap<PHINode *, PHINode *> &VisitedPhis) {
if (auto *II = dyn_cast<IntrinsicInst>(I)) {
if (llvm::is_contained(HandleIntrins, II->getIntrinsicID())) {
@@ -1073,7 +1073,7 @@ getAccessIndices(Instruction *I, SmallSetVector<Instruction *, 16> &DeadInsts,
static void
replaceHandleWithIndices(Instruction *Ptr, IntrinsicInst *OldHandle,
- SmallSetVector<Instruction *, 16> &DeadInsts,
+ SmallSetVector<Instruction *> &DeadInsts,
SmallDenseMap<PHINode *, PHINode *> &VisitedPhis) {
auto AccessIdx = getAccessIndices(Ptr, DeadInsts, VisitedPhis);
assert(AccessIdx.hasHandleIdx() &&
@@ -1115,7 +1115,7 @@ replaceHandleWithIndices(Instruction *Ptr, IntrinsicInst *OldHandle,
//
// Returns true if any changes are made.
static bool legalizeResourceHandles(Function &F, DXILResourceTypeMap &DRTM) {
- SmallSetVector<Instruction *, 16> DeadInsts;
+ SmallSetVector<Instruction *> DeadInsts;
SmallDenseMap<PHINode *, PHINode *> VisitedPhis;
for (BasicBlock &BB : make_early_inc_range(F)) {
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index e1c829833e04a..29dd422a74f26 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -745,11 +745,11 @@ class X86LowerAMXCast {
bool transformAMXCast(IntrinsicInst *AMXCast);
bool transformAllAMXCast();
bool optimizeAMXCastFromPhi(IntrinsicInst *CI, PHINode *PN,
- SmallSetVector<Instruction *, 16> &DeadInst);
+ SmallSetVector<Instruction *> &DeadInst);
};
static bool DCEInstruction(Instruction *I,
- SmallSetVector<Instruction *, 16> &WorkList,
+ SmallSetVector<Instruction *> &WorkList,
const TargetLibraryInfo *TLI) {
if (isInstructionTriviallyDead(I, TLI)) {
salvageDebugInfo(*I);
@@ -788,8 +788,7 @@ static bool DCEInstruction(Instruction *I,
/// All the related PHI nodes can be replaced by new PHI nodes with type A.
/// The uses of \p CI can be changed to the new PHI node corresponding to \p PN.
bool X86LowerAMXCast::optimizeAMXCastFromPhi(
- IntrinsicInst *CI, PHINode *PN,
- SmallSetVector<Instruction *, 16> &DeadInst) {
+ IntrinsicInst *CI, PHINode *PN, SmallSetVector<Instruction *> &DeadInst) {
IRBuilder<> Builder(CI);
Value *Src = CI->getOperand(0);
Type *SrcTy = Src->getType(); // Type B
@@ -1099,7 +1098,7 @@ bool X86LowerAMXCast::combineAMXcast(TargetLibraryInfo *TLI) {
SmallVector<Instruction *, 8> Vec2TileInsts;
SmallVector<Instruction *, 8> Tile2VecInsts;
SmallVector<Instruction *, 8> PhiCastWorkList;
- SmallSetVector<Instruction *, 16> DeadInst;
+ SmallSetVector<Instruction *> DeadInst;
for (BasicBlock &BB : Func) {
for (Instruction &I : BB) {
Value *Vec;
diff --git a/llvm/lib/Transforms/IPO/AlwaysInliner.cpp b/llvm/lib/Transforms/IPO/AlwaysInliner.cpp
index 1bdefb25b8dfb..c79bf0869d9c0 100644
--- a/llvm/lib/Transforms/IPO/AlwaysInliner.cpp
+++ b/llvm/lib/Transforms/IPO/AlwaysInliner.cpp
@@ -40,7 +40,7 @@ bool AlwaysInlineImpl(
function_ref<AAResults &(Function &)> GetAAR,
function_ref<TargetTransformInfo &(Function &)> GetTTI,
function_ref<const TargetLibraryInfo &(Function &)> GetTLI) {
- SmallSetVector<CallBase *, 16> Calls;
+ SmallSetVector<CallBase *> Calls;
bool Changed = false;
SmallVector<Function *, 16> InlinedComdatFunctions;
SmallVector<Function *, 4> NeedFlattening;
diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
index 7bf628ce27fa8..9793d43ded4ed 100644
--- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
@@ -1580,7 +1580,7 @@ struct OpenMPOpt {
OMPRTL_omp_get_partition_place_nums};
// Global-tid is handled separately.
- SmallSetVector<Value *, 16> GTIdArgs;
+ SmallSetVector<Value *> GTIdArgs;
collectGlobalThreadIdArguments(GTIdArgs);
LLVM_DEBUG(dbgs() << TAG << "Found " << GTIdArgs.size()
<< " global thread ID arguments\n");
@@ -1989,7 +1989,7 @@ struct OpenMPOpt {
}
/// Collect arguments that represent the global thread id in \p GTIdArgs.
- void collectGlobalThreadIdArguments(SmallSetVector<Value *, 16> >IdArgs) {
+ void collectGlobalThreadIdArguments(SmallSetVector<Value *> >IdArgs) {
// TODO: Below we basically perform a fixpoint iteration with a pessimistic
// initialization. We could define an AbstractAttribute instead and
// run the Attributor here once it can be run as an SCC pass.
@@ -2887,7 +2887,7 @@ struct AAExecutionDomainFunction : public AAExecutionDomain {
Changed = ChangeStatus::CHANGED;
SmallVector<CallBase *> Worklist(ED.AlignedBarriers.begin(),
ED.AlignedBarriers.end());
- SmallSetVector<CallBase *, 16> Visited;
+ SmallSetVector<CallBase *> Visited;
while (!Worklist.empty()) {
CallBase *LastCB = Worklist.pop_back_val();
if (!Visited.insert(LastCB))
@@ -3097,7 +3097,7 @@ struct AAExecutionDomainFunction : public AAExecutionDomain {
DenseMap<const BasicBlock *, ExecutionDomainTy> BEDMap;
DenseMap<PointerIntPair<const CallBase *, 1, Direction>, ExecutionDomainTy>
CEDMap;
- SmallSetVector<CallBase *, 16> AlignedBarriers;
+ SmallSetVector<CallBase *> AlignedBarriers;
ReversePostOrderTraversal<Function *> *RPOT = nullptr;
@@ -3458,7 +3458,7 @@ ChangeStatus AAExecutionDomainFunction::updateImpl(Attributor &A) {
// Propagate (non-aligned) sync instruction effects backwards until the
// entry is hit or an aligned barrier.
- SmallSetVector<BasicBlock *, 16> Visited;
+ SmallSetVector<BasicBlock *> Visited;
while (!SyncInstWorklist.empty()) {
Instruction *SyncInst = SyncInstWorklist.pop_back_val();
Instruction *CurInst = SyncInst;
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 214262a95e41a..de730207a9e82 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -1243,7 +1243,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
};
SmallVector<ShadowOriginAndInsertPoint, 16> InstrumentationList;
DenseMap<const DILocation *, int> LazyWarningDebugLocationCount;
- SmallSetVector<AllocaInst *, 16> AllocaSet;
+ SmallSetVector<AllocaInst *> AllocaSet;
SmallVector<std::pair<IntrinsicInst *, AllocaInst *>, 16> LifetimeStartList;
SmallVector<StoreInst *, 16> StoreList;
int64_t SplittableBlocksCount = 0;
diff --git a/llvm/lib/Transforms/Scalar/ADCE.cpp b/llvm/lib/Transforms/Scalar/ADCE.cpp
index fba8dc22a5c98..5815bef9ee466 100644
--- a/llvm/lib/Transforms/Scalar/ADCE.cpp
+++ b/llvm/lib/Transforms/Scalar/ADCE.cpp
@@ -115,7 +115,7 @@ class AggressiveDeadCodeElimination {
SmallPtrSet<const Metadata *, 32> AliveScopes;
/// Set of blocks with not known to have live terminators.
- SmallSetVector<BasicBlock *, 16> BlocksWithDeadTerminators;
+ SmallSetVector<BasicBlock *> BlocksWithDeadTerminators;
/// The set of blocks which we have determined whose control
/// dependence sources must be live and which have not had
diff --git a/llvm/lib/Transforms/Scalar/DCE.cpp b/llvm/lib/Transforms/Scalar/DCE.cpp
index 2ad46130dc945..86f7b35fac215 100644
--- a/llvm/lib/Transforms/Scalar/DCE.cpp
+++ b/llvm/lib/Transforms/Scalar/DCE.cpp
@@ -53,7 +53,7 @@ RedundantDbgInstEliminationPass::run(Function &F, FunctionAnalysisManager &AM) {
//
static bool DCEInstruction(Instruction *I,
- SmallSetVector<Instruction *, 16> &WorkList,
+ SmallSetVector<Instruction *> &WorkList,
const TargetLibraryInfo *TLI) {
if (isInstructionTriviallyDead(I, TLI)) {
if (!DebugCounter::shouldExecute(DCECounter))
@@ -88,7 +88,7 @@ static bool DCEInstruction(Instruction *I,
static bool eliminateDeadCode(Function &F, TargetLibraryInfo *TLI) {
bool MadeChange = false;
- SmallSetVector<Instruction *, 16> WorkList;
+ SmallSetVector<Instruction *> WorkList;
// Iterate over the original function, only adding insts to the worklist
// if they actually need to be revisited. This avoids having to pre-init
// the worklist with the entire function's worth of instructions.
diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
index 1949d52302e1e..02ef1f9af509b 100644
--- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
@@ -1103,7 +1103,7 @@ struct TransformDFA {
DuplicateBlockMap DuplicateMap;
DefMap NewDefs;
- SmallSetVector<BasicBlock *, 16> BlocksToClean;
+ SmallSetVector<BasicBlock *> BlocksToClean;
BlocksToClean.insert_range(successors(SwitchBlock));
for (const ThreadingPath &TPath : SwitchPaths->getThreadingPaths()) {
@@ -1132,7 +1132,7 @@ struct TransformDFA {
/// the predecessors, and phis in the successor blocks.
void createExitPath(DefMap &NewDefs, const ThreadingPath &Path,
DuplicateBlockMap &DuplicateMap,
- SmallSetVector<BasicBlock *, 16> &BlocksToClean,
+ SmallSetVector<BasicBlock *> &BlocksToClean,
DomTreeUpdater *DTU) {
APInt NextState = Path.getExitValue();
const BasicBlock *Determinator = Path.getDeterminatorBB();
diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
index ad3b123f3327c..65b4d4e19eb03 100644
--- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
@@ -361,7 +361,7 @@ static std::optional<EstimatedUnrollCost> analyzeLoopUnrollCost(
return std::nullopt;
}
- SmallSetVector<BasicBlock *, 16> BBWorklist;
+ SmallSetVector<BasicBlock *> BBWorklist;
SmallSetVector<std::pair<BasicBlock *, BasicBlock *>, 4> ExitWorklist;
DenseMap<Value *, Value *> SimplifiedValues;
SmallVector<std::pair<Value *, Value *>, 4> SimplifiedInputValues;
diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
index 6ac5637e0c9bd..f606cfa3eeb0d 100644
--- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
+++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
@@ -2832,7 +2832,7 @@ static bool insertParsePoints(Function &F, DominatorTree &DT,
// Do all the fixups of the original live variables to their relocated selves.
// A SmallSetVector is used to collect live variables while retaining the
// order in which we add them, which is important for reproducible tests.
- SmallSetVector<Value *, 16> Live;
+ SmallSetVector<Value *> Live;
for (const PartiallyConstructedSafepointRecord &Info : Records) {
// We can't simply save the live set from the original insertion. One of
// the live values might be the result of a call which needs a safepoint.
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index 9178f8fb6ac9f..bb69dfc6315b9 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -188,7 +188,7 @@ class SROA {
/// directly promoted. Finally, each time we rewrite a use of an alloca other
/// the one being actively rewritten, we add it back onto the list if not
/// already present to ensure it is re-visited.
- SmallSetVector<AllocaInst *, 16> Worklist;
+ SmallSetVector<AllocaInst *> Worklist;
/// A collection of instructions to delete.
/// We try to batch deletions to simplify code and make things a bit more
@@ -203,7 +203,7 @@ class SROA {
///
/// Note that we have to be very careful to clear allocas out of this list in
/// the event they are deleted.
- SmallSetVector<AllocaInst *, 16> PostPromotionWorklist;
+ SmallSetVector<AllocaInst *> PostPromotionWorklist;
/// A collection of alloca instructions we can directly promote.
SetVector<AllocaInst *, SmallVector<AllocaInst *>,
@@ -1768,7 +1768,7 @@ static void speculatePHINodeLoads(IRBuilderTy &IRB, PHINode &PN) {
/// Move a store through a pointer PHI onto each of the PHI's incoming edges.
/// Returns whether this required modifying the CFG.
static bool rewritePHINodeStore(PHINode &PN, StoreInst &SI, DomTreeUpdater &DTU,
- SmallSetVector<AllocaInst *, 16> &Worklist) {
+ SmallSetVector<AllocaInst *> &Worklist) {
LLVM_DEBUG(dbgs() << " original: " << PN << "\n"
<< " " << SI << "\n");
diff --git a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
index 310ef7c4f3548..ecbc233fe2158 100644
--- a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+++ b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
@@ -1582,7 +1582,7 @@ static void buildClonedLoops(Loop &OrigL, ArrayRef<BasicBlock *> ExitBlocks,
// cloned blocks out of the original loop. While not all of these will
// necessarily be in the cloned loop, it is enough to establish that they
// aren't in unreachable cycles, etc.
- SmallSetVector<BasicBlock *, 16> ClonedLoopBlocks;
+ SmallSetVector<BasicBlock *> ClonedLoopBlocks;
for (auto *BB : OrigL.blocks())
if (auto *ClonedBB = cast_or_null<BasicBlock>(VMap.lookup(BB)))
ClonedLoopBlocks.insert(ClonedBB);
diff --git a/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp b/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
index 65bff2b878bda..0b62ddc1956b9 100644
--- a/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
+++ b/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
@@ -356,7 +356,7 @@ bool llvm::SplitIndirectBrCriticalEdges(Function &F,
// Check whether the function has any indirectbrs, and collect which blocks
// they may jump to. Since most functions don't have indirect branches,
// this lowers the common case's overhead to O(Blocks) instead of O(Edges).
- SmallSetVector<BasicBlock *, 16> Targets;
+ SmallSetVector<BasicBlock *> Targets;
for (auto &BB : F) {
if (isa<IndirectBrInst>(BB.getTerminator()))
Targets.insert_range(successors(&BB));
diff --git a/llvm/lib/Transforms/Utils/LCSSA.cpp b/llvm/lib/Transforms/Utils/LCSSA.cpp
index 415c6baff20d7..03aeeaba23f01 100644
--- a/llvm/lib/Transforms/Utils/LCSSA.cpp
+++ b/llvm/lib/Transforms/Utils/LCSSA.cpp
@@ -86,7 +86,7 @@ formLCSSAForInstructionsImpl(SmallVectorImpl<Instruction *> &Worklist,
SmallVectorImpl<PHINode *> *InsertedPHIs,
LoopExitBlocksTy &LoopExitBlocks) {
SmallVector<Use *, 16> UsesToRewrite;
- SmallSetVector<PHINode *, 16> LocalPHIsToRemove;
+ SmallSetVector<PHINode *> LocalPHIsToRemove;
PredIteratorCache PredCache;
bool Changed = false;
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 78c632069af74..c9c0dc614d1a1 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -653,11 +653,10 @@ bool llvm::RecursivelyDeleteDeadPHINode(
return false;
}
-static bool
-simplifyAndDCEInstruction(Instruction *I,
- SmallSetVector<Instruction *, 16> &WorkList,
- const DataLayout &DL,
- const TargetLibraryInfo *TLI) {
+static bool simplifyAndDCEInstruction(Instruction *I,
+ SmallSetVector<Instruction *> &WorkList,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
if (isInstructionTriviallyDead(I, TLI)) {
salvageDebugInfo(*I);
@@ -725,7 +724,7 @@ bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB,
AssertingVH<Instruction> TerminatorVH(&BB->back());
#endif
- SmallSetVector<Instruction *, 16> WorkList;
+ SmallSetVector<Instruction *> WorkList;
// Iterate over the original function, only adding insts to the worklist
// if they actually need to be revisited. This avoids having to pre-init
// the worklist with the entire function's worth of instructions.
diff --git a/llvm/lib/Transforms/Utils/ModuleUtils.cpp b/llvm/lib/Transforms/Utils/ModuleUtils.cpp
index 71e9c70cbf9a5..886e8f4237c0c 100644
--- a/llvm/lib/Transforms/Utils/ModuleUtils.cpp
+++ b/llvm/lib/Transforms/Utils/ModuleUtils.cpp
@@ -124,7 +124,7 @@ void llvm::transformGlobalDtors(Module &M, const GlobalCtorTransformFn &Fn) {
}
static void collectUsedGlobals(GlobalVariable *GV,
- SmallSetVector<Constant *, 16> &Init) {
+ SmallSetVector<Constant *> &Init) {
if (!GV || !GV->hasInitializer())
return;
@@ -136,7 +136,7 @@ static void collectUsedGlobals(GlobalVariable *GV,
static void appendToUsedList(Module &M, StringRef Name, ArrayRef<GlobalValue *> Values) {
GlobalVariable *GV = M.getGlobalVariable(Name);
- SmallSetVector<Constant *, 16> Init;
+ SmallSetVector<Constant *> Init;
collectUsedGlobals(GV, Init);
if (GV)
GV->eraseFromParent();
@@ -169,7 +169,7 @@ static void removeFromUsedList(Module &M, StringRef Name,
if (!GV)
return;
- SmallSetVector<Constant *, 16> Init;
+ SmallSetVector<Constant *> Init;
collectUsedGlobals(GV, Init);
Type *ArrayEltTy = cast<ArrayType>(GV->getValueType())->getElementType();
diff --git a/llvm/lib/Transforms/Utils/SCCPSolver.cpp b/llvm/lib/Transforms/Utils/SCCPSolver.cpp
index 114389ff057a7..c41436b6497bc 100644
--- a/llvm/lib/Transforms/Utils/SCCPSolver.cpp
+++ b/llvm/lib/Transforms/Utils/SCCPSolver.cpp
@@ -613,7 +613,7 @@ class SCCPInstVisitor : public InstVisitor<SCCPInstVisitor> {
/// Worklist of instructions to re-visit. This only includes instructions
/// in blocks that have already been visited at least once.
- SmallSetVector<Instruction *, 16> InstWorkList;
+ SmallSetVector<Instruction *> InstWorkList;
/// Current instruction while visiting a block for the first time, used to
/// avoid unnecessary instruction worklist insertions. Null if an instruction
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 7b31b2ec37a66..9ff68126a6f46 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1480,7 +1480,7 @@ bool SimplifyCFGOpt::foldValueComparisonIntoPredecessors(Instruction *TI,
bool Changed = false;
- SmallSetVector<BasicBlock *, 16> Preds(pred_begin(BB), pred_end(BB));
+ SmallSetVector<BasicBlock *> Preds(pred_begin(BB), pred_end(BB));
while (!Preds.empty()) {
BasicBlock *Pred = Preds.pop_back_val();
Instruction *PTI = Pred->getTerminator();
@@ -8572,7 +8572,7 @@ static bool mergeIdenticalBBs(ArrayRef<BasicBlock *> Candidates,
bool SimplifyCFGOpt::simplifyDuplicateSwitchArms(SwitchInst *SI,
DomTreeUpdater *DTU) {
// Collect candidate switch-arms top-down.
- SmallSetVector<BasicBlock *, 16> FilteredArms(
+ SmallSetVector<BasicBlock *> FilteredArms(
llvm::from_range,
make_filter_range(successors(SI), EqualBBWrapper::canBeMerged));
return mergeIdenticalBBs(FilteredArms.getArrayRef(), DTU);
@@ -8776,7 +8776,7 @@ static bool tryToMergeLandingPad(LandingPadInst *LPad, UncondBrInst *BI,
// We've found an identical block. Update our predecessors to take that
// path instead and make ourselves dead.
- SmallSetVector<BasicBlock *, 16> UniquePreds(pred_begin(BB), pred_end(BB));
+ SmallSetVector<BasicBlock *> UniquePreds(pred_begin(BB), pred_end(BB));
for (BasicBlock *Pred : UniquePreds) {
InvokeInst *II = cast<InvokeInst>(Pred->getTerminator());
assert(II->getNormalDest() != BB && II->getUnwindDest() == BB &&
@@ -8788,7 +8788,7 @@ static bool tryToMergeLandingPad(LandingPadInst *LPad, UncondBrInst *BI,
}
}
- SmallSetVector<BasicBlock *, 16> UniqueSuccs(succ_begin(BB), succ_end(BB));
+ SmallSetVector<BasicBlock *> UniqueSuccs(succ_begin(BB), succ_end(BB));
for (BasicBlock *Succ : UniqueSuccs) {
Succ->removePredecessor(BB);
if (DTU)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index b76a213957eeb..263b368418cd0 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -16494,7 +16494,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
E->isAltShuffle() ? (unsigned)Instruction::ShuffleVector : E->getOpcode();
if (E->CombinedOp != TreeEntry::NotCombinedOp)
ShuffleOrOp = E->CombinedOp;
- SmallSetVector<Value *, 16> UniqueValues;
+ SmallSetVector<Value *> UniqueValues;
SmallVector<unsigned, 16> UniqueIndexes;
for (auto [Idx, V] : enumerate(VL))
if (UniqueValues.insert(V))
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index d16a3a1535cb7..27d1dd79fea9a 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -4268,7 +4268,7 @@ bool VectorCombine::foldShuffleChainsToReduce(Instruction &I) {
// Collect the chain, building Nodes in postorder. Bail if the chain is empty
// or exceeds MaxChainNodes.
constexpr unsigned MaxChainNodes = 32;
- SmallSetVector<Value *, 16> Nodes;
+ SmallSetVector<Value *> Nodes;
SmallSetVector<Value *, 4> Sources;
unsigned NumVisited = 0;
auto AddSource = [&](Value *V) {
diff --git a/llvm/unittests/ADT/SetVectorTest.cpp b/llvm/unittests/ADT/SetVectorTest.cpp
index 6230472553c38..eec1f50c186bb 100644
--- a/llvm/unittests/ADT/SetVectorTest.cpp
+++ b/llvm/unittests/ADT/SetVectorTest.cpp
@@ -106,3 +106,13 @@ TEST(SmallSetVector, CtorRange) {
SmallSetVector<unsigned, 4> Set(llvm::from_range, Args);
EXPECT_THAT(Set, ::testing::ElementsAre(3, 1, 2));
}
+
+TEST(SetVector, CtorInitList) {
+ SetVector<unsigned> Set = {3, 1, 2, 1};
+ EXPECT_THAT(Set, ::testing::ElementsAre(3, 1, 2));
+}
+
+TEST(SmallSetVector, CtorInitList) {
+ SmallSetVector<unsigned> Set = {3, 1, 2, 1};
+ EXPECT_THAT(Set, ::testing::ElementsAre(3, 1, 2));
+}
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index b756582603ffd..7f77e7fd423f0 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2025,10 +2025,9 @@ void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
}
}
-static unsigned
-getConverterOperandID(const std::string &Name,
- SmallSetVector<CachedHashString, 16> &Table,
- bool &IsNew) {
+static unsigned getConverterOperandID(const std::string &Name,
+ SmallSetVector<CachedHashString> &Table,
+ bool &IsNew) {
IsNew = Table.insert(CachedHashString(Name));
unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();
@@ -2043,8 +2042,8 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
std::vector<std::unique_ptr<MatchableInfo>> &Infos,
bool HasMnemonicFirst, bool HasOptionalOperands,
raw_ostream &OS) {
- SmallSetVector<CachedHashString, 16> OperandConversionKinds;
- SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
+ SmallSetVector<CachedHashString> OperandConversionKinds;
+ SmallSetVector<CachedHashString> InstructionConversionKinds;
std::vector<std::vector<uint8_t>> ConversionTable;
// minimum is custom converter plus a operand index in parsed OperandVector
>From 4030f81f41b26d4b49f85bba12830e8801e6fdf1 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers at google.com>
Date: Thu, 17 Sep 2026 14:53:57 -0700
Subject: [PATCH 2/2] [CodeGen] Use SmallSetVector for getRegAllocationHints
Change TargetRegisterInfo::getRegAllocationHints and all target overrides
to accept SmallSetVector<MCPhysReg> &Hints instead of SmallVectorImpl,
structurally preventing duplicate register allocation hints while preserving
insertion order.
Assisted-by: Gemini
Link: #190139
Link: #193011
Link: #219007
Link: #224448
Link: #224451
Link: #224742
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 3 +-
llvm/lib/CodeGen/AllocationOrder.cpp | 10 ++--
llvm/lib/CodeGen/AllocationOrder.h | 8 ++--
llvm/lib/CodeGen/TargetRegisterInfo.cpp | 10 +---
.../Target/AArch64/AArch64RegisterInfo.cpp | 27 ++++++-----
llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 2 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 2 +-
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 8 ++--
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 2 +-
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 8 ++--
llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 10 ++--
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 2 +-
.../Target/SystemZ/SystemZRegisterInfo.cpp | 12 ++---
llvm/lib/Target/SystemZ/SystemZRegisterInfo.h | 2 +-
llvm/lib/Target/X86/X86RegisterInfo.cpp | 14 +++---
llvm/lib/Target/X86/X86RegisterInfo.h | 2 +-
.../unittests/CodeGen/AllocationOrderTest.cpp | 27 +++++++----
.../AArch64/AArch64RegisterInfoTest.cpp | 46 +++++++++++++++++++
20 files changed, 127 insertions(+), 78 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 4678773607377..edbfe5ae178b1 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -16,6 +16,7 @@
#define LLVM_CODEGEN_TARGETREGISTERINFO_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator_range.h"
@@ -837,7 +838,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// expect to see generic copy hints added.
virtual bool
getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM = nullptr,
const LiveRegMatrix *Matrix = nullptr) const;
diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp
index 6294b86b27c44..d67643b1bf08c 100644
--- a/llvm/lib/CodeGen/AllocationOrder.cpp
+++ b/llvm/lib/CodeGen/AllocationOrder.cpp
@@ -53,14 +53,14 @@ AllocationOrder AllocationOrder::create(Register VirtReg, const VirtRegMap &VRM,
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
const MachineRegisterInfo &MRI = MF.getRegInfo();
auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
+ // Get Hints.
+ SmallSetVector<MCPhysReg> Hints;
+ bool HardHints =
+ TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
// HintsAndCustomOrder holds Hints first followed by the custom order if the
// anti-hints reorders it.
- SmallVector<MCPhysReg, 16> HintsAndCustomOrder;
-
- // Get Hints.
- bool HardHints = TRI->getRegAllocationHints(
- VirtReg, Order, HintsAndCustomOrder, MF, &VRM, Matrix);
+ SmallVector<MCPhysReg, 16> HintsAndCustomOrder = Hints.takeVector();
const int NumHints = static_cast<int>(HintsAndCustomOrder.size());
// HintsAndCustomOrder only holds Hints (custom order is not added yet).
diff --git a/llvm/lib/CodeGen/AllocationOrder.h b/llvm/lib/CodeGen/AllocationOrder.h
index 7c61c01d9ea59..3553f884fbba5 100644
--- a/llvm/lib/CodeGen/AllocationOrder.h
+++ b/llvm/lib/CodeGen/AllocationOrder.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -108,10 +109,11 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
/// Create an AllocationOrder given the Hints, Order, and HardHints values.
/// Use the create method above - the ctor is for unittests.
- AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order,
+ AllocationOrder(SmallSetVector<MCPhysReg> &&Hints, ArrayRef<MCPhysReg> Order,
bool HardHints)
- : AllocationOrder(std::move(Hints), static_cast<int>(Hints.size()), Order,
- HardHints) {}
+ : HintsAndCustomOrder(Hints.takeVector()),
+ NumHints(static_cast<int>(HintsAndCustomOrder.size())), Order(Order),
+ IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {}
Iterator begin() const { return Iterator(*this, -NumHints); }
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 79b01d27d91a5..4d93ee844a5df 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -14,7 +14,6 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/CodeGen/LiveInterval.h"
@@ -399,7 +398,7 @@ float TargetRegisterInfo::getSpillWeightScaleFactor(
// Compute target-independent register allocator hints to help eliminate copies.
bool TargetRegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
+ SmallSetVector<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
@@ -408,7 +407,6 @@ bool TargetRegisterInfo::getRegAllocationHints(
if (!Hints_MRI)
return false;
- SmallSet<Register, 32> HintedRegs;
// First hint may be a target hint.
bool Skip = (Hints_MRI->first != 0);
for (auto Reg : Hints_MRI->second) {
@@ -422,10 +420,6 @@ bool TargetRegisterInfo::getRegAllocationHints(
if (VRM && Phys.isVirtual())
Phys = VRM->getPhys(Phys);
- // Don't add the same reg twice (Hints_MRI may contain multiple virtual
- // registers allocated to the same physreg).
- if (!HintedRegs.insert(Phys).second)
- continue;
// Check that Phys is a valid hint in VirtReg's register class.
if (!Phys.isPhysical())
continue;
@@ -438,7 +432,7 @@ bool TargetRegisterInfo::getRegAllocationHints(
continue;
// All clear, tell the register allocator to prefer this register.
- Hints.push_back(Phys.id());
+ Hints.insert(Phys);
}
return false;
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 7f22038c206b7..1672e6fdc1caa 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -1111,7 +1111,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
static bool HandleDestructivePredicateHint(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const VirtRegMap *VRM,
+ SmallSetVector<MCPhysReg> &Hints, const VirtRegMap *VRM,
const MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
const AArch64Subtarget &ST, const LiveRegMatrix *Matrix) {
const TargetRegisterClass *RegRC = MRI.getRegClass(VirtReg);
@@ -1150,15 +1150,17 @@ static bool HandleDestructivePredicateHint(
CSRs.insert(R);
}
- Hints.append(Order.begin(), Order.end());
+ Hints.insert_range(Order);
auto CanUseReg = [&](Register R) {
return !CSRs.contains(R) || !MRI.def_empty(R) || Matrix->isPhysRegUsed(R);
};
- llvm::stable_sort(Hints, [&](Register A, Register B) {
+ SmallVector<MCPhysReg, 16> SortedHints = Hints.takeVector();
+ llvm::stable_sort(SortedHints, [&](Register A, Register B) {
bool PrefA = (A != Op1Reg) && CanUseReg(A);
bool PrefB = (B != Op1Reg) && CanUseReg(B);
return PrefA && !PrefB;
});
+ Hints.insert_range(SortedHints);
return true;
}
@@ -1184,7 +1186,7 @@ static bool HandleDestructivePredicateHint(
// begins with $z24 (i.e. $z24_z25_z26_z27).
bool AArch64RegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
+ SmallSetVector<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
auto &ST = MF.getSubtarget<AArch64Subtarget>();
const AArch64InstrInfo *TII =
@@ -1219,7 +1221,7 @@ bool AArch64RegisterInfo::getRegAllocationHints(
PhysReg = getSubReg(PhysReg, MO.getSubReg());
if (PhysReg != R)
return false;
- Hints.push_back(R);
+ Hints.insert(R);
return true;
};
@@ -1260,8 +1262,7 @@ bool AArch64RegisterInfo::getRegAllocationHints(
return ConsiderOnlyHints;
if (!ST.hasSME() || !ST.isStreaming())
- return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
- VRM);
+ return ConsiderOnlyHints;
// The SVE calling convention preserves registers Z8-Z23. As a result, there
// are no ZPR2Strided or ZPR4Strided registers that do not overlap with the
@@ -1380,7 +1381,7 @@ bool AArch64RegisterInfo::getRegAllocationHints(
!Matrix->isPhysRegUsed(R);
};
if (all_of(seq(0U, TupleSize), IsFreeConsecutiveReg))
- Hints.push_back(Reg);
+ Hints.insert(Reg);
}
} else {
// At least copy already has a physical register assigned to its source.
@@ -1399,12 +1400,11 @@ bool AArch64RegisterInfo::getRegAllocationHints(
for (unsigned I = 0; I < StridedOrder.size(); ++I)
if (getSubReg(StridedOrder[I], AArch64::zsub0) == TargetStartReg)
- Hints.push_back(StridedOrder[I]);
+ Hints.insert(StridedOrder[I]);
}
if (!Hints.empty())
- return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints,
- MF, VRM);
+ return ConsiderOnlyHints;
}
}
@@ -1431,12 +1431,11 @@ bool AArch64RegisterInfo::getRegAllocationHints(
// Try to pick a tuple register for Dst with Src as a member.
for (MCPhysReg R : Order) {
if (getSubReg(R, Dst.getSubReg()) == SrcZPR)
- Hints.push_back(R);
+ Hints.insert(R);
}
}
- return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
- VRM);
+ return ConsiderOnlyHints;
}
unsigned AArch64RegisterInfo::getLocalAddressRegister(
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 5f6b0a2472b1a..6d5a9d1153c6d 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -138,7 +138,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
MachineFunction &MF) const override;
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 1aa423e1da647..d39e57a074e8f 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4239,7 +4239,7 @@ const int *SIRegisterInfo::getRegUnitPressureSets(MCRegUnit RegUnit) const {
bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
@@ -4266,7 +4266,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
if (PairedPhys)
// isLo(Paired) is implicitly true here from the API of
// getMatchingSuperReg.
- Hints.push_back(PairedPhys);
+ Hints.insert(PairedPhys);
return false;
}
case AMDGPURI::Size16: {
@@ -4281,7 +4281,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
// First prefer the paired physreg.
if (PairedPhys)
- Hints.push_back(PairedPhys);
+ Hints.insert(PairedPhys);
else {
// Add all the lo16 physregs.
// When the Paired operand has not yet been assigned a physreg it is
@@ -4293,7 +4293,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
continue;
if (AMDGPU::VGPR_16RegClass.contains(PhysReg) &&
!MRI.isReserved(PhysReg))
- Hints.push_back(PhysReg);
+ Hints.insert(PhysReg);
}
}
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index c5a4162fbb01c..55b1078102d5a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -375,7 +375,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
unsigned Idx) const override;
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 5496729bcb2b3..979c6c72a0704 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -358,7 +358,7 @@ static MCRegister getPairedGPR(MCRegister Reg, bool Odd,
// Resolve the RegPairEven / RegPairOdd register allocator hints.
bool ARMBaseRegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
+ SmallSetVector<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
std::pair<unsigned, Register> Hint = MRI.getRegAllocationHint(VirtReg);
@@ -374,7 +374,7 @@ bool ARMBaseRegisterInfo::getRegAllocationHints(
case ARMRI::RegLR:
TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
if (MRI.getRegClass(VirtReg)->contains(ARM::LR))
- Hints.push_back(ARM::LR);
+ Hints.insert(ARM::LR);
return false;
default:
return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
@@ -396,7 +396,7 @@ bool ARMBaseRegisterInfo::getRegAllocationHints(
// First prefer the paired physreg.
if (PairedPhys && is_contained(Order, PairedPhys))
- Hints.push_back(PairedPhys);
+ Hints.insert(PairedPhys);
// Then prefer even or odd registers.
for (MCPhysReg Reg : Order) {
@@ -406,7 +406,7 @@ bool ARMBaseRegisterInfo::getRegAllocationHints(
MCRegister Paired = getPairedGPR(Reg, !Odd, this);
if (!Paired || MRI.isReserved(Paired))
continue;
- Hints.push_back(Reg);
+ Hints.insert(Reg);
}
return false;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index 7a73680e637bc..fc9d6e45a7cf7 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -101,7 +101,7 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
MachineFunction &MF) const override;
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 80f678200f79a..08d7d57154991 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -536,7 +536,7 @@ bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
@@ -580,11 +580,11 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
// Ensure that the hint is a VSRp register.
if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
- Hints.push_back(HintReg);
+ Hints.insert(HintReg);
} else if (RegClass->contains(PPC::ACC0)) {
HintReg = PPC::ACC0 + (UACCPhys - PPC::UACC0);
if (HintReg >= PPC::ACC0 && HintReg <= PPC::ACC7)
- Hints.push_back(HintReg);
+ Hints.insert(HintReg);
}
}
break;
@@ -598,7 +598,7 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
"Expecting an ACC register for BUILD_UACC.");
Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
- Hints.push_back(HintReg);
+ Hints.insert(HintReg);
}
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 0c5b9d8b94233..5b4005bbc20c5 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -106,7 +106,7 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
// Similarly if UACC5 is assigned, we want to assign VSRp10, VSRp11
// to its inputs.
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index adc6eadee2e35..efe8084397473 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -999,7 +999,7 @@ float RISCVRegisterInfo::getSpillWeightScaleFactor(
// instruction.
bool RISCVRegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
+ SmallSetVector<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
@@ -1023,7 +1023,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
// Verify it's valid and available
if (RISCV::GPRRegClass.contains(TargetReg) &&
is_contained(Order, TargetReg))
- Hints.push_back(TargetReg.id());
+ Hints.insert(TargetReg.id());
}
// Second priority: Try to find consecutive register pairs in the allocation
@@ -1040,7 +1040,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
// Don't provide hints that are paired to a reserved register.
MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
if (WantOdd == IsOdd && !MRI->isReserved(Paired))
- Hints.push_back(PhysReg);
+ Hints.insert(PhysReg);
}
}
@@ -1062,7 +1062,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
// physical register is even (or vice versa), we should not add the hint.
if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg)) &&
!MO.getSubReg() && !VRRegMO.getSubReg()) {
- if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
+ if (!MRI->isReserved(PhysReg) && !Hints.contains(PhysReg))
TwoAddrHints.insert(PhysReg);
}
};
@@ -1190,7 +1190,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
for (MCPhysReg OrderReg : Order)
if (TwoAddrHints.count(OrderReg))
- Hints.push_back(OrderReg);
+ Hints.insert(OrderReg);
return BaseImplRetVal;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e94f5f0b4b364..a91115aef738c 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -151,7 +151,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index 177f2c50e4f01..7aa9483213bfa 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -55,7 +55,7 @@ static const TargetRegisterClass *getRC32(MachineOperand &MO,
// registers are copy hints (and therefore already in Hints), hint them
// first.
static void addHints(ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const TargetRegisterClass *RC,
const MachineRegisterInfo *MRI) {
SmallSet<unsigned, 4> CopyHints(llvm::from_range, Hints);
@@ -63,16 +63,16 @@ static void addHints(ArrayRef<MCPhysReg> Order,
for (MCPhysReg Reg : Order)
if (CopyHints.count(Reg) &&
RC->contains(Reg) && !MRI->isReserved(Reg))
- Hints.push_back(Reg);
+ Hints.insert(Reg);
for (MCPhysReg Reg : Order)
if (!CopyHints.count(Reg) &&
RC->contains(Reg) && !MRI->isReserved(Reg))
- Hints.push_back(Reg);
+ Hints.insert(Reg);
}
bool SystemZRegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
+ SmallSetVector<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
@@ -114,7 +114,7 @@ bool SystemZRegisterInfo::getRegAllocationHints(
if (VRRegMO->getSubReg())
PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
MRI->getRegClass(VirtReg));
- if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
+ if (!MRI->isReserved(PhysReg) && !Hints.contains(PhysReg))
TwoAddrHints.insert(PhysReg);
}
};
@@ -124,7 +124,7 @@ bool SystemZRegisterInfo::getRegAllocationHints(
}
for (MCPhysReg OrderReg : Order)
if (TwoAddrHints.count(OrderReg))
- Hints.push_back(OrderReg);
+ Hints.insert(OrderReg);
}
if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
index 7247736ff44e9..0089f513fb851 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
@@ -138,7 +138,7 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 7e1003c9b470b..d479e5d8a22b5 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -1165,7 +1165,7 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
@@ -1192,7 +1192,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
auto TryAddNDDHint = [&](const MachineOperand &MO) {
Register Reg = MO.getReg();
Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
- if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
+ if (PhysReg && !MRI->isReserved(PhysReg) && !Hints.contains(PhysReg))
TwoAddrHints.insert(PhysReg);
};
@@ -1219,7 +1219,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
for (MCPhysReg OrderReg : Order)
if (TwoAddrHints.count(OrderReg))
- Hints.push_back(OrderReg);
+ Hints.insert(OrderReg);
return BaseImplRetVal;
}
@@ -1228,22 +1228,22 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
auto AddHint = [&](MCPhysReg PhysReg) {
Register VReg = Matrix->getOneVReg(PhysReg);
if (VReg == MCRegister::NoRegister) { // Not allocated yet
- Hints.push_back(PhysReg);
+ Hints.insert(PhysReg);
return;
}
ShapeT PhysShape = getTileShape(VReg, const_cast<VirtRegMap *>(VRM), MRI);
if (PhysShape == VirtShape)
- Hints.push_back(PhysReg);
+ Hints.insert(PhysReg);
};
- SmallSet<MCPhysReg, 4> CopyHints(llvm::from_range, Hints);
+ SmallSetVector<MCPhysReg> CopyHints(Hints);
Hints.clear();
for (auto Hint : CopyHints) {
if (RC.contains(Hint) && !MRI->isReserved(Hint))
AddHint(Hint);
}
for (MCPhysReg PhysReg : Order) {
- if (!CopyHints.count(PhysReg) && RC.contains(PhysReg) &&
+ if (!CopyHints.contains(PhysReg) && RC.contains(PhysReg) &&
!MRI->isReserved(PhysReg))
AddHint(PhysReg);
}
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
index 399c6ab863705..218e9e281b5a1 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -165,7 +165,7 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
unsigned getSlotSize() const { return SlotSize; }
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
- SmallVectorImpl<MCPhysReg> &Hints,
+ SmallSetVector<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
diff --git a/llvm/unittests/CodeGen/AllocationOrderTest.cpp b/llvm/unittests/CodeGen/AllocationOrderTest.cpp
index 5346d1b1863aa..f3938146503bd 100644
--- a/llvm/unittests/CodeGen/AllocationOrderTest.cpp
+++ b/llvm/unittests/CodeGen/AllocationOrderTest.cpp
@@ -25,28 +25,35 @@ std::vector<MCPhysReg> loadOrder(const AllocationOrder &O, unsigned Limit = 0) {
} // namespace
TEST(AllocationOrderTest, Basic) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6, 7}), loadOrder(O));
}
TEST(AllocationOrderTest, Duplicates) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
+ SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6};
+ AllocationOrder O(std::move(Hints), Order, false);
+ EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6}), loadOrder(O));
+}
+
+TEST(AllocationOrderTest, DuplicateHints) {
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 1, 3, 2};
SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6}), loadOrder(O));
}
TEST(AllocationOrderTest, HardHints) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7};
AllocationOrder O(std::move(Hints), Order, true);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3}), loadOrder(O));
}
TEST(AllocationOrderTest, LimitsBasic) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6, 7}), loadOrder(O, 0));
@@ -55,7 +62,7 @@ TEST(AllocationOrderTest, LimitsBasic) {
}
TEST(AllocationOrderTest, LimitsDuplicates) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4}), loadOrder(O, 1));
@@ -65,21 +72,21 @@ TEST(AllocationOrderTest, LimitsDuplicates) {
}
TEST(AllocationOrderTest, LimitsHardHints) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6};
AllocationOrder O(std::move(Hints), Order, true);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3}), loadOrder(O, 1));
}
TEST(AllocationOrderTest, DuplicateIsFirst) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6}), loadOrder(O));
}
TEST(AllocationOrderTest, DuplicateIsFirstWithLimits) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3}), loadOrder(O, 1));
@@ -88,7 +95,7 @@ TEST(AllocationOrderTest, DuplicateIsFirstWithLimits) {
}
TEST(AllocationOrderTest, NoHints) {
- SmallVector<MCPhysReg, 16> Hints;
+ SmallSetVector<MCPhysReg> Hints;
SmallVector<MCPhysReg, 16> Order = {1, 2, 3, 4};
AllocationOrder O(std::move(Hints), Order, false);
EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4}), loadOrder(O));
@@ -97,7 +104,7 @@ TEST(AllocationOrderTest, NoHints) {
}
TEST(AllocationOrderTest, IsHintTest) {
- SmallVector<MCPhysReg, 16> Hints = {1, 2, 3};
+ SmallSetVector<MCPhysReg> Hints = {1, 2, 3};
SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6};
AllocationOrder O(std::move(Hints), Order, false);
auto I = O.begin();
diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
index 0f2cc69be42e5..13a61aaf0efa8 100644
--- a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
@@ -4,6 +4,7 @@
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -187,4 +188,49 @@ TEST(AArch64ReservedRegs, ArtificialHIRegistersAreReserved) {
EXPECT_TRUE(Reserved.test(AArch64::Q31_HI));
}
+TEST(AArch64RegAllocationHints, NoDuplicates) {
+ std::unique_ptr<TargetMachine> TM = createTargetMachine("");
+ ASSERT_TRUE(TM);
+
+ std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
+ ASSERT_TRUE(II);
+
+ const AArch64RegisterInfo &TRI = II->getRegisterInfo();
+
+ LLVMContext Context;
+ Module M("", Context);
+ M.setDataLayout(TM->getTargetTriple().computeDataLayout());
+ Function *F = Function::Create(
+ FunctionType::get(Type::getVoidTy(Context), /*isVarArg=*/false),
+ GlobalValue::ExternalLinkage, "f", &M);
+
+ MachineModuleInfo MMI(TM.get());
+ const TargetSubtargetInfo *STI = TM->getSubtargetImpl(*F);
+ MachineFunction MF(*F, *TM, *STI, MMI.getContext(), /*FunctionNum=*/0);
+ MF.initTargetMachineFunctionInfo(*STI);
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ MRI.freezeReservedRegs();
+
+ Register VirtReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
+ MRI.addRegAllocationHint(VirtReg, AArch64::X0);
+
+ ArrayRef<MCPhysReg> Order = AArch64::GPR64RegClass.getRegisters();
+ SmallSetVector<MCPhysReg> Hints;
+
+ // Calling getRegAllocationHints once should not produce duplicate hints
+ // from fallthrough to TargetRegisterInfo::getRegAllocationHints.
+ TRI.getRegAllocationHints(VirtReg, Order, Hints, MF, /*VRM=*/nullptr,
+ /*Matrix=*/nullptr);
+ EXPECT_EQ(Hints.size(), 1u);
+ EXPECT_EQ(Hints[0], MCPhysReg(AArch64::X0));
+
+ // Calling getRegAllocationHints a second time with Hints already populated
+ // should not append duplicate hints.
+ TRI.getRegAllocationHints(VirtReg, Order, Hints, MF, /*VRM=*/nullptr,
+ /*Matrix=*/nullptr);
+ EXPECT_EQ(Hints.size(), 1u);
+ EXPECT_EQ(Hints[0], MCPhysReg(AArch64::X0));
+}
+
} // namespace
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