[llvm] [AMDGPU] [NFC] Fix MSVC C4146 warnings in AMDGPU backend (PR #225474)

[Younes Yazami via llvm-commits]

https://github.com/yelidris-public updated https://github.com/llvm/llvm-project/pull/225474

>From a753b5be04dfb93ae5533824ac0f781d3d4474e1 Mon Sep 17 00:00:00 2001
From: yelidris <younes.elidrissiyazami at amd.com>
Date: Tue, 22 Sep 2026 14:12:08 -0400
Subject: [PATCH] [AMDGPU] [NFC] Fix MSVC C4146 warnings in AMDGPU backend

MSVC emits C4146 "unary minus operator applied to unsigned type, result still unsigned" for expressions of the form `-x` where `x` is an unsigned integer.
This patch is part of a series addressing these warnings.

Other LLVM header files will be addressed in separate PRs.
---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp               | 2 +-
 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp    | 4 ++--
 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 2 +-
 llvm/lib/Target/AMDGPU/SIFrameLowering.cpp                  | 6 +++---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp                   | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index ccf73a6aeef846..8746ed77eb94b2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3804,7 +3804,7 @@ SDValue AMDGPUTargetLowering::LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
   // Subtract the fp64 exponent bias (1023) to get the real exponent and
   // add the f16 bias (15) to get the biased exponent for the f16 format.
   E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
-                  DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
+                  DAG.getConstant(ExpBiasf16 - ExpBiasf64, DL, MVT::i32));
 
   SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
                           DAG.getConstant(8, DL, MVT::i32));
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index d71dcf225df504..c551cde57ad7c9 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -170,8 +170,8 @@ AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
                   .Case("BFD_RELOC_NONE", ELF::R_AMDGPU_NONE)
                   .Case("BFD_RELOC_32", ELF::R_AMDGPU_ABS32)
                   .Case("BFD_RELOC_64", ELF::R_AMDGPU_ABS64)
-                  .Default(-1u);
-  if (Type != -1u)
+                  .Default(~0u);
+  if (Type != ~0u)
     return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
   return std::nullopt;
 }
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index b3fdf38b9a6883..65a97009729c04 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -428,7 +428,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
                                            AMDGPU::OpName::srsrc);
     assert(vaddr0 >= 0 && srsrc > vaddr0);
     unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
-    unsigned NumPadding = (-NumExtraAddrs) & 3;
+    unsigned NumPadding = ~(NumExtraAddrs - 1u) & 3;
 
     for (unsigned i = 0; i < NumExtraAddrs; ++i) {
       getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups,
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index a9620b40931b83..8611998854bdb3 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1522,9 +1522,9 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
         .addImm((Alignment - 1) * getScratchScaleFactor(ST))
         .setMIFlag(MachineInstr::FrameSetup);
     auto And = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
-        .addReg(FramePtrReg, RegState::Kill)
-        .addImm(-Alignment * getScratchScaleFactor(ST))
-        .setMIFlag(MachineInstr::FrameSetup);
+                   .addReg(FramePtrReg, RegState::Kill)
+                   .addImm(~(Alignment * getScratchScaleFactor(ST) - 1u))
+                   .setMIFlag(MachineInstr::FrameSetup);
     And->getOperand(3).setIsDead(); // Mark SCC as dead.
     FuncInfo->setIsStackRealigned(true);
   } else if ((HasFP = hasFP(MF))) {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 9cf33b4ccbb875..fed12a9b7fbed4 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4712,7 +4712,7 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
     SDValue TmpAddr = DAG.getNode(ISD::ADD, dl, VT, BaseAddr,
                                   DAG.getConstant(StackAlignMask, dl, VT));
     BaseAddr = DAG.getNode(ISD::AND, dl, VT, TmpAddr,
-                           DAG.getSignedConstant(-ScaledAlignment, dl, VT));
+                           DAG.getConstant(~StackAlignMask, dl, VT));
   }
 
   assert(Size.getValueType() == MVT::i32 && "Size must be 32-bit");