[llvm] [ARM][FastISel] Fix soft-float f64 register pair order on big endian (PR #227172)

[David Green via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armebv7-linux-gnueabi -mattr=+vfp3 | FileCheck %s
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davemgreen wrote:

Could we test with and without fast-isel? To make it clear that the code lines up between the two isel's. With -fast-isel=0/1. I think -fast-isel-abort=1 shouldn't be needed.

https://github.com/llvm/llvm-project/pull/227172