[llvm] [Hexagon] Fix duplicate A2_tfr check in HexagonGlobalScheduler (PR #227762)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-hexagon

Author: Fateme Hosseini (fhossein-quic)

<details>
<summary>Changes</summary>

Fix a typo where both sides of a logical AND checked the same opcode (A2_tfr). The second check should be A2_tfrsi.

---
Full diff: https://github.com/llvm/llvm-project/pull/227762.diff


1 Files Affected:

- (modified) llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
index 452ef6a5facbf..aeab8d83ca100 100644
--- a/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
@@ -4161,7 +4161,7 @@ bool HexagonGlobalSchedulerImpl::pullUpPeelBBLoop(MachineBasicBlock *PredBB,
   if (RegMI->isBundle())
     return false;
   int TfrOpcode = RegMI->getOpcode();
-  if (TfrOpcode != Hexagon::A2_tfr && TfrOpcode != Hexagon::A2_tfr)
+  if (TfrOpcode != Hexagon::A2_tfr && TfrOpcode != Hexagon::A2_tfrsi)
     return false;
   if (!(RegMI->getOperand(0).isReg() && RegMI->getOperand(1).isReg()))
     return false;

``````````

</details>


https://github.com/llvm/llvm-project/pull/227762