[llvm] Sync pass name between newPM and legacy for irtranslator (PR #227425)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 08:56:08 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-m68k
Author: Mikołaj Piróg (mikolaj-pirog)
<details>
<summary>Changes</summary>
As in title
---
Patch is 199.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/227425.diff
226 Files Affected:
- (modified) llvm/docs/GlobalISel/GMIR.md (+2-2)
- (modified) llvm/docs/GlobalISel/IRTranslator.md (+4-4)
- (modified) llvm/docs/GlobalISel/index.md (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+13-13)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/debug-cpp.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dilocation.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/threadlocal-address.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/dbg-declare-swift-async.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/dbg-value-swift-async-non-entry-block.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/dereferenceable-metadata-mmo.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/memsize-remarks.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/speculative-load-intrinsic-mmo.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/convergence-tokens.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll (+4-4)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll (+3-3)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll (+2-2)
- (modified) llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll (+1-1)
- (modified) llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll (+3-3)
- (modified) llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/GlobalISel/irtranslator-pic.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll (+1-1)
- (modified) llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir (+1-1)
- (modified) llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir (+1-1)
- (modified) llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator-stackprotect.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll (+2-2)
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- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll (+1-1)
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- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll (+2-2)
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- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll (+2-2)
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- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll (+2-2)
- (modified) llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll (+1-1)
- (modified) llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll (+1-1)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll (+3-3)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll (+2-2)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll (+2-2)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll (+4-4)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll (+4-4)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll (+2-2)
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/GlobalISel/callingconv.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll (+1-1)
- (modified) llvm/test/Other/print-changed-machine.ll (+10-10)
``````````diff
diff --git a/llvm/docs/GlobalISel/GMIR.md b/llvm/docs/GlobalISel/GMIR.md
index e2cf2c7e4a6ff..4f07c1e852970 100644
--- a/llvm/docs/GlobalISel/GMIR.md
+++ b/llvm/docs/GlobalISel/GMIR.md
@@ -55,7 +55,7 @@ generic and non-generic). There are some exceptions to this but in general:
- instead of immediates, they use a generic virtual register defined by an
instruction that materializes the immediate value (see
- {ref}`irtranslator-constants`). Typically this is a G_CONSTANT or a
+ {ref}`ir-translator-constants`). Typically this is a G_CONSTANT or a
G_FCONSTANT. One example of an exception to this rule is G_SEXT_INREG where
having an immediate is mandatory.
- instead of physical register, they use a generic virtual register that is
@@ -208,7 +208,7 @@ scalar type is a nice simplification.
[^abi-dependent]: This mapping is ABI dependent. Here we've assumed no additional padding is required.
[^byte-as-integer]: The {ref}`byte type <t_byte>` `bN` is translated as the
- equi-sized integer scalar `sN`. See {ref}`irtranslator-byte-type`.
+ equi-sized integer scalar `sN`. See {ref}`ir-translator-byte-type`.
## Generic Opcode Reference
diff --git a/llvm/docs/GlobalISel/IRTranslator.md b/llvm/docs/GlobalISel/IRTranslator.md
index ef40644a1d6c8..3d347e899e591 100644
--- a/llvm/docs/GlobalISel/IRTranslator.md
+++ b/llvm/docs/GlobalISel/IRTranslator.md
@@ -1,4 +1,4 @@
-(irtranslator)=
+(ir-translator)=
# IRTranslator
@@ -74,7 +74,7 @@ backends, `CallLowering` makes available a few helpers and interfaces:
for invoking a given `ValueAssigner` and `ValueHandler` on a series of
`ArgInfo` objects.
-(irtranslator-aggregates)=
+(ir-translator-aggregates)=
### Aggregates
@@ -95,7 +95,7 @@ information on vregs).
See [PR26161](https://llvm.org/PR26161): [GlobalISel] Value to vreg during
IR to MachineInstr translation for aggregate type
-(irtranslator-constants)=
+(ir-translator-constants)=
## Translation of Constants
@@ -112,7 +112,7 @@ spills and reloads in an -O0 pipeline, as these virtual registers can have long
live ranges. This can be mitigated by running a [localizer](https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalISel/Localizer.cpp)
after the translator.
-(irtranslator-byte-type)=
+(ir-translator-byte-type)=
## Translation of the Byte Type
diff --git a/llvm/docs/GlobalISel/index.md b/llvm/docs/GlobalISel/index.md
index c960f7fe000d8..34e6e547b9566 100644
--- a/llvm/docs/GlobalISel/index.md
+++ b/llvm/docs/GlobalISel/index.md
@@ -102,7 +102,7 @@ We considered never having a fallback to SelectionDAG, instead deciding early
whether a given function is supported by GlobalISel or not. The decision would
be based on {ref}`milegalizer` queries.
We abandoned that for two reasons:
-a) on IR inputs, we'd need to basically simulate the {ref}`irtranslator`;
+a) on IR inputs, we'd need to basically simulate the {ref}`ir-translator`;
b) to be robust against unforeseen failures and to enable iterative
improvements.
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index cbad39bf4016c..ff142261e6a4f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -97,13 +97,13 @@
#include <utility>
#include <vector>
-#define DEBUG_TYPE "irtranslator"
+#define DEBUG_TYPE "ir-translator"
using namespace llvm;
static cl::opt<bool>
- EnableCSEInIRTranslator("enable-cse-in-irtranslator",
- cl::desc("Should enable CSE in irtranslator"),
+ EnableCSEInIRTranslator("enable-cse-in-ir-translator",
+ cl::desc("Should enable CSE in ir-translator"),
cl::init(false));
namespace llvm {
@@ -978,7 +978,7 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
if (isa<Constant>(Val)) {
bool Success = translate(cast<Constant>(Val), VRegs->front());
if (!Success) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
MF->getFunction().getSubprogram(),
&MF->getFunction().getEntryBlock());
R << "unable to translate constant: " << ore::NV("Type", Val.getType());
@@ -1046,7 +1046,7 @@ Align IRTranslatorImpl::getMemOpAlign(const Instruction &I) {
if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I))
return AI->getAlign();
- OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
+ OptimizationRemarkMissed R("gisel-ir-translator", "", &I);
R << "unable to translate memop: " << ore::NV("Opcode", &I);
reportTranslationError(*MF, *ORE, R);
return Align(1);
@@ -3024,7 +3024,7 @@ bool IRTranslatorImpl::translateKnownIntrinsic(const CallInst &CI,
if (auto *MI = dyn_cast<AnyMemIntrinsic>(&CI)) {
if (ORE->enabled()) {
if (MemoryOpRemark::canHandle(MI, *LibInfo)) {
- MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
+ MemoryOpRemark R(*ORE, "gisel-ir-translator-memsize", *DL, *LibInfo);
R.visit(MI);
}
}
@@ -3577,7 +3577,7 @@ bool IRTranslatorImpl::translateCallBase(const CallBase &CB,
if (auto *CI = dyn_cast<CallInst>(&CB)) {
if (ORE->enabled()) {
if (MemoryOpRemark::canHandle(CI, *LibInfo)) {
- MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
+ MemoryOpRemark R(*ORE, "gisel-ir-translator-memsize", *DL, *LibInfo);
R.visit(CI);
}
}
@@ -5120,7 +5120,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
SPInfo = StackProtectorInfo;
if (CLI->fallBackToDAGISel(*MF)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to lower function: "
<< ore::NV("Prototype", F.getFunctionType());
@@ -5184,7 +5184,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
// enableBigEndian()
if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
// Currently we don't properly handle big endian code.
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to translate in big endian mode";
reportTranslationError(*MF, *ORE, R);
@@ -5254,7 +5254,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
}
if (!CLI->lowerFormalArguments(*EntryBuilder, F, VRegArgs, FuncInfo)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to lower arguments: "
<< ore::NV("Prototype", F.getFunctionType());
@@ -5297,11 +5297,11 @@ bool IRTranslatorImpl::runOnMachineFunction(
if (translate(Inst))
continue;
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
Inst.getDebugLoc(), BB);
R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
- if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
+ if (ORE->allowExtraAnalysis("gisel-ir-translator")) {
std::string InstStrStorage;
raw_string_ostream InstStr(InstStrStorage);
InstStr << Inst;
@@ -5314,7 +5314,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
}
if (!finalizeBasicBlock(*BB, MBB)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
BB->getTerminator()->getDebugLoc(), BB);
R << "unable to translate basic block";
reportTranslationError(*MF, *ORE, R);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index f46bc68141028..365581ffab22b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-apple-ios9.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 3c9ff2d2d3865..11a6d49888725 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
index 291d89cdde99a..50dfe200b1e1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator %s | FileCheck %s
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=ir-translator %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
index edc1b0a974b9f..8f27f0a6d039b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
-; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
+; RUN: llc -O3 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
index 4e709ec684dc9..5dd0cc394367f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=ir-translator -o - -global-isel | FileCheck %s
; CHECK: name: test_stack_guard
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 7417636ce44b9..575f60795c400 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple aarch64 -aarch64-min-jump-table-entries=4 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -global-isel -mtriple aarch64 -aarch64-min-jump-table-entries=4 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i32 @switch(i32 %argc) {
; CHECK-LABEL: name: switch
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 29c70461a7ce6..da0020e814596 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
-; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
-; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
+; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
+; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
; This file checks that the translation from llvm IR to generic MachineInstr
; is correct.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
index 3e977e42ddef7..f3f5e9a2efb54 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel -stop-after=irtranslator | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel -stop-after=ir-translator | FileCheck %s
%struct.A = type { i8 }
%struct.B = type { i32 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll b/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
index 601645e0944f5..080caf31577b0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
; Test that the GlobalISel IRTranslator correctly marks blocks as address-taken
; based on whether the BlockAddress actually has users.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
index 140236d542d82..d82fbb175a0e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
@foo_alias = alias ptr, ptr @callee
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
index 3bdf1a26a8d47..7675360cf4d2e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-macho -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-macho -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
@foo_ifunc = ifunc i32 (i32), ptr @foo_resolver
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
index 2fb49d65dff46..78297cd6e7e38 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
; Verify that we generate G_ASSERT_SEXT for signext parameters.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
index c8cf5c56ffaca..ba54a9eb1a62e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define [9 x i64] @callee_sret_demotion() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index c261ead06b620..19419c0996ec9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i8 @v1s8_add(<1 x i8> %a0) {
; CHECK-LABEL: name: v1s8_add
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
index 45883b98ce9aa..557f117e638b6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
; Verify that we generate G_ASSERT_ZEXT for zeroext parameters.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/227425
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