[llvm] Sync pass name between newPM and legacy for irtranslator (PR #227425)
Mikołaj Piróg via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 08:55:19 PDT 2026
https://github.com/mikolaj-pirog updated https://github.com/llvm/llvm-project/pull/227425
>From d9ac580b8ebf2ce01d9d3583902da32271888de0 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 29 Sep 2026 20:26:37 +0200
Subject: [PATCH 1/2] Sync pass name between newPM and legacy for irtranslator
---
llvm/include/llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index d27a4740e8e52..85c9096972430 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -85,7 +85,7 @@ MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass())
MACHINE_FUNCTION_PASS("init-undef", InitUndefPass())
MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass())
MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass())
-MACHINE_FUNCTION_PASS("ir-translator", IRTranslatorPass(TM->getOptLevel()))
+MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass(TM->getOptLevel()))
MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass())
MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass())
MACHINE_FUNCTION_PASS("legalizer", LegalizerPass())
diff --git a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
index 8d3789ea8e838..06f42bdd23edf 100644
--- a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
@@ -1,7 +1,7 @@
# RUN: llc < %s -O0 -mtriple=aarch64-none-linux-gnu -mattr=+pauth -run-pass irtranslator -x mir | \
# RUN: llc -x mir -run-pass legalizer | FileCheck %s
# RUN: llc < %s -O0 -mtriple=aarch64-none-linux-gnu -mattr=+pauth -x mir \
-# RUN: -passes='require<libcall-lowering-info>,function(machine-function(ir-translator,legalizer))' | \
+# RUN: -passes='require<libcall-lowering-info>,function(machine-function(irtranslator,legalizer))' | \
# RUN: FileCheck %s
--- |
>From 5310cd9fb9cf0669a7ac4d1397ad6ca2f6963272 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 30 Sep 2026 17:54:47 +0200
Subject: [PATCH 2/2] Use ir-translator spelling
---
llvm/docs/GlobalISel/GMIR.md | 4 +--
llvm/docs/GlobalISel/IRTranslator.md | 8 +++---
llvm/docs/GlobalISel/index.md | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 26 +++++++++----------
.../GlobalISel/arm64-callingconv-ios.ll | 2 +-
.../AArch64/GlobalISel/arm64-callingconv.ll | 2 +-
.../GlobalISel/arm64-irtranslator-fmuladd.ll | 2 +-
.../GlobalISel/arm64-irtranslator-gep.ll | 4 +--
.../arm64-irtranslator-stackprotect.ll | 2 +-
.../GlobalISel/arm64-irtranslator-switch.ll | 2 +-
.../AArch64/GlobalISel/arm64-irtranslator.ll | 6 ++---
.../AArch64/GlobalISel/arm64-this-return.ll | 2 +-
.../blockaddress-stale-addresstaken.ll | 2 +-
.../AArch64/GlobalISel/call-lowering-alias.ll | 2 +-
.../AArch64/GlobalISel/call-lowering-ifunc.ll | 4 +--
.../GlobalISel/call-lowering-signext.ll | 2 +-
.../GlobalISel/call-lowering-sret-demotion.ll | 2 +-
.../GlobalISel/call-lowering-vectors.ll | 2 +-
.../GlobalISel/call-lowering-zeroext.ll | 2 +-
.../AArch64/GlobalISel/call-translator-cse.ll | 2 +-
.../AArch64/GlobalISel/call-translator-ios.ll | 2 +-
.../call-translator-tail-call-sret.ll | 2 +-
.../call-translator-tail-call-weak.ll | 2 +-
.../GlobalISel/call-translator-tail-call.ll | 4 +--
.../AArch64/GlobalISel/call-translator.ll | 2 +-
.../AArch64/GlobalISel/constant-dbg-loc.ll | 2 +-
.../CodeGen/AArch64/GlobalISel/debug-cpp.ll | 2 +-
.../CodeGen/AArch64/GlobalISel/debug-insts.ll | 2 +-
.../AArch64/GlobalISel/dynamic-alloca.ll | 2 +-
.../AArch64/GlobalISel/fconstant-dbg-loc.ll | 2 +-
.../GlobalISel/irtranslator-arguments.ll | 2 +-
.../irtranslator-atomic-metadata.ll | 2 +-
.../GlobalISel/irtranslator-bitcast.ll | 2 +-
.../irtranslator-condbr-lower-tree.ll | 2 +-
.../irtranslator-constrained-fcmp.ll | 2 +-
.../irtranslator-delayed-stack-protector.ll | 2 +-
.../GlobalISel/irtranslator-dilocation.ll | 4 +--
.../irtranslator-dynamic-alloca-scalable.ll | 2 +-
.../GlobalISel/irtranslator-exceptions.ll | 2 +-
.../GlobalISel/irtranslator-extends.ll | 2 +-
.../irtranslator-extract-used-by-dbg.ll | 2 +-
.../irtranslator-fixed-point-intrinsics.ll | 2 +-
.../irtranslator-fp-min-max-intrinsics.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-fpenv.ll | 2 +-
.../GlobalISel/irtranslator-gep-flags.ll | 2 +-
.../irtranslator-hoisted-constants.ll | 2 +-
...irtranslator-indirect-br-repeated-block.ll | 2 +-
.../GlobalISel/irtranslator-inline-asm.ll | 2 +-
.../irtranslator-invoke-probabilities.ll | 2 +-
.../GlobalISel/irtranslator-load-metadata.ll | 2 +-
.../GlobalISel/irtranslator-localescape.ll | 2 +-
.../irtranslator-max-address-space.ll | 2 +-
.../GlobalISel/irtranslator-memcpy-inline.ll | 2 +-
.../GlobalISel/irtranslator-memfunc-undef.ll | 2 +-
.../GlobalISel/irtranslator-memset-inline.ll | 4 +--
.../GlobalISel/irtranslator-nneg-disjoint.ll | 2 +-
.../irtranslator-no-op-intrinsics.ll | 2 +-
.../irtranslator-no-unwind-inline-asm.ll | 2 +-
.../irtranslator-one-by-n-vector-ptr-add.ll | 4 +--
.../GlobalISel/irtranslator-reductions.ll | 2 +-
.../GlobalISel/irtranslator-samesign.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-sincos.ll | 2 +-
.../irtranslator-split-vector-arg.ll | 2 +-
.../irtranslator-stack-evt-bug47619.ll | 2 +-
.../GlobalISel/irtranslator-stack-objects.ll | 2 +-
...slator-stack-protector-trap-unreachable.ll | 6 ++---
.../GlobalISel/irtranslator-stepvector.ll | 2 +-
.../GlobalISel/irtranslator-store-metadata.ll | 2 +-
.../GlobalISel/irtranslator-subvector.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-sucmp.ll | 2 +-
.../GlobalISel/irtranslator-switch-bittest.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-tbaa.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-trunc.ll | 2 +-
.../GlobalISel/irtranslator-unreachable.ll | 2 +-
.../irtranslator-unwind-inline-asm.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-vararg.ll | 2 +-
.../irtranslator-vector-deinterleave2.ll | 2 +-
.../irtranslator-vector-interleave2.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-vscale.ll | 2 +-
.../irtranslator-weird-alloca-size.ll | 2 +-
.../AArch64/GlobalISel/phi-with-empty-type.ll | 2 +-
.../CodeGen/AArch64/GlobalISel/ret-1x-vec.ll | 2 +-
.../AArch64/GlobalISel/ret-vec-promote.ll | 2 +-
.../AArch64/GlobalISel/threadlocal-address.ll | 2 +-
.../AArch64/GlobalISel/translate-gep.ll | 2 +-
.../AArch64/GlobalISel/translate-ret.ll | 2 +-
.../translate-sve-formal-argument-multiple.ll | 2 +-
.../translate-sve-formal-argument.ll | 2 +-
.../CodeGen/AArch64/GlobalISel/vastart.ll | 4 +--
.../CodeGen/AArch64/GlobalISel/vec-param.ll | 2 +-
.../AArch64/GlobalISel/vec-s16-param.ll | 2 +-
.../AArch64/dbg-declare-swift-async.ll | 2 +-
.../dbg-value-swift-async-non-entry-block.ll | 2 +-
.../CodeGen/AArch64/dbg-value-swift-async.ll | 2 +-
.../AArch64/dereferenceable-metadata-mmo.ll | 2 +-
llvm/test/CodeGen/AArch64/memsize-remarks.ll | 12 ++++-----
.../AArch64/speculative-load-intrinsic-mmo.ll | 2 +-
.../AMDGPU/GlobalISel/amdgpu-irtranslator.ll | 2 +-
.../GlobalISel/dereferenceable-declaration.ll | 2 +-
.../AMDGPU/GlobalISel/function-returns.ll | 2 +-
.../GlobalISel/function-returns.v2i65.ll | 2 +-
.../AMDGPU/GlobalISel/irtranslate-bf16.ll | 2 +-
.../irtranslator-amdgcn-cs-chain.ll | 4 +--
.../GlobalISel/irtranslator-amdgcn-sendmsg.ll | 2 +-
...irtranslator-amdgpu_kernel-system-sgprs.ll | 2 +-
.../GlobalISel/irtranslator-amdgpu_kernel.ll | 4 +--
.../GlobalISel/irtranslator-amdgpu_ps.ll | 2 +-
.../GlobalISel/irtranslator-amdgpu_vs.ll | 2 +-
.../GlobalISel/irtranslator-assert-align.ll | 2 +-
.../GlobalISel/irtranslator-atomicrmw.ll | 2 +-
.../irtranslator-call-abi-attribute-hints.ll | 2 +-
.../irtranslator-call-implicit-args.ll | 4 +--
.../GlobalISel/irtranslator-call-non-fixed.ll | 2 +-
.../irtranslator-call-return-values.ll | 2 +-
.../GlobalISel/irtranslator-call-sret.ll | 2 +-
.../AMDGPU/GlobalISel/irtranslator-call.ll | 2 +-
.../irtranslator-constant-fold-vector-op.ll | 2 +-
.../GlobalISel/irtranslator-constantexpr.ll | 2 +-
.../GlobalISel/irtranslator-constrained-fp.ll | 2 +-
.../irtranslator-fast-math-flags.ll | 2 +-
.../AMDGPU/GlobalISel/irtranslator-fence.ll | 2 +-
...translator-fixed-function-abi-vgpr-args.ll | 2 +-
.../GlobalISel/irtranslator-function-args.ll | 2 +-
.../irtranslator-function-args.v2i65.ll | 2 +-
.../GlobalISel/irtranslator-getelementptr.ll | 2 +-
.../GlobalISel/irtranslator-indirect-call.ll | 2 +-
.../GlobalISel/irtranslator-inline-asm.ll | 2 +-
.../GlobalISel/irtranslator-invariant.ll | 2 +-
.../irtranslator-memory-intrinsics.ll | 2 +-
.../GlobalISel/irtranslator-metadata.ll | 2 +-
...tor-non-integral-address-spaces-vectors.ll | 2 +-
...rtranslator-non-integral-address-spaces.ll | 2 +-
.../GlobalISel/irtranslator-prefetch.ll | 2 +-
.../AMDGPU/GlobalISel/irtranslator-ptrmask.ll | 2 +-
...rtranslator-readnone-intrinsic-callsite.ll | 2 +-
.../AMDGPU/GlobalISel/irtranslator-sat.ll | 2 +-
.../GlobalISel/irtranslator-sibling-call.ll | 2 +-
.../irtranslator-struct-return-intrinsics.ll | 2 +-
.../GlobalISel/irtranslator-tail-call.ll | 2 +-
.../GlobalISel/irtranslator-zext-vec-index.ll | 2 +-
.../promote-dependency-on-invariant-result.ll | 2 +-
.../attributor-flatscratchinit-globalisel.ll | 2 +-
.../test/CodeGen/AMDGPU/convergence-tokens.ll | 2 +-
.../irtranslator-whole-wave-functions.ll | 2 +-
.../ARM/GlobalISel/arm-call-lowering.ll | 8 +++---
.../ARM/GlobalISel/arm-irtranslator.ll | 4 +--
.../ARM/GlobalISel/arm-param-lowering.ll | 6 ++---
.../irtranslator-varargs-lowering.ll | 4 +--
.../BPF/GlobalISel/ir-translator-ret.ll | 2 +-
.../GlobalISel/irtranslator-byte-type.ll | 6 ++---
.../M68k/GlobalISel/irtranslator-call.ll | 2 +-
.../M68k/GlobalISel/irtranslator-pic.ll | 2 +-
.../M68k/GlobalISel/irtranslator-ret.ll | 2 +-
.../MIR/AArch64/deactivation-symbols.mir | 4 +--
.../print-parse-overloaded-intrinsics.mir | 2 +-
.../test/CodeGen/MIR/AArch64/unnamed-stack.ll | 2 +-
.../Mips/GlobalISel/irtranslator/add.ll | 2 +-
.../irtranslator/aggregate_struct_return.ll | 4 +--
.../GlobalISel/irtranslator/big-endian.ll | 8 +++---
.../Mips/GlobalISel/irtranslator/bitwise.ll | 2 +-
.../Mips/GlobalISel/irtranslator/call.ll | 4 +--
.../GlobalISel/irtranslator/extend_args.ll | 4 +--
.../GlobalISel/irtranslator/float_args.ll | 4 +--
.../GlobalISel/irtranslator/global_address.ll | 2 +-
.../irtranslator/global_address_pic.ll | 2 +-
.../Mips/GlobalISel/irtranslator/pointers.ll | 2 +-
.../Mips/GlobalISel/irtranslator/ret.ll | 2 +-
.../GlobalISel/irtranslator/split_args.ll | 2 +-
.../GlobalISel/irtranslator/sret_pointer.ll | 2 +-
.../GlobalISel/irtranslator/stack_args.ll | 2 +-
.../Mips/GlobalISel/irtranslator/var_arg.ll | 2 +-
.../irtranslator-args-lowering-fp128.ll | 2 +-
.../irtranslator-args-lowering-mixed-types.ll | 2 +-
.../irtranslator-args-lowering-scalar.ll | 2 +-
.../irtranslator-args-lowering-vectors.ll | 2 +-
.../GlobalISel/irtranslator-args-lowering.ll | 2 +-
.../ppc-irtranslator-stackprotect.ll | 4 +--
.../GlobalISel/irtranslator-calllowering.ll | 4 +--
.../GlobalISel/irtranslator-inline-asm.ll | 2 +-
.../RISCV/GlobalISel/irtranslator/alloca.ll | 2 +-
.../RISCV/GlobalISel/irtranslator/args.ll | 4 +--
.../irtranslator/calling-conv-half.ll | 12 ++++-----
.../calling-conv-ilp32-ilp32f-common.ll | 4 +--
...calling-conv-ilp32-ilp32f-ilp32d-common.ll | 6 ++---
.../irtranslator/calling-conv-ilp32.ll | 2 +-
.../irtranslator/calling-conv-ilp32d.ll | 2 +-
.../calling-conv-ilp32f-ilp32d-common.ll | 4 +--
.../calling-conv-lp64-lp64f-common.ll | 4 +--
.../calling-conv-lp64-lp64f-lp64d-common.ll | 6 ++---
.../irtranslator/calling-conv-lp64.ll | 4 +--
.../irtranslator/calling-conv-lp64d.ll | 2 +-
.../RISCV/GlobalISel/irtranslator/calls.ll | 4 +--
.../fixed-vectors-calling-conv.ll | 2 +-
.../GlobalISel/irtranslator/insertelement.ll | 4 +--
.../irtranslator/lower-args-vararg.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/ret.ll | 4 +--
.../GlobalISel/irtranslator/shufflevector.ll | 4 +--
.../GlobalISel/irtranslator/splat_vector.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/vacopy.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/vararg.ll | 14 +++++-----
.../irtranslator/vec-args-bf16-err.ll | 4 +--
.../irtranslator/vec-args-f16-err.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/vec-args.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/vec-ld.ll | 4 +--
.../irtranslator/vec-ret-bf16-err.ll | 4 +--
.../irtranslator/vec-ret-f16-err.ll | 4 +--
.../RISCV/GlobalISel/irtranslator/vec-ret.ll | 4 +--
.../GlobalISel/irtranslator/vec-store.ll | 4 +--
.../SPIRV/passes/translate-aggregate-uaddo.ll | 2 +-
.../SPIRV/pointers/global-vars-untyped.ll | 2 +-
.../GlobalISel/irtranslator/args-simd.ll | 6 ++---
.../GlobalISel/irtranslator/args-swiftcc.ll | 4 +--
.../GlobalISel/irtranslator/args.ll | 4 +--
.../GlobalISel/irtranslator/call-basics.ll | 8 +++---
.../GlobalISel/irtranslator/ret-aggregates.ll | 8 +++---
.../GlobalISel/irtranslator/ret-basics.ll | 4 +--
.../GlobalISel/irtranslator/ret-simd.ll | 4 +--
.../X86/GlobalISel/bitinsert-bitextract.ll | 2 +-
.../CodeGen/X86/GlobalISel/callingconv.ll | 4 +--
.../X86/GlobalISel/calllowering-inalloca.ll | 2 +-
.../X86/GlobalISel/calllowering-nocrashret.ll | 2 +-
.../GlobalISel/irtranslator-callingconv.ll | 4 +--
.../X86/GlobalISel/x32-irtranslator.ll | 2 +-
.../x86_64-irtranslator-struct-return.ll | 2 +-
.../X86/GlobalISel/x86_64-irtranslator.ll | 2 +-
llvm/test/Other/print-changed-machine.ll | 20 +++++++-------
227 files changed, 339 insertions(+), 339 deletions(-)
diff --git a/llvm/docs/GlobalISel/GMIR.md b/llvm/docs/GlobalISel/GMIR.md
index e2cf2c7e4a6ff..4f07c1e852970 100644
--- a/llvm/docs/GlobalISel/GMIR.md
+++ b/llvm/docs/GlobalISel/GMIR.md
@@ -55,7 +55,7 @@ generic and non-generic). There are some exceptions to this but in general:
- instead of immediates, they use a generic virtual register defined by an
instruction that materializes the immediate value (see
- {ref}`irtranslator-constants`). Typically this is a G_CONSTANT or a
+ {ref}`ir-translator-constants`). Typically this is a G_CONSTANT or a
G_FCONSTANT. One example of an exception to this rule is G_SEXT_INREG where
having an immediate is mandatory.
- instead of physical register, they use a generic virtual register that is
@@ -208,7 +208,7 @@ scalar type is a nice simplification.
[^abi-dependent]: This mapping is ABI dependent. Here we've assumed no additional padding is required.
[^byte-as-integer]: The {ref}`byte type <t_byte>` `bN` is translated as the
- equi-sized integer scalar `sN`. See {ref}`irtranslator-byte-type`.
+ equi-sized integer scalar `sN`. See {ref}`ir-translator-byte-type`.
## Generic Opcode Reference
diff --git a/llvm/docs/GlobalISel/IRTranslator.md b/llvm/docs/GlobalISel/IRTranslator.md
index ef40644a1d6c8..3d347e899e591 100644
--- a/llvm/docs/GlobalISel/IRTranslator.md
+++ b/llvm/docs/GlobalISel/IRTranslator.md
@@ -1,4 +1,4 @@
-(irtranslator)=
+(ir-translator)=
# IRTranslator
@@ -74,7 +74,7 @@ backends, `CallLowering` makes available a few helpers and interfaces:
for invoking a given `ValueAssigner` and `ValueHandler` on a series of
`ArgInfo` objects.
-(irtranslator-aggregates)=
+(ir-translator-aggregates)=
### Aggregates
@@ -95,7 +95,7 @@ information on vregs).
See [PR26161](https://llvm.org/PR26161): [GlobalISel] Value to vreg during
IR to MachineInstr translation for aggregate type
-(irtranslator-constants)=
+(ir-translator-constants)=
## Translation of Constants
@@ -112,7 +112,7 @@ spills and reloads in an -O0 pipeline, as these virtual registers can have long
live ranges. This can be mitigated by running a [localizer](https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalISel/Localizer.cpp)
after the translator.
-(irtranslator-byte-type)=
+(ir-translator-byte-type)=
## Translation of the Byte Type
diff --git a/llvm/docs/GlobalISel/index.md b/llvm/docs/GlobalISel/index.md
index c960f7fe000d8..34e6e547b9566 100644
--- a/llvm/docs/GlobalISel/index.md
+++ b/llvm/docs/GlobalISel/index.md
@@ -102,7 +102,7 @@ We considered never having a fallback to SelectionDAG, instead deciding early
whether a given function is supported by GlobalISel or not. The decision would
be based on {ref}`milegalizer` queries.
We abandoned that for two reasons:
-a) on IR inputs, we'd need to basically simulate the {ref}`irtranslator`;
+a) on IR inputs, we'd need to basically simulate the {ref}`ir-translator`;
b) to be robust against unforeseen failures and to enable iterative
improvements.
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 85c9096972430..d27a4740e8e52 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -85,7 +85,7 @@ MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass())
MACHINE_FUNCTION_PASS("init-undef", InitUndefPass())
MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass())
MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass())
-MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass(TM->getOptLevel()))
+MACHINE_FUNCTION_PASS("ir-translator", IRTranslatorPass(TM->getOptLevel()))
MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass())
MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass())
MACHINE_FUNCTION_PASS("legalizer", LegalizerPass())
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index cbad39bf4016c..ff142261e6a4f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -97,13 +97,13 @@
#include <utility>
#include <vector>
-#define DEBUG_TYPE "irtranslator"
+#define DEBUG_TYPE "ir-translator"
using namespace llvm;
static cl::opt<bool>
- EnableCSEInIRTranslator("enable-cse-in-irtranslator",
- cl::desc("Should enable CSE in irtranslator"),
+ EnableCSEInIRTranslator("enable-cse-in-ir-translator",
+ cl::desc("Should enable CSE in ir-translator"),
cl::init(false));
namespace llvm {
@@ -978,7 +978,7 @@ ArrayRef<Register> IRTranslatorImpl::getOrCreateVRegs(const Value &Val) {
if (isa<Constant>(Val)) {
bool Success = translate(cast<Constant>(Val), VRegs->front());
if (!Success) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
MF->getFunction().getSubprogram(),
&MF->getFunction().getEntryBlock());
R << "unable to translate constant: " << ore::NV("Type", Val.getType());
@@ -1046,7 +1046,7 @@ Align IRTranslatorImpl::getMemOpAlign(const Instruction &I) {
if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I))
return AI->getAlign();
- OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
+ OptimizationRemarkMissed R("gisel-ir-translator", "", &I);
R << "unable to translate memop: " << ore::NV("Opcode", &I);
reportTranslationError(*MF, *ORE, R);
return Align(1);
@@ -3024,7 +3024,7 @@ bool IRTranslatorImpl::translateKnownIntrinsic(const CallInst &CI,
if (auto *MI = dyn_cast<AnyMemIntrinsic>(&CI)) {
if (ORE->enabled()) {
if (MemoryOpRemark::canHandle(MI, *LibInfo)) {
- MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
+ MemoryOpRemark R(*ORE, "gisel-ir-translator-memsize", *DL, *LibInfo);
R.visit(MI);
}
}
@@ -3577,7 +3577,7 @@ bool IRTranslatorImpl::translateCallBase(const CallBase &CB,
if (auto *CI = dyn_cast<CallInst>(&CB)) {
if (ORE->enabled()) {
if (MemoryOpRemark::canHandle(CI, *LibInfo)) {
- MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
+ MemoryOpRemark R(*ORE, "gisel-ir-translator-memsize", *DL, *LibInfo);
R.visit(CI);
}
}
@@ -5120,7 +5120,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
SPInfo = StackProtectorInfo;
if (CLI->fallBackToDAGISel(*MF)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to lower function: "
<< ore::NV("Prototype", F.getFunctionType());
@@ -5184,7 +5184,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
// enableBigEndian()
if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
// Currently we don't properly handle big endian code.
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to translate in big endian mode";
reportTranslationError(*MF, *ORE, R);
@@ -5254,7 +5254,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
}
if (!CLI->lowerFormalArguments(*EntryBuilder, F, VRegArgs, FuncInfo)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
F.getSubprogram(), &F.getEntryBlock());
R << "unable to lower arguments: "
<< ore::NV("Prototype", F.getFunctionType());
@@ -5297,11 +5297,11 @@ bool IRTranslatorImpl::runOnMachineFunction(
if (translate(Inst))
continue;
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
Inst.getDebugLoc(), BB);
R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
- if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
+ if (ORE->allowExtraAnalysis("gisel-ir-translator")) {
std::string InstStrStorage;
raw_string_ostream InstStr(InstStrStorage);
InstStr << Inst;
@@ -5314,7 +5314,7 @@ bool IRTranslatorImpl::runOnMachineFunction(
}
if (!finalizeBasicBlock(*BB, MBB)) {
- OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
+ OptimizationRemarkMissed R("gisel-ir-translator", "GISelFailure",
BB->getTerminator()->getDebugLoc(), BB);
R << "unable to translate basic block";
reportTranslationError(*MF, *ORE, R);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index f46bc68141028..365581ffab22b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-apple-ios9.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 3c9ff2d2d3865..11a6d49888725 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
index 291d89cdde99a..50dfe200b1e1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator %s | FileCheck %s
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=ir-translator %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
index edc1b0a974b9f..8f27f0a6d039b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
-; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
+; RUN: llc -O3 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
index 4e709ec684dc9..5dd0cc394367f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=ir-translator -o - -global-isel | FileCheck %s
; CHECK: name: test_stack_guard
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 7417636ce44b9..575f60795c400 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple aarch64 -aarch64-min-jump-table-entries=4 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -global-isel -mtriple aarch64 -aarch64-min-jump-table-entries=4 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i32 @switch(i32 %argc) {
; CHECK-LABEL: name: switch
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 29c70461a7ce6..da0020e814596 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
-; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
-; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
+; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
+; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
; This file checks that the translation from llvm IR to generic MachineInstr
; is correct.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
index 3e977e42ddef7..f3f5e9a2efb54 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel -stop-after=irtranslator | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel -stop-after=ir-translator | FileCheck %s
%struct.A = type { i8 }
%struct.B = type { i32 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll b/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
index 601645e0944f5..080caf31577b0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/blockaddress-stale-addresstaken.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
; Test that the GlobalISel IRTranslator correctly marks blocks as address-taken
; based on whether the BlockAddress actually has users.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
index 140236d542d82..d82fbb175a0e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
@foo_alias = alias ptr, ptr @callee
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
index 3bdf1a26a8d47..7675360cf4d2e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-macho -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-macho -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-elf -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
@foo_ifunc = ifunc i32 (i32), ptr @foo_resolver
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
index 2fb49d65dff46..78297cd6e7e38 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
; Verify that we generate G_ASSERT_SEXT for signext parameters.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
index c8cf5c56ffaca..ba54a9eb1a62e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define [9 x i64] @callee_sret_demotion() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index c261ead06b620..19419c0996ec9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i8 @v1s8_add(<1 x i8> %a0) {
; CHECK-LABEL: name: v1s8_add
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
index 45883b98ce9aa..557f117e638b6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
; Verify that we generate G_ASSERT_ZEXT for zeroext parameters.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
index 4ac1adc0ee2f9..d4547bb3e1d1b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=ir-translator -enable-cse-in-ir-translator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index d5ffcb2b9b556..f2a8c544d4dcb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_stack_slots
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
index 71104bb4de1ca..752f0eaec3ffb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc < %s -mtriple arm64-apple-darwin -global-isel -stop-after=irtranslator -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple arm64-apple-darwin -global-isel -stop-after=ir-translator -verify-machineinstrs | FileCheck %s
; Check that we don't try to tail-call with a non-forwarded sret parameter.
declare void @test_explicit_sret(ptr sret(i64))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll
index b2f9d41f35359..ffb503007aa26 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc %s -stop-after=irtranslator -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -o - 2>&1 | FileCheck %s --check-prefix=DARWIN
+; RUN: llc %s -stop-after=ir-translator -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -o - 2>&1 | FileCheck %s --check-prefix=DARWIN
; Shouldn't tail call when the OS doesn't support it.
declare extern_weak void @extern_weak_fn()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
index e394aaf0d8f4a..7a06e1d3cac17 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc %s -stop-after=irtranslator -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -o - 2>&1 | FileCheck %s --check-prefix=DARWIN
-; RUN: llc %s -stop-after=irtranslator -verify-machineinstrs -mtriple aarch64-windows -global-isel -o - 2>&1 | FileCheck %s --check-prefix=WINDOWS
+; RUN: llc %s -stop-after=ir-translator -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -o - 2>&1 | FileCheck %s --check-prefix=DARWIN
+; RUN: llc %s -stop-after=ir-translator -verify-machineinstrs -mtriple aarch64-windows -global-isel -o - 2>&1 | FileCheck %s --check-prefix=WINDOWS
declare void @simple_fn()
define void @tail_call() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 240651012ccf8..d3330e2b104df 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_trivial_call
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
index b21f184ae78ce..5213501652954 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple aarch64 -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck --match-full-lines %s
+; RUN: llc -mtriple aarch64 -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck --match-full-lines %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/debug-cpp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/debug-cpp.ll
index cb4a01cbcf092..a8b0189f95d66 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/debug-cpp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/debug-cpp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=ir-translator -o - | FileCheck %s
; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null
; struct NTCopy {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
index d24d1f822e4ac..c5d693b446aef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=ir-translator -o - | FileCheck %s
; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 %s -o /dev/null
; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 %s -o /dev/null -debug
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
index f46cc65b5c60f..5850cf84de6b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=ir-translator | FileCheck %s
define ptr @test_simple_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_simple_alloca
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
index 4661a0132afc0..c1a8fa9c74229 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
@@ -1,6 +1,6 @@
; Make sure we don't assign debug locations to G_FCONSTANT(s) when lowering.
-; RUN: llc -mtriple aarch64 -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck --match-full-lines %s
+; RUN: llc -mtriple aarch64 -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck --match-full-lines %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
index 68d6d493323cd..965fcc37a98f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
declare void @use_s128(i128 %a, i128 %b)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
index 1b36f217dbc9e..d65ced7d71e68 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
define i32 @atomicrmw_volatile(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_volatile
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
index 6749a32e237db..4d63afafdc189 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
; Check that we don't invalidate the vreg map.
; This test is brittle: the invalidation only triggers when we grow the map.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
index 8f5c41de13d3b..addd58dab054e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple aarch64 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
index bb9c9caefabc1..66e11a48a8e1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc --global-isel --mtriple=aarch64-- --stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc --global-isel --mtriple=aarch64-- --stop-after=ir-translator -o - %s | FileCheck %s
define void @test_strict_fcmp(float %a, float %b) strictfp {
; CHECK-LABEL: name: test_strict_fcmp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
index 0b7fc9d516bd4..37343a076de87 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=ir-translator -o - -global-isel | FileCheck %s
define void @caller() sspreq {
; CHECK-LABEL: name: caller
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dilocation.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dilocation.ll
index 2bd019b148a94..e9388b591dd68 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dilocation.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dilocation.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -debug-only=irtranslator \
-; RUN: -stop-after=irtranslator %s -o - 2>&1 | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -debug-only=ir-translator \
+; RUN: -stop-after=ir-translator %s -o - 2>&1 | FileCheck %s
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll
index 04bf589a17505..4a571bd9255c8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve %s -o - -stop-after=irtranslator | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve %s -o - -stop-after=ir-translator | FileCheck %s
; Tests for scalable vector allocas in GlobalISel
; Test basic scalable vector alloca (single allocation)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index c0a9f0cb1edb8..75446a89af627 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
@_ZTIi = external global ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
index 249bca91a3cb4..58dbb42a5bb79 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
; Test that extends correctly translate to G_[ZS]EXT. The translator will never
; emit a G_SEXT_INREG.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll
index 9f398b4a9d3b1..1316f1c58127a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-fuchsia"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
index a9301581e7694..081d1eb074990 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=aarch64-- -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=aarch64-- -verify-machineinstrs -o - %s | FileCheck %s
define i16 @smul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
index d8e172d93513a..30e258a5db99e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-- -verify-machineinstrs -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-- -verify-machineinstrs -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
define float @test_minnum(float %x, float %y) {
; CHECK-LABEL: name: test_minnum
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
index 56354d5ddfd33..bde21a7186e32 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
declare i64 @llvm.get.fpenv.i64()
declare void @llvm.set.fpenv.i64(i64 %fpenv)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
index 7f596ca20234d..7fa31b2394be7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define i32 @gep_nusw_nuw(ptr %ptr, i32 %idx) {
; CHECK-LABEL: name: gep_nusw_nuw
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
index bc6a4a3febf76..74567dc5159bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s --check-prefix=TRANSLATED
+; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s --check-prefix=TRANSLATED
; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-before=instruction-select %s -o - | FileCheck %s --check-prefix=PRESELECTION
; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-after=instruction-select %s -o - | FileCheck %s --check-prefix=POSTSELECTION
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll
index 70872da376123..779c4b956f49b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
;
; Make sure that we don't duplicate successors/predecessors when translating
; indirectbr instructions with duplicate block labels.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 5569de5c4ba61..a62897e802490 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-darwin-ios13 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-darwin-ios13 -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define void @asm_simple_memory_clobber() {
; CHECK-LABEL: name: asm_simple_memory_clobber
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
index ca65bbb7cee3a..947788df84378 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
%struct.foo = type { i64, i64, %struct.pluto, %struct.pluto }
%struct.pluto = type { %struct.wombat }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
index 52f6d90e2c72b..817eb918d729a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
define i32 @load_invariant(ptr %ptr) {
; CHECK-LABEL: name: load_invariant
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
index 03a148c9292a4..3a5626136f56b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=arm64-windows -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=arm64-windows -stop-after=ir-translator -o - %s | FileCheck %s
define void @local_escape() {
; CHECK-LABEL: name: local_escape
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
index 2e4d020cc495c..a64f8e589b020 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
; CHECK-LABEL: name: store_max_address_space
; CHECK: %0:_(p16777215) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
index 1d4f53d2ed4dd..aa4d9e833155d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=ir-translator %s -o - | FileCheck %s
define void @copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll
index e96b6bf906dac..1beb15b7d58d7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -verify-machineinstrs -stop-after=ir-translator %s -o - | FileCheck %s
define void @memset() {
; CHECK-LABEL: name: memset
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll
index 4e299a2eec47d..3566243c5952a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
-; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+mops -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=ir-translator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+mops -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=ir-translator %s -o - | FileCheck %s
define void @memset(ptr %dst, i8 %val) {
; CHECK-LABEL: name: memset
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
index af07caa67539d..8519776b38dc7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i32 @call_nneg(i16 %a) {
; CHECK-LABEL: name: call_nneg
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
index d2fcbe2473e39..a81e15f374f39 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -O0 -mtriple=aarch64-- -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -global-isel -O0 -mtriple=aarch64-- -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define i64 @expect_i64(i64 %arg0) {
; CHECK-LABEL: name: expect_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
index 33e842ac535e2..aa72b1196cacd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -global-isel -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -O0 -global-isel -stop-after=ir-translator < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
index e9a02e768b305..1939d4083824f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -global-isel -mtriple aarch64 -stop-after=irtranslator -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false | FileCheck %s --check-prefix=CHECK
-; RUN: llc -O0 -global-isel -mtriple aarch64 -stop-after=irtranslator -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat | FileCheck %s --check-prefix=CHECK-CI
+; RUN: llc -O0 -global-isel -mtriple aarch64 -stop-after=ir-translator -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false | FileCheck %s --check-prefix=CHECK
+; RUN: llc -O0 -global-isel -mtriple aarch64 -stop-after=ir-translator -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat | FileCheck %s --check-prefix=CHECK-CI
; Make sure we treat <1 x N> getelementptrs like scalar getelementptrs.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
index d7d5bdf6d1c22..ba8a239611394 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -disable-expand-reductions -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -disable-expand-reductions -stop-after=ir-translator %s -o - | FileCheck %s
define float @fadd_seq(float %start, <4 x float> %vec) {
; CHECK-LABEL: name: fadd_seq
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll
index 5dbd18a148222..c2103c6952e3c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -global-isel -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator < %s | FileCheck %s
define <2 x i1> @call_icmp_samesign_vector(<2 x i32> %a, <2 x i32> %b) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
index 471fb5ad0017f..b7a30106ac03d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define { half, half } @test_sincos_f16(half %a) {
; CHECK-LABEL: name: test_sincos_f16
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
index 749c221651f81..b4e22e3773861 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=1 %s -stop-after=irtranslator -o - | FileCheck %s
+; RUN: llc -global-isel -global-isel-abort=1 %s -stop-after=ir-translator -o - | FileCheck %s
target triple = "aarch64-apple-ios"
; Check that we correctly split %arg into two vector registers of
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
index f6421dfc2c9e2..d16d2a8bb9f44 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
; Make sure the i3 %arg8 value is correctly handled. This was trying
; to use MVT for EVT values passed on the stack and asserting before
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
index 256ab9c2bd705..c701997251e93 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
@@ -1,4 +1,4 @@
-; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
; The byval object should not be immutable, but the non-byval stack
; passed argument should be.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
index afa4d58d78723..314006d47c89c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs \
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs \
; RUN: -trap-unreachable=false -o - %s | FileCheck -check-prefix=NO_TRAP_UNREACHABLE %s
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs \
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs \
; RUN: -trap-unreachable -no-trap-after-noreturn -o - %s | FileCheck -check-prefix=NO_TRAP_UNREACHABLE %s
-; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs \
+; RUN: llc -mtriple=aarch64 -global-isel -stop-after=ir-translator -verify-machineinstrs \
; RUN: -trap-unreachable -no-trap-after-noreturn=false -o - %s | FileCheck -check-prefix=TRAP_UNREACHABLE %s
;; Make sure we emit trap instructions after stack protector checks iff NoTrapAfterNoReturn is false.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
index 164435ee8f52d..766f7b2fe6181 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 -stop-after=ir-translator %s -o - | FileCheck %s
define <vscale x 2 x i64> @call_step_vector_i64() {
; CHECK-LABEL: name: call_step_vector_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
index a9521bc852644..5a07d90deedb9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
define void @store_nontemporal(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: store_nontemporal
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
index 1144466e677ec..b0ec604e3b048 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -stop-after=irtranslator -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -stop-after=ir-translator -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s
define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK-LABEL: name: extract_v4i32_vector_insert_const
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
index 09efe53912453..84c07b075ffb2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define void @scmp_i32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: scmp_i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
index 5a8b0935475c5..66e0fd15ce9c1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs -disable-cgp-delete-phis %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs -disable-cgp-delete-phis %s -o - 2>&1 | FileCheck %s
define i32 @test_bittest(i16 %p) {
; CHECK-LABEL: name: test_bittest
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
index fd324071306e9..633a325143790 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=ir-translator -o - %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
index 598e91fa0e2f5..c81ac816a3816 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define i32 @call_trunc_no_flags(i64 %a) {
; CHECK-LABEL: name: call_trunc_no_flags
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll
index 8b5d652fb5f7a..9420b052618e0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
declare void @llvm.trap()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
index 983b6d1b4d577..0fc68e9a74e88 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -global-isel -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -O0 -global-isel -stop-after=ir-translator < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
index e1256f118182f..d85beeae883d7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define i64 @vararg(...) #0 {
; CHECK-LABEL: name: vararg
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
index 235137273f851..5f1f2f59c725a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -O0 -mtriple=aarch64-- --global-isel --verify-machineinstrs --stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-- --global-isel --verify-machineinstrs --stop-after=ir-translator %s -o - | FileCheck %s
; Check that vector.deinterleave2 with <1 x float> results does not crash in GlobalISel.
; We used to try to build G_SHUFFLE_VECTOR with a scalar result type, which is not valid.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
index c5cddbae4ed48..d30541b936adb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -O0 -mtriple=aarch64-- --global-isel --verify-machineinstrs --stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-- --global-isel --verify-machineinstrs --stop-after=ir-translator %s -o - | FileCheck %s
define void @vector_interleave2_v4i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: name: vector_interleave2_v4i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
index 137064dc3464a..6738f46596927 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define i64 @call_vscale_i64() {
; CHECK-LABEL: name: call_vscale_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll
index 0a632d45a91cc..b4b744dc68d5c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll
@@ -1,4 +1,4 @@
-; RUN: llc -global-isel -stop-after irtranslator -mtriple aarch64-apple-ios %s -o - | FileCheck %s
+; RUN: llc -global-isel -stop-after ir-translator -mtriple aarch64-apple-ios %s -o - | FileCheck %s
; We use to incorrectly use the store size instead of the alloc size when
; creating the stack slot for allocas. This shows on aarch64 only when
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
index 9ff99dae65fa2..e9aed1f2157fe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -O0 -global-isel -mtriple=aarch64 -stop-after=irtranslator | FileCheck %s
+; RUN: llc < %s -O0 -global-isel -mtriple=aarch64 -stop-after=ir-translator | FileCheck %s
%zero = type [0 x i8]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
index 8a47bd8a062a4..eb5f33017c623 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
define <1 x float> @ret_v1f32(<1 x float> %v) {
; CHECK-LABEL: name: ret_v1f32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
index 3f8144c2c558e..f85d0afcbbae8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
; Tests vectors of i1 types can appropriately extended first before return handles it.
define <4 x i1> @ret_v4i1(ptr %v) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/threadlocal-address.ll b/llvm/test/CodeGen/AArch64/GlobalISel/threadlocal-address.ll
index b0e608edb9f5c..5e07cf2740da3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/threadlocal-address.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/threadlocal-address.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple aarch64-apple-macosx -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple aarch64-apple-macosx -stop-after=ir-translator %s -o - | FileCheck %s
@tls_var = external thread_local global ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index 46271256fc840..b9f787c48c5be 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
%type = type [4 x {i8, i32}]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
index c5748c83bb88a..b741444c6a045 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel -global-isel-abort=1 -stop-after=ir-translator | FileCheck %s
define i128 @func_i128(ptr %ptr) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
index 255b2c6505e79..e19544b93c3bc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -mattr=+sve -global-isel -global-isel-abort=1 -aarch64-enable-gisel-sve=1 \
-; RUN: -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
;; Test the correct usage of the Z registers with multiple SVE arguments.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
index 4e96cc0d9b08f..1bcfe0e3c6f26 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -mattr=+sve -global-isel -global-isel-abort=1 -aarch64-enable-gisel-sve=1 \
-; RUN: -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
;; vscale x 128-bit
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll
index 8c6e01d934c2d..06aa6b1667ab6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-IOS %s
-; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LINUX %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-IOS %s
+; RUN: llc -O0 -stop-after=ir-translator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LINUX %s
declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
index 84ffe3f9e0904..8dc76dde3a4b3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define i12 @v1i12(<1 x i12> %v) {
; CHECK-LABEL: name: v1i12
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
index 50517866173f5..7c2a6008c6cf5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -verify-machineinstrs -o - %s | FileCheck %s
define <2 x half> @f16_vec_param(<2 x half> %v) {
; CHECK-LABEL: name: f16_vec_param
diff --git a/llvm/test/CodeGen/AArch64/dbg-declare-swift-async.ll b/llvm/test/CodeGen/AArch64/dbg-declare-swift-async.ll
index 15eb5f9acfabd..4b08a51584a1e 100644
--- a/llvm/test/CodeGen/AArch64/dbg-declare-swift-async.ll
+++ b/llvm/test/CodeGen/AArch64/dbg-declare-swift-async.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
; RUN: llc -O0 -fast-isel -stop-after=finalize-isel %s -o - | FileCheck %s
; RUN: llc -O0 -fast-isel=false -global-isel=false -stop-after=finalize-isel %s -o - | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/dbg-value-swift-async-non-entry-block.ll b/llvm/test/CodeGen/AArch64/dbg-value-swift-async-non-entry-block.ll
index 02ef2e90092fa..75f33b46d928b 100644
--- a/llvm/test/CodeGen/AArch64/dbg-value-swift-async-non-entry-block.ll
+++ b/llvm/test/CodeGen/AArch64/dbg-value-swift-async-non-entry-block.ll
@@ -1,4 +1,4 @@
-; RUN: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AARCH
+; RUN: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AARCH
; RUN: llc --mtriple="aarch64-" -O0 -fast-isel=false -global-isel=false -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH
; RUN: llc --mtriple="aarch64-" -O0 -fast-isel -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH
diff --git a/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll b/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll
index e52555ba6350a..d5041d6659207 100644
--- a/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll
+++ b/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll
@@ -1,4 +1,4 @@
-; RUN: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AARCH
+; RUN: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AARCH
; RUN: llc --mtriple="aarch64-" -O0 -fast-isel=false -global-isel=false -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH
; RUN: llc --mtriple="aarch64-" -O0 -fast-isel -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH
diff --git a/llvm/test/CodeGen/AArch64/dereferenceable-metadata-mmo.ll b/llvm/test/CodeGen/AArch64/dereferenceable-metadata-mmo.ll
index bff203a6951c0..41150654b0650 100644
--- a/llvm/test/CodeGen/AArch64/dereferenceable-metadata-mmo.ll
+++ b/llvm/test/CodeGen/AArch64/dereferenceable-metadata-mmo.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64 -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -O0 -fast-isel -stop-after=finalize-isel -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -O2 -stop-after=finalize-isel -o - %s | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/memsize-remarks.ll b/llvm/test/CodeGen/AArch64/memsize-remarks.ll
index f256389c7349e..14bf24abc0b63 100644
--- a/llvm/test/CodeGen/AArch64/memsize-remarks.ll
+++ b/llvm/test/CodeGen/AArch64/memsize-remarks.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -pass-remarks-analysis=gisel-irtranslator-memsize -pass-remarks-output=%t.opt.yaml -pass-remarks-filter=gisel-irtranslator-memsize -global-isel -o /dev/null 2>&1 | FileCheck %s --check-prefix=GISEL --implicit-check-not=GISEL
+; RUN: llc %s -pass-remarks-analysis=gisel-ir-translator-memsize -pass-remarks-output=%t.opt.yaml -pass-remarks-filter=gisel-ir-translator-memsize -global-isel -o /dev/null 2>&1 | FileCheck %s --check-prefix=GISEL --implicit-check-not=GISEL
; RUN: cat %t.opt.yaml | FileCheck -check-prefix=YAML %s
source_filename = "memsize.c"
@@ -144,7 +144,7 @@ define void @known_call_with_dereferenceable_bytes(ptr dereferenceable(42) %dst,
; GISEL-NOT: Read Variables:
; GISEL-NEXT: Written Variables: <unknown> (42 bytes).
; YAML: --- !Analysis
-; YAML: gisel-irtranslator-memsize
+; YAML: gisel-ir-translator-memsize
; YAML: Name: MemoryOpIntrinsicCall
; YAML-LABEL: Function: known_call_with_dereferenceable_bytes
; YAML-NEXT: Args:
@@ -176,7 +176,7 @@ define void @known_call_with_dereferenceable_bytes(ptr dereferenceable(42) %dst,
; GISEL-NEXT: Read Variables: <unknown> (314 bytes).
; GISEL-NEXT: Written Variables: <unknown> (42 bytes).
; YAML: --- !Analysis
-; YAML: gisel-irtranslator-memsize
+; YAML: gisel-ir-translator-memsize
; YAML: Name: MemoryOpIntrinsicCall
; YAML-LABEL: Function: known_call_with_dereferenceable_bytes
; YAML-NEXT: Args:
@@ -214,7 +214,7 @@ define void @known_call_with_dereferenceable_bytes(ptr dereferenceable(42) %dst,
; GISEL-NEXT: Read Variables: <unknown> (314 bytes).
; GISEL-NEXT: Written Variables: <unknown> (42 bytes).
; YAML: --- !Analysis
-; YAML: gisel-irtranslator-memsize
+; YAML: gisel-ir-translator-memsize
; YAML: Name: MemoryOpIntrinsicCall
; YAML-LABEL: Function: known_call_with_dereferenceable_bytes
; YAML-NEXT: Args:
@@ -252,7 +252,7 @@ define void @known_call_with_dereferenceable_bytes(ptr dereferenceable(42) %dst,
; GISEL-NOT: Read Variables:
; GISEL-NEXT: Written Variables: <unknown> (42 bytes).
; YAML: --- !Analysis
-; YAML: gisel-irtranslator-memsize
+; YAML: gisel-ir-translator-memsize
; YAML: Name: MemoryOpCall
; YAML-LABEL: Function: known_call_with_dereferenceable_bytes
; YAML-NEXT: Args:
@@ -275,7 +275,7 @@ define void @known_call_with_dereferenceable_bytes(ptr dereferenceable(42) %dst,
; GISEL-NEXT: Read Variables: <unknown> (314 bytes).
; GISEL-NEXT: Written Variables: <unknown> (42 bytes).
; YAML: --- !Analysis
-; YAML: gisel-irtranslator-memsize
+; YAML: gisel-ir-translator-memsize
; YAML: Name: MemoryOpCall
; YAML-LABEL: Function: known_call_with_dereferenceable_bytes
; YAML-NEXT: Args:
diff --git a/llvm/test/CodeGen/AArch64/speculative-load-intrinsic-mmo.ll b/llvm/test/CodeGen/AArch64/speculative-load-intrinsic-mmo.ll
index 58d66f8eb5be8..33ed2d24340d1 100644
--- a/llvm/test/CodeGen/AArch64/speculative-load-intrinsic-mmo.ll
+++ b/llvm/test/CodeGen/AArch64/speculative-load-intrinsic-mmo.ll
@@ -2,7 +2,7 @@
; RUN: -stop-after=finalize-isel < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,SDAG
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve -global-isel \
-; RUN: -aarch64-enable-gisel-sve=1 -stop-after=irtranslator < %s \
+; RUN: -aarch64-enable-gisel-sve=1 -stop-after=ir-translator < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,GISEL
define <4 x i32> @plain(ptr %ptr) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
index 672aec2551c03..f46ac5c0d93e8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=ir-translator -global-isel %s -o - 2>&1 | FileCheck %s
; This file checks that the translation from llvm IR to generic
; MachineInstr is correct.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
index 73bb3a2d5fe95..b06501688514b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.03 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03 -stop-after=ir-translator -o - %s | FileCheck %s
declare align(8) dereferenceable(8) ptr @declared_with_ret_deref() #0
declare align(8) ptr @unknown_decl() #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
index 7ea054e6a7bb7..e765ca0caf9e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu8.03-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu8.03-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
; FIXME: Also test with a pre-gfx8 target.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
index 98b6d6f8da429..85fd5ded9e4d8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=ir-translator -o - %s | FileCheck %s
define <2 x i65> @v2i65_func_void() #0 {
; CHECK-LABEL: name: v2i65_func_void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
index 5e4da6ba777b6..134af09936fbe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00 | FileCheck %s -check-prefixes=GFX9
+; RUN: llc < %s -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00 | FileCheck %s -check-prefixes=GFX9
; tests bf16 argument & return values lowering.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
index 442876257794c..008e1d0e21af7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc --global-isel=1 -mtriple=amdgpu11.00--amdpal -stop-after=irtranslator %s -o - | FileCheck %s --check-prefix=GFX11
-; RUN: llc --global-isel=1 -mtriple=amdgpu10.30--amdpal -stop-after=irtranslator %s -o - | FileCheck %s --check-prefix=GFX10
+; RUN: llc --global-isel=1 -mtriple=amdgpu11.00--amdpal -stop-after=ir-translator %s -o - | FileCheck %s --check-prefix=GFX11
+; RUN: llc --global-isel=1 -mtriple=amdgpu10.30--amdpal -stop-after=ir-translator %s -o - | FileCheck %s --check-prefix=GFX10
declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 })
declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 })
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
index 099c8e1bc0416..d402f605ad9d0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=ir-translator -global-isel %s -o - | FileCheck %s
declare void @llvm.amdgcn.s.sendmsg(i32 immarg, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
index 717f6a10cf691..293cb5b966d55 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=amdgpu8.03-amd-amdhsa -passes=amdgpu-attributor < %s | llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -o - | FileCheck -check-prefix=HSA %s
+; RUN: opt -mtriple=amdgpu8.03-amd-amdhsa -passes=amdgpu-attributor < %s | llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa -amdgpu-ir-lower-kernel-arguments=0 -stop-after=ir-translator -o - | FileCheck -check-prefix=HSA %s
; HSA-LABEL: name: default_kernel
; HSA: liveins:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
index 75cb59e7d75f4..5e602576a3853 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator %s -o - | FileCheck -check-prefix=HSA-VI %s
-; RUN: llc -global-isel -mtriple=amdgpu8.03-- -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator %s -o - | FileCheck -check-prefix=LEGACY-MESA-VI %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa -amdgpu-ir-lower-kernel-arguments=0 -stop-after=ir-translator %s -o - | FileCheck -check-prefix=HSA-VI %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-- -amdgpu-ir-lower-kernel-arguments=0 -stop-after=ir-translator %s -o - | FileCheck -check-prefix=LEGACY-MESA-VI %s
define amdgpu_kernel void @i8_arg(ptr addrspace(1) nocapture %out, i8 %in) nounwind {
; HSA-VI-LABEL: name: i8_arg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
index aa44f28775ced..84df85cc0d4ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.02-mesa-mesa3d -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu8.02-mesa-mesa3d -stop-after=ir-translator %s -o - | FileCheck %s
; Check that we correctly skip over disabled inputs
define amdgpu_ps void @disabled_input(float inreg %arg0, float %psinput0, float %psinput1) #1 {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
index f392820ba6c90..239fac44d7470 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=ir-translator %s -o - | FileCheck %s
define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
; CHECK-LABEL: name: test_f32_inreg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
index b89195526fbb0..6e09102e27a52 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=irtranslator -global-isel -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=ir-translator -global-isel -o - %s | FileCheck %s
; TODO: Could potentially insert it here
define void @arg_align_8(ptr addrspace(1) align 8 %arg0) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
index d0be9b9c66f9f..010ee839253b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.42 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.42 -O0 -stop-after=ir-translator -o - %s | FileCheck %s
define float @test_atomicrmw_fadd(ptr addrspace(3) %addr) {
; CHECK-LABEL: name: test_atomicrmw_fadd
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
index dc89415a08aa1..c6e56c1f7b4b8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -enable-var-scope %s
; Test that we don't insert code to pass implicit arguments we know
; the callee does not need.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
index 347f59a48b3f0..2f5491ddf0329 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope -check-prefix=GFX900 %s
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.08-mesa-mesa3d -o - %s | FileCheck -enable-var-scope -check-prefix=GFX908 %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope -check-prefix=GFX900 %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.08-mesa-mesa3d -o - %s | FileCheck -enable-var-scope -check-prefix=GFX908 %s
; Workitem IDs are passed to the kernel differently for gfx908
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
index 9042850d23ad6..1e54a1d9701f7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
; amdgpu_gfx calling convention
declare hidden amdgpu_gfx void @external_gfx_void_func_void() #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
index 9a48bc379445f..59e817126495f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=ir-translator < %s | FileCheck -check-prefix=GCN %s
declare i1 @external_i1_func_void() #0
declare zeroext i1 @external_i1_zeroext_func_void() #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
index eedfb14b48914..bc859b1ac094f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=ir-translator < %s | FileCheck -check-prefix=GCN %s
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(ptr addrspace(5) sret({ i8, i32 }), ptr addrspace(5) byval({ i8, i32 })) #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
index 2c93907566e8c..03ff6e938f0cf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -stop-after=irtranslator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -global-isel-abort=2 -stop-after=ir-translator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
declare hidden void @external_void_func_void() #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
index addbdde19fd98..afbc6575d624b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -O0 -global-isel -mtriple=amdgpu9.00-amd-amdhsa -stop-after=ir-translator -o - %s | FileCheck %s
; The CSEMIRBuilder was mishandling the result operand when constant
; folding a vector operation, resulting in a missing def for the
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
index 5614e7d422b00..2e28f8dd56021 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=ir-translator -o - %s | FileCheck %s
@var = global i32 poison
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
index 6961a876a5ca3..02bd1976c67a2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=ir-translator %s -o - | FileCheck %s
define float @v_constained_fadd_f32_fpexcept_strict(float %x, float %y) #0 {
; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_strict
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
index 7163695b8606b..3ef761dad2a64 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=ir-translator -global-isel %s -o - | FileCheck %s
; Check flags are preserved for a regular instruction.
; CHECK-LABEL: name: fadd_nnan
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
index 2d60999ff8773..bb863e30509de 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=ir-translator < %s | FileCheck %s
define amdgpu_kernel void @system_one_as_acquire() {
; CHECK-LABEL: name: system_one_as_acquire
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
index 0feb2d76f0074..df6ea0920ab85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck --check-prefix=FIXED %s
+; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=ir-translator -o - %s | FileCheck --check-prefix=FIXED %s
; Make sure arg1 is not allocated in v31, which is reserved for
; workitem IDs with -amdgpu-fixed-function-abi.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
index 25f952df63f29..b89257cfeecb1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
@@ -2,7 +2,7 @@
; Note update_mir_test_checks does not support generating checks for
; the frame info, so some functions have manually added stack object
; checks.
-; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=irtranslator -global-isel -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu8.03 -O0 -stop-after=ir-translator -global-isel -o - %s | FileCheck %s
; FIXME: pre-VI should have same ABI without legal i16 operations.
define void @void_func_empty_arg({} %arg0, i32 %arg1) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
index c03392d5423e6..1caafbc71e2a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel -mtriple=amdgpu8.03 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03 -stop-after=ir-translator -o - %s | FileCheck %s
define void @void_func_v2i65(<2 x i65> %arg0) #0 {
; CHECK-LABEL: name: void_func_v2i65
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
index fd7b7056ad57d..b689c7eccaa1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=ir-translator -o - %s | FileCheck %s
; Test 64-bit pointer with 64-bit index
define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_v2i64(<2 x ptr addrspace(1)> %ptr, <2 x i64> %idx) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
index 18411967bcaa5..384a408ec6185 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
define amdgpu_kernel void @test_indirect_call_sgpr_ptr(ptr %fptr) {
; CHECK-LABEL: name: test_indirect_call_sgpr_ptr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
index 026f43ba0655e..fbe19b87b085d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
define amdgpu_kernel void @asm_convergent() convergent{
; CHECK-LABEL: name: asm_convergent
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
index 418ca159196e0..ef89a93cbe10c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -simplify-mir -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -simplify-mir -global-isel -mtriple=amdgpu6.00 -stop-after=ir-translator %s -o - | FileCheck %s
; Check the flags set on the memory operands for loads determined to
; be constants by alias analysis.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
index 46498710bafc9..985c4853e3f91 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00 -O0 -stop-after=ir-translator %s -o - | FileCheck %s
; Size operand should be the minimum of the two pointer sizes.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
index 1c6c52e0be081..2ac07a6907f63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00 -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00 -stop-after=ir-translator -o - %s | FileCheck %s
; Make sure intrinsics with metadata arguments are translated
define i32 @reloc_constant() {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
index fddf215dd272a..56b003f0db710 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - -stop-after=ir-translator < %s | FileCheck %s
define <2 x ptr addrspace(7)> @no_auto_constfold_gep_vector() {
; CHECK-LABEL: name: no_auto_constfold_gep_vector
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
index 944604bc8d727..bdbdb7b954f88 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - -stop-after=irtranslator %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - -stop-after=ir-translator %s | FileCheck %s
; Check that the CSEMIRBuilder doesn't fold away the getelementptr during IRTranslator
define ptr addrspace(7) @no_auto_constfold_gep() {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
index 3629f6361ed03..a507d8c599305 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=ir-translator < %s | FileCheck %s
define void @prefetch_read(ptr %ptr) {
; CHECK-LABEL: name: prefetch_read
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
index 31da8e7c7179d..2474bb2d0ae7d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=ir-translator < %s | FileCheck %s
define ptr @ptrmask_flat_i64(ptr %ptr, i64 %mask) {
; CHECK-LABEL: name: ptrmask_flat_i64
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
index 3e05ed51ea1bf..ae280dda8300e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
; Make sure that an intrinsic declaration that has side effects, but
; called with a readnone call site is translated to
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
index 55b4188ddbda0..1fb306fb2cf28 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu6.00 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu6.00 -global-isel -stop-after=ir-translator %s -o - | FileCheck %s
define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) {
; CHECK-LABEL: name: uaddsat_i16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
index 85ec50d5f73ca..1fbeacb024ec0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; This is a copy of sibling-call.ll, but stops after the IRTranslator.
define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
index ad3424e82475f..861d1b1d71cab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
index 27de5521fc859..f7270ca094d67 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -enable-var-scope %s
declare hidden void @external_void_func_void()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
index 27dd893b68386..1a3be34e03bd7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=ir-translator -global-isel %s -o - | FileCheck %s
define i8 @f_i1_1() {
; CHECK-LABEL: name: f_i1_1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
index a3caff4c1e04e..f7c0e7d9e6230 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgpu9.0a -O0 -global-isel=true --stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.0a -O0 -global-isel=true --stop-after=ir-translator -o - %s | FileCheck %s
declare ptr @llvm.invariant.start.p5(i64 immarg, ptr addrspace(5) nocapture)
declare void @llvm.invariant.end.p5(ptr, i64 immarg, ptr addrspace(5) nocapture)
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
index aab2968ae7e20..a701557105551 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
@@ -1,5 +1,5 @@
; Test the generation of the attribute amdgpu-no-flat-scratch-init
-; RUN: opt -S -O2 -mtriple=amdgpu10.10-amd-amdhsa %s | llc -global-isel -stop-after=irtranslator | FileCheck -check-prefixes=GFX10 %s
+; RUN: opt -S -O2 -mtriple=amdgpu10.10-amd-amdhsa %s | llc -global-isel -stop-after=ir-translator | FileCheck -check-prefixes=GFX10 %s
;; tests of addrspacecast
diff --git a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
index 78909952aeb70..d0ed15514b24e 100644
--- a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
+++ b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
@@ -1,6 +1,6 @@
; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s
; RUN: llc -stop-after=dead-mi-elimination -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,DEADMI %s
-; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-- -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc -global-isel -stop-after=ir-translator -mtriple=amdgpu9.00-- -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL
; CHECK-LABEL: name: basic_call
; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ENTRY
diff --git a/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
index f69e16ac38f16..b247bffba2d8b 100644
--- a/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=1 -mtriple=amdgpu12.00--amdpal -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00--amdpal -stop-after=ir-translator < %s | FileCheck %s
define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; CHECK-LABEL: name: basic_test
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
index 290b5b8a298f9..c6942cf0a8a37 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=NOV4T
-; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=V4T
-; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=V5T
-; RUN: llc -mtriple thumb-unknown -mattr=+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=THUMB
+; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=NOV4T
+; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=V4T
+; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=V5T
+; RUN: llc -mtriple thumb-unknown -mattr=+v6t2 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=THUMB
define arm_aapcscc void @test_indirect_call(ptr %fptr) {
; NOV4T-LABEL: name: test_indirect_call
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index 7df230ccda67e..7ceda4dab83f8 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
-; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
+; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
+; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
index 65586f72c7c19..7f38dec1f0375 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE
-; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
-; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
+; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE
+; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
+; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
declare arm_aapcscc ptr @simple_reg_params_target(i32, ptr)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
index daae1b7a094e7..684e56bd4d945 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM
-; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=THUMB
+; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM
+; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=THUMB
declare arm_aapcscc i32 @int_varargs_target(i32, ...)
diff --git a/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
index 031e82dcb67bd..62d0cb54f043b 100644
--- a/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
+++ b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs < %s | FileCheck --check-prefix=ISEL %s
; CHECK: name: f
diff --git a/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll b/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
index 9d91ff55d6916..225463fdadb02 100644
--- a/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+++ b/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
@@ -3,9 +3,9 @@
; REQUIRES: amdgpu-registered-target
; REQUIRES: x86-registered-target
-; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AARCH64
-; RUN: llc -mtriple=amdgpu6.00--mesa-mesa3d -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AMDGPU
-; RUN: llc -mtriple=x86_64-linux-gnu -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=X86
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=ir-translator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AARCH64
+; RUN: llc -mtriple=amdgpu6.00--mesa-mesa3d -O0 -stop-after=ir-translator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AMDGPU
+; RUN: llc -mtriple=x86_64-linux-gnu -O0 -stop-after=ir-translator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=X86
; IRTranslator handling of LLVM IR's byte type (bN), constants and loads /
; stores of byte values, and bitcasts to/from byte types. Byte values are
diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
index b0b038344ebc7..da83c10ec7368 100644
--- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=m68k -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=m68k -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
%struct.A = type { i8, i16, i32 }
diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-pic.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-pic.ll
index fa50b568715de..f36d0740d2aaf 100644
--- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-pic.ll
+++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-pic.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=m68k --relocation-model=pic -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=m68k --relocation-model=pic -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s
define void @test_pic() nounwind {
; CHECK-LABEL: name: test_pic
diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
index 0504792c3fceb..2cba209defb8c 100644
--- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
+++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -mtriple=m68k -global-isel -stop-after=ir-translator < %s | FileCheck %s
; CHECK: name: noArgRetVoid
diff --git a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
index 06f42bdd23edf..4de06496e2a55 100644
--- a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
@@ -1,7 +1,7 @@
-# RUN: llc < %s -O0 -mtriple=aarch64-none-linux-gnu -mattr=+pauth -run-pass irtranslator -x mir | \
+# RUN: llc < %s -O0 -mtriple=aarch64-none-linux-gnu -mattr=+pauth -run-pass ir-translator -x mir | \
# RUN: llc -x mir -run-pass legalizer | FileCheck %s
# RUN: llc < %s -O0 -mtriple=aarch64-none-linux-gnu -mattr=+pauth -x mir \
-# RUN: -passes='require<libcall-lowering-info>,function(machine-function(irtranslator,legalizer))' | \
+# RUN: -passes='require<libcall-lowering-info>,function(machine-function(ir-translator,legalizer))' | \
# RUN: FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
index 953a13389f9d8..2083b694f67b8 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-- -global-isel -run-pass=irtranslator -simplify-mir %s -o %t \
+# RUN: llc -mtriple=aarch64-- -global-isel -run-pass=ir-translator -simplify-mir %s -o %t \
# RUN: -verify-machineinstrs; llc -mtriple=aarch64-- -run-pass=legalizer \
# RUN: -simplify-mir %t -x mir -o - -verify-machineinstrs | FileCheck %s
diff --git a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
index 69e54ba5cdb4f..8c215c2989523 100644
--- a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
+++ b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -march aarch64 -global-isel -stop-after=irtranslator -o - %s | llc -x mir -march aarch64 -run-pass=none -o - | FileCheck %s
+; RUN: llc -O0 -march aarch64 -global-isel -stop-after=ir-translator -o - %s | llc -x mir -march aarch64 -run-pass=none -o - | FileCheck %s
define i16 @unnamed_stack() {
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
index 9884b996ce08c..5339e55259220 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define i32 @add_i32(i32 %x, i32 %y) {
; MIPS32-LABEL: name: add_i32
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
index 1d912ff3c14a5..bc795fe5f0a16 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define { float, float } @add_complex_float(ptr %a, ptr %b) {
; MIPS32-LABEL: name: add_complex_float
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
index 97621f6e54ab5..eb4165d6a3016 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
@@ -1,7 +1,7 @@
-; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,BE,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,LE,FP32
-; RUN: llc -O0 -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,BE,FP64
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,LE,FP64
+; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,BE,FP32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,LE,FP32
+; RUN: llc -O0 -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,BE,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,LE,FP64
; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - > /dev/null
; RUN: llc -O0 -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - > /dev/null
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
index fa34ea403085e..8f1f678e3c17e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define i32 @shl(i32 %a) {
; MIPS32-LABEL: name: shl
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
index fb8e47e10b12f..7607a25aaebbc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -relocation-model=pic -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -relocation-model=pic -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
declare i32 @f(i32 %a, i32 %b);
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
index 8c6dfb40e4fb5..5e8743659b463 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
-; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mips-linux-gnu -global-isel -global-isel-abort=1 -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define signext i8 @sext_arg_i8(i8 signext %a) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
index d2af56cd8eace..d8212c9a3a38d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
define float @float_in_fpr(float %a, float %b) {
; FP32-LABEL: name: float_in_fpr
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
index cc21b55851388..5274729977782 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
index a61e24610292d..b6d9474d3fa4a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -relocation-model=pic -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -relocation-model=pic -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
declare i32 @f(i32 %a, i32 %b);
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
index 60bd5925cf2ab..a9d44c946f6d4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define i32 @ptr_arg_in_regs(ptr %p) {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll
index a8e710c63c8d3..e47dde05b9108 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/ret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define void @void() {
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
index 5a2c8f05b2137..d85c63774d064 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define i64 @i64_reg(i64 %a) {
; MIPS32-LABEL: name: i64_reg
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
index 8a0f4829023ec..ef1d59e936492 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
%struct.S = type { i32, i32 }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
index 5bf2d4ded8dcd..d549afab2126e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
declare i32 @f(i32, i32, i32, i32, i32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
index 16e848780a1d6..d27e0a96ef2d9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
index 021a7090ab942..1dfdeb40737da 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
-; RUN: -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
; Passing ppc_fp128 in registers (in fp registers as f64)
define void @test_ppc_fp128_1(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d, ppc_fp128 %e) {
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
index 26a2457dd2bca..0267d47f43a76 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
-; RUN: -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
; Mixed parameter passing involving integers, floats, vectors (all in registers).
define void @test_mixed_arg1(i32 %a, i32 %b, i32 %c, <4 x i32> %d) {
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
index 4aa55a94db7d7..00b966e552690 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
-; RUN: -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
; Pass up to eight integer arguments in registers.
define void @test_scalar1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
index 9d0188e76e3e7..d3f7b799dff49 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
-; RUN: -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
; Pass up to twelve vector arguments in registers.
define void @test_vec1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h, <4 x i32> %i, <4 x i32> %j, <4 x i32> %k, <4 x i32> %l) {
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll
index a3c909cb9fd0c..6b7751a58903c 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -verify-machineinstrs -stop-after=ir-translator < %s | FileCheck %s
%struct.A = type { i8, float, i32, i32, i32 }
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator-stackprotect.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator-stackprotect.ll
index a091c6fbb7755..07a6dd0fc23ce 100644
--- a/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator-stackprotect.ll
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator-stackprotect.ll
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux %s -global-isel -stop-after=irtranslator -o - | FileCheck %s --check-prefix=LINUX
-; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-openbsd %s -global-isel -stop-after=irtranslator -o - | FileCheck %s --check-prefix=OPENBSD
+; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux %s -global-isel -stop-after=ir-translator -o - | FileCheck %s --check-prefix=LINUX
+; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-openbsd %s -global-isel -stop-after=ir-translator -o - | FileCheck %s --check-prefix=OPENBSD
; The stack guard on Linux
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll
index 33f34705c3012..ba4635e0bcc75 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define void @foo() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll
index c5bbc15aaff7e..897f721781e49 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -O0 -global-isel -stop-after=ir-translator -o - %s | FileCheck %s
define void @test_simple_memory_clobber() {
; CHECK-LABEL: name: test_simple_memory_clobber
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll
index 127ba6b804864..f4c2f00e3557d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel %s -o - -stop-after=ir-translator | FileCheck %s
; Test that single scalable vector alloca works and store
define void @test_single_scalable_alloca() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll
index fda08d91dc3a2..d6cb2c9c7335c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define void @test_args_i8(i8 %a) {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
index c3a8c7a9aff02..1b3d8f5cffbee 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
-; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IZFH %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
-; RUN: llc -mtriple=riscv64 -mattr=+zfh -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zfh -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IZFH %s
define half @callee_half_in_regs(half %x) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
index b87cc7869a467..e7eb45428dd20 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I,ILP32 %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I,ILP32F %s
; This file contains tests that should have identical output for the ilp32,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index cc73e19f5b60b..96d21273f63d0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I,ILP32 %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I,ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I,ILP32D %s
; This file contains tests that should have identical output for the ilp32,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
index 93649b5f60f7b..e6f29d0c85b16 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s
; Any tests that would have identical output for some combination of the ilp32*
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
index 4d487eb5cda23..4b8c293bbf782 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32-ILP32D %s
; This file contains tests that will have differing output for the ilp32/ilp32f
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
index a9c603bfdd743..a3141000ec346 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32D %s
; This file contains tests that should have identical output for the ilp32f
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
index e4d1d3132ea45..7ba1fbcf660e0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I,LP64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I,LP64F %s
; This file contains tests that should have identical output for the lp64 and
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
index 6f40942b8fcb6..b32db920c0618 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I,LP64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I,LP64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I,LP64D %s
; This file contains tests that should have identical output for the lp64,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
index 9283f1f090ed5..0a7ba9998db90 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64F %s
; Any tests that would have identical output for some combination of the lp64*
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
index 3d7ae6802fc4a..2edd281f3393a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \
-; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; This file contains tests that should have identical output for the lp64 and
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
index 8a2f54691c088..102b8c21d6487 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
declare void @void_noargs()
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fixed-vectors-calling-conv.ll
index bb717e84af742..105ef79d57cf6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fixed-vectors-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fixed-vectors-calling-conv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel -mtriple=riscv64 -mattr=+v -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=riscv64 -mattr=+v -stop-after=ir-translator -verify-machineinstrs < %s | FileCheck %s
define <4 x i8> @ret_v4i8(ptr %p) {
; CHECK-LABEL: name: ret_v4i8
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll
index a1347d2306cad..b72890ddc5cd8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
define <vscale x 1 x i1> @insertelement_nxv1i1_0() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll
index 020f171076995..f088dbbeea75f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64 %s
define void @va1arg(ptr %a, ...) {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/ret.ll
index 5870ca08be9b5..39d4a84dbd59a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/ret.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/ret.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define void @test_ret_void() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
index 3ce62e7909f39..278aa50c9237f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
define <vscale x 1 x i1> @shufflevector_nxv1i1_0() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
index 676d8a844ab81..38d1830fb0674 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
define <vscale x 1 x i1> @splat_zero_nxv1i1() {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
index cd1e95e88ab8a..7b3f12d59972a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define void @test_va_copy(ptr %dest_list, ptr %src_list) {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
index ad1544db84391..c18972c5fad85 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,ILP32 %s
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32 %s
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32f \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -mattr=+d -target-abi ilp32f \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32F %s
-; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32d \
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=ir-translator -mattr=+d -target-abi ilp32d \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32D %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,LP64 %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64f \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -mattr=+d -target-abi lp64f \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,LP64F %s
-; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64d \
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=ir-translator -mattr=+d -target-abi lp64d \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,LP64D %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
index 90ed020e4c315..09949215234ef 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
; The purpose of this test is to show that the compiler throws an error when
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
index ce73b914d657c..2b837d11e413f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
; The purpose of this test is to show that the compiler throws an error when
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
index 1a99dac7d8a4c..8dbcd802b0ddd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
; ==========================================================================
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll
index 31b3c3fe3c5be..df2991d7f14ca 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
define <vscale x 1 x i8> @vload_nx1i8(ptr %pa) {
; RV32-LABEL: name: vload_nx1i8
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll
index 73cfed184c425..0b2983bb4a63e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
; The purpose of this test is to show that the compiler throws an error when
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll
index a775b00d54757..4483f85c11e3a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
; The purpose of this test is to show that the compiler throws an error when
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll
index 73b0d3a173b72..68ad5b7d16d4e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=ir-translator \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
; ==========================================================================
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
index 5a9cfd4d55cf5..7ae0be6a32bd7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=ir-translator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=ir-translator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
define void @vstore_nx1i8(ptr %pa, <vscale x 1 x i8> %b) {
; RV32-LABEL: name: vstore_nx1i8
diff --git a/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll b/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
index 1007404411d8f..ca903e5600e1e 100644
--- a/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
+++ b/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
@@ -18,7 +18,7 @@
; Origin data type of the value.
; CHECK-IR-DAG: ![[#MD2]] = !{{[{]}}{{[{]}} i32, i1 {{[}]}} poison{{[}]}}
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -print-after=irtranslator 2>&1 | FileCheck %s --check-prefix=CHECK-GMIR
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -print-after=ir-translator 2>&1 | FileCheck %s --check-prefix=CHECK-GMIR
; Required info succeeded to get through IRTranslator.
; CHECK-GMIR: %[[phires:.*]]:_(s32) = G_PHI
; CHECK-GMIR: %[[math:.*]]:id(s32), %[[ov:.*]]:_(s1) = G_UADDO %[[phires]]:_, %[[#]]:_
diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll b/llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll
index fcf9581e4b648..7bdc87e2ef8e3 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -stop-after=irtranslator -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -stop-after=ir-translator -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: @__spirv_BuiltInLocalInvocationId = external addrspace(1) global ptr addrspace
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
index 6c4675f79087d..24cc837d5afdc 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=NO-SIMD
-; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
-; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16
+; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=NO-SIMD
+; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
+; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16
define void @test_v16i8_arg(<16 x i8> %arg) {
; NO-SIMD-LABEL: name: test_v16i8_arg
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
index 8668b1d9539f8..a6970c386cf58 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
define swiftcc void @test_implicit_self_and_error(float %arg) {
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
index 97413111536be..844a74686eaea 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
define void @test_i8_arg(i8 %arg) {
; CHECK-LABEL: name: test_i8_arg
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll
index 5a1a4fc8f3c68..ba887f6e6f603 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=-simd128,-multivalue -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32,WASM32-BASIC
-; RUN: llc -mtriple=wasm64 -mattr=-simd128,-multivalue -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64,WASM64-BASIC
-; RUN: llc -mtriple=wasm32 -mattr=+simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32,MULTIVAL-SIMD,WASM32-MULTIVAL-SIMD
-; RUN: llc -mtriple=wasm64 -mattr=+simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64,MULTIVAL-SIMD,WASM64-MULTIVAL-SIMD
+; RUN: llc -mtriple=wasm32 -mattr=-simd128,-multivalue -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM32,WASM32-BASIC
+; RUN: llc -mtriple=wasm64 -mattr=-simd128,-multivalue -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM64,WASM64-BASIC
+; RUN: llc -mtriple=wasm32 -mattr=+simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM32,MULTIVAL-SIMD,WASM32-MULTIVAL-SIMD
+; RUN: llc -mtriple=wasm64 -mattr=+simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM64,MULTIVAL-SIMD,WASM64-MULTIVAL-SIMD
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
index e0bd8c8510d83..27761e5dabc66 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=WASM32-NOMULTIVAL
-; RUN: llc -mtriple=wasm64 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=WASM64-NOMULTIVAL
-; RUN: llc -mtriple=wasm32 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM32-MULTIVAL
-; RUN: llc -mtriple=wasm64 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM64-MULTIVAL
+; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=WASM32-NOMULTIVAL
+; RUN: llc -mtriple=wasm64 -mattr=-simd128 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=WASM64-NOMULTIVAL
+; RUN: llc -mtriple=wasm32 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM32-MULTIVAL
+; RUN: llc -mtriple=wasm64 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM64-MULTIVAL
define i128 @test_ret_i128() {
; WASM32-NOMULTIVAL-LABEL: name: test_ret_i128
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
index 3bc6aaaa3d48c..19192f94cc427 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
define void @test_ret_void() {
; CHECK-LABEL: name: test_ret_void
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
index e0eb097ad78e4..e38d059c8ac84 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=+simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,NO-FP16
-; RUN: llc -mtriple=wasm32 -mattr=+fp16,+simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,FP16
+; RUN: llc -mtriple=wasm32 -mattr=+simd128 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,NO-FP16
+; RUN: llc -mtriple=wasm32 -mattr=+fp16,+simd128 -global-isel -stop-after=ir-translator < %s | FileCheck %s -check-prefixes=CHECK,FP16
define <16 x i8> @test_ret_v16i8() {
; CHECK-LABEL: name: test_ret_v16i8
diff --git a/llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll b/llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
index f99a0b4d273c2..2385fb8c865a0 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -global-isel -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -global-isel -stop-after=ir-translator < %s | FileCheck %s
define i16 @test_bitextract(b32 %src, i32 %off) {
; CHECK-LABEL: name: test_bitextract
; CHECK: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/X86/GlobalISel/callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
index ab8880734afe0..2d8cb14dbb695 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -enable-cse-in-irtranslator=0 -enable-cse-in-legalizer=0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32
-; RUN: llc -enable-cse-in-irtranslator=0 -enable-cse-in-legalizer=0 -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64
+; RUN: llc -enable-cse-in-ir-translator=0 -enable-cse-in-legalizer=0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32
+; RUN: llc -enable-cse-in-ir-translator=0 -enable-cse-in-legalizer=0 -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64
define i32 @test_ret_i32() {
; X32-LABEL: test_ret_i32:
diff --git a/llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll b/llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
index a1d4ca1c02df8..23ea135d923f1 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=i686-pc-win32 -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -global-isel -mtriple=i686-pc-win32 -stop-after=ir-translator %s -o - | FileCheck %s
; inalloca and preallocated formal arguments used to crash CallLowering with
; an isByVal() assertion in setByValSize; check they translate instead.
diff --git a/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll b/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
index 5e9311559b400..344dec7da2c7b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -o - -global-isel %s -stop-after=irtranslator | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux-gnu -o - -global-isel %s -stop-after=ir-translator | FileCheck %s
define <4 x i1> @foo() {
; CHECK-LABEL: name: foo
diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
index 70a2a9e578342..a51189c87d0b6 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -O0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -stop-after=irtranslator < %s | FileCheck %s --check-prefix=X86
-; RUN: llc -O0 -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -O0 -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -stop-after=ir-translator < %s | FileCheck %s --check-prefix=X86
+; RUN: llc -O0 -mtriple=x86_64-linux-gnu -global-isel -stop-after=ir-translator < %s | FileCheck %s --check-prefix=X64
@a1_8bit = external global i8
@a7_8bit = external global i8
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll b/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll
index e4b9fac7334e0..37ac303c0b3f0 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=x86_64-linux-gnux32 -stop-after=irtranslator -verify-machineinstrs < %s -o - | FileCheck -check-prefix=X32ABI %s
+; RUN: llc -global-isel -mtriple=x86_64-linux-gnux32 -stop-after=ir-translator -verify-machineinstrs < %s -o - | FileCheck -check-prefix=X32ABI %s
define ptr @ret_ptr() {
; X32ABI-LABEL: name: ret_ptr
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
index 2f1f8bc63aa4f..cafb751ee228b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=ir-translator < %s -o - | FileCheck %s --check-prefix=ALL
%struct.f1 = type { float }
%struct.d1 = type { double }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
index 18907c0c40045..8a5bb3b7aecbe 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after=ir-translator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
define i8 @zext_i1_to_i8(i1 %val) {
; CHECK-LABEL: name: zext_i1_to_i8
diff --git a/llvm/test/Other/print-changed-machine.ll b/llvm/test/Other/print-changed-machine.ll
index b30e1f4a8771f..7b2b9b3c10d95 100644
--- a/llvm/test/Other/print-changed-machine.ll
+++ b/llvm/test/Other/print-changed-machine.ll
@@ -5,7 +5,7 @@
; RUN: --implicit-check-not='(cseinfo)' --implicit-check-not='Free MachineFunction'
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-print-funcs=foo %s 2>&1 | FileCheck %s --check-prefixes=VERBOSE,NO-BAR
-; VERBOSE: *** IR Dump After IRTranslator (irtranslator) on foo ***
+; VERBOSE: *** IR Dump After IRTranslator (ir-translator) on foo ***
; VERBOSE-NEXT: # Machine code for function foo: IsSSA, TracksLiveness{{$}}
; VERBOSE-NEXT: Function Live Ins: $w0
; VERBOSE-EMPTY:
@@ -17,29 +17,29 @@
; VERBOSE-EMPTY:
; VERBOSE-NEXT: bb.1.entry:
-; VERBOSE-BAR: *** IR Dump After IRTranslator (irtranslator) on bar ***
+; VERBOSE-BAR: *** IR Dump After IRTranslator (ir-translator) on bar ***
; NO-BAR-NOT: on bar ***
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet %s 2>&1 | FileCheck %s --check-prefix=QUIET
-; QUIET: *** IR Dump After IRTranslator (irtranslator) on foo ***
+; QUIET: *** IR Dump After IRTranslator (ir-translator) on foo ***
; QUIET-NOT: ***
; QUIET: *** IR Dump After Localizer (localizer) on foo ***
-; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=irtranslator,legalizer %s 2>&1 | \
+; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=ir-translator,legalizer %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=VERBOSE-FILTER
-; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet -filter-passes=irtranslator %s 2>&1 | \
+; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet -filter-passes=ir-translator %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=QUIET-FILTER --implicit-check-not='IR Dump'
-; VERBOSE-FILTER: *** IR Dump After IRTranslator (irtranslator) on foo ***
+; VERBOSE-FILTER: *** IR Dump After IRTranslator (ir-translator) on foo ***
; VERBOSE-FILTER: *** IR Dump After AArch64O0PreLegalizerCombiner (aarch64-O0-prelegalizer-combiner) on foo filtered out ***
; VERBOSE-FILTER: *** IR Dump After Legalizer (legalizer) on foo ***
; VERBOSE-FILTER-NOT: *** IR Dump After {{.*}} () on
-; QUIET-FILTER: *** IR Dump After IRTranslator (irtranslator) on foo ***
-; QUIET-FILTER: *** IR Dump After IRTranslator (irtranslator) on bar ***
-; QUIET-FILTER: *** IR Dump After IRTranslator (irtranslator) on atomic_load ***
-; QUIET-FILTER: *** IR Dump After IRTranslator (irtranslator) on lr ***
+; QUIET-FILTER: *** IR Dump After IRTranslator (ir-translator) on foo ***
+; QUIET-FILTER: *** IR Dump After IRTranslator (ir-translator) on bar ***
+; QUIET-FILTER: *** IR Dump After IRTranslator (ir-translator) on atomic_load ***
+; QUIET-FILTER: *** IR Dump After IRTranslator (ir-translator) on lr ***
;; dot-cfg/dot-cfg-quiet are unimplemented. Currently they behave like 'quiet'.
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=dot-cfg %s 2>&1 | FileCheck %s --check-prefix=QUIET
More information about the llvm-commits
mailing list