[llvm] [VPlan] Encode single-scalar-ness of VPInstruction in a field (NFC). (PR #227761)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 08:49:54 PDT 2026
https://github.com/fhahn created https://github.com/llvm/llvm-project/pull/227761
Add a dedicated field to VPInstruction to encode whether it produces a single scalar.
The goal is to remove the hard-coded opcodes in isSingleScalar and support opcodes both as single-scalar and vector.
The initial version just uses it for casts, to enable using VPInstruction for VPWidenCastRecipe (https://github.com/llvm/llvm-project/pull/129712)
Other single-scalar opcodes (PHI, Load, Intrinsic, ExplicitVectorLength, ResumeForEpilogue) are still derived from the opcodes and will be transitioned later.
>From 654f8f47ff521cc7013c410d3646d1a60de8ad9d Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Thu, 2 Jul 2026 16:27:26 +0100
Subject: [PATCH] [VPlan] Encode single-scalar-ness of VPInstruction in a field
(NFC).
Add a dedicated field to VPInstruction to encode whether it produces a
single scalar.
The goal is to remove the hard-coded opcodes in isSingleScalar and
support opcodes both as single-scalar and vector.
The initial version just uses it for casts, to enable using
VPInstruction for VPWidenCastRecipe (https://github.com/llvm/llvm-project/pull/129712)
Other single-scalar opcodes (PHI, Load, Intrinsic, ExplicitVectorLength,
ResumeForEpilogue) are still derived from the opcodes and will be
transitioned later.
---
.../Vectorize/LoopVectorizationPlanner.h | 5 +++--
llvm/lib/Transforms/Vectorize/VPlan.h | 11 ++++++++---
llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp | 11 +++++++----
.../VPlan/AArch64/vplan-memory-op-decisions.ll | 6 +++---
.../LoopVectorize/VPlan/constant-fold.ll | 2 +-
.../VPlan/scalarize-irregular-type-memops.ll | 4 ++--
.../VPlan/vplan-based-stride-mv.ll | 18 +++++++++---------
.../VPlan/vplan-printing-branch-weights.ll | 8 ++++----
.../VPlan/vplan-scev-address-idioms.ll | 4 ++--
.../LoopVectorize/VPlan/widen_mem_idioms.ll | 2 +-
10 files changed, 40 insertions(+), 31 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
index 733b8647a06e3..806fb9fd15eea 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
@@ -441,7 +441,7 @@ template <typename InserterTy> class VPBuilderBase : public InserterTy {
const VPIRMetadata &Metadata = {}) {
return tryInsertInstruction(new VPInstruction(
Opcode, Op, Flags.value_or(VPIRFlags::getDefaultFlags(Opcode)),
- Metadata, DL, "", ResultTy));
+ Metadata, DL, "", ResultTy, /*IsSingleScalar=*/true));
}
/// Create a scalar call to the intrinsic \p IntrinsicID with \p Operands, and
@@ -507,7 +507,8 @@ template <typename InserterTy> class VPBuilderBase : public InserterTy {
if (Instruction::isCast(Opcode)) {
assert(!Mask && "Cast cannot be predicated");
auto *VPI = new VPInstruction(Opcode, Operands, Flags, Metadata, DL,
- UV->getName(), ResultTy);
+ UV->getName(), ResultTy,
+ /*IsSingleScalar=*/true);
VPI->setUnderlyingValue(UV);
return VPI;
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index aa93dbaa65170..c105c90936a70 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1432,6 +1432,10 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags,
/// An optional name that can be used for the generated IR instruction.
std::string Name;
+ /// Whether this VPInstruction produces a single scalar value, for opcodes
+ /// where it cannot be derived from the opcode.
+ const bool IsSingleScalar;
+
/// Returns true if we can generate a scalar for the first lane only if
/// needed.
bool doesGenerateSingleScalar() const;
@@ -1459,7 +1463,7 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags,
VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands,
const VPIRFlags &Flags = {}, const VPIRMetadata &MD = {},
DebugLoc DL = DebugLoc::getUnknown(), const Twine &Name = "",
- Type *ResultTy = nullptr);
+ Type *ResultTy = nullptr, bool IsSingleScalar = false);
VP_CLASSOF_IMPL(VPRecipeBase::VPInstructionSC)
@@ -1469,8 +1473,9 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags,
VPInstruction *cloneWithOperands(ArrayRef<VPValue *> NewOperands,
Type *ResultTy = nullptr) {
- auto *New = new VPInstruction(Opcode, NewOperands, *this, *this,
- getDebugLoc(), Name, ResultTy);
+ auto *New =
+ new VPInstruction(Opcode, NewOperands, *this, *this, getDebugLoc(),
+ Name, ResultTy, IsSingleScalar);
if (getUnderlyingValue())
New->setUnderlyingValue(getUnderlyingInstr());
return New;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index ae9001dc8c67f..e97884f86449a 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -607,13 +607,15 @@ Type *VPReplicateRecipe::computeScalarType(const Instruction *I,
VPInstruction::VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands,
const VPIRFlags &Flags, const VPIRMetadata &MD,
- DebugLoc DL, const Twine &Name, Type *ResultTy)
+ DebugLoc DL, const Twine &Name, Type *ResultTy,
+ bool IsSingleScalar)
: VPRecipeWithIRFlags(
VPRecipeBase::VPInstructionSC, Operands,
ResultTy ? ResultTy
: computeScalarTypeForInstruction(Opcode, Operands),
Flags, DL),
- VPIRMetadata(MD), Opcode(Opcode), Name(Name.str()) {
+ VPIRMetadata(MD), Opcode(Opcode), Name(Name.str()),
+ IsSingleScalar(IsSingleScalar) {
assert(flagsValidForOpcode(getOpcode()) &&
"Set flags not supported for the provided opcode");
assert(hasRequiredFlagsForOpcode(getOpcode(), getScalarType()) &&
@@ -720,7 +722,8 @@ bool VPInstruction::doesGenerateSingleScalar() const {
case VPInstruction::Not:
return vputils::onlyFirstLaneUsed(this);
default:
- return Instruction::isBinaryOp(Opcode) && vputils::onlyFirstLaneUsed(this);
+ return (Instruction::isBinaryOp(Opcode) || Instruction::isCast(Opcode)) &&
+ vputils::onlyFirstLaneUsed(this);
}
}
@@ -1623,7 +1626,7 @@ bool VPInstruction::isSingleScalar() const {
case VPInstruction::Intrinsic:
return true;
default:
- return Instruction::isCast(getOpcode());
+ return IsSingleScalar;
}
}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
index af2978f1bfab4..043446ac98854 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
@@ -25,7 +25,7 @@ define void @replicating_load_used_as_store_addr(ptr noalias %A) {
; CHECK-NEXT: EMIT ir<%iv.next> = add ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%gep.A> = getelementptr ir<%A>, ir<%iv>
; CHECK-NEXT: REPLICATE ir<%l.p> = load ir<%gep.A>
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.trunc> = trunc ir<%iv.next> to i32
+; CHECK-NEXT: EMIT ir<%iv.trunc> = trunc ir<%iv.next> to i32
; CHECK-NEXT: EMIT store ir<%iv.trunc>, ir<%l.p>
; CHECK-NEXT: EMIT ir<%ec> = icmp eq ir<%iv>, ir<100>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
@@ -147,7 +147,7 @@ define void @single_scalar_load_used_as_store_addr(ptr noalias %p) {
; CHECK-NEXT: EMIT ir<%iv.next> = add ir<%iv>, ir<1>
; CHECK-NEXT: CLONE ir<%l.p> = load ir<%p>
; CHECK-NEXT: EMIT ir<%gep> = getelementptr ir<%l.p>, ir<%iv>
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.trunc> = trunc ir<%iv.next> to i32
+; CHECK-NEXT: EMIT ir<%iv.trunc> = trunc ir<%iv.next> to i32
; CHECK-NEXT: EMIT store ir<%iv.trunc>, ir<%gep>
; CHECK-NEXT: EMIT ir<%ec> = icmp eq ir<%iv>, ir<100>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
@@ -313,7 +313,7 @@ define void @consecutive_load_with_first_order_recurrence_address(ptr noalias %a
; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%prev> = phi ir<0>, ir<%ext>
; CHECK-NEXT: EMIT ir<%iv.next> = add nuw nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%inc> = add ir<%narrow>, ir<1>
-; CHECK-NEXT: EMIT-SCALAR ir<%ext> = zext ir<%inc> to i64
+; CHECK-NEXT: EMIT ir<%ext> = zext ir<%inc> to i64
; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = first-order splice ir<%prev>, ir<%ext>
; CHECK-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, vp<[[VP4]]>
; CHECK-NEXT: EMIT-SCALAR ir<%lv> = load ir<%gep.a>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
index 057e2c71eacd5..870ae0b0a7327 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
@@ -25,7 +25,7 @@ define void @f1() {
; CHECK-EMPTY:
; CHECK-NEXT: bb2:
; CHECK-NEXT: EMIT-SCALAR ir<%c.1.0> = phi [ ir<0>, vector.ph ], [ ir<%_tmp9>, bb2 ]
-; CHECK-NEXT: EMIT-SCALAR ir<%_tmp6> = sext ir<%c.1.0> to i64
+; CHECK-NEXT: EMIT ir<%_tmp6> = sext ir<%c.1.0> to i64
; CHECK-NEXT: EMIT ir<%_tmp7> = getelementptr ir<@b>, ir<0>, ir<%_tmp6>
; CHECK-NEXT: EMIT store ir<@a>, ir<%_tmp7>
; CHECK-NEXT: EMIT ir<%_tmp9> = add nsw ir<%c.1.0>, ir<1>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll b/llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll
index c01f2eccf2149..6c8c9c9861f42 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll
@@ -22,7 +22,7 @@ define void @scalarize_irregular_types(ptr noalias %p1, ptr noalias %p2) {
; CHECK-NEXT: EMIT-SCALAR ir<%load1> = load ir<%gep1>
; CHECK-NEXT: EMIT ir<%gep2> = getelementptr ir<%p2>, ir<%iv>
; CHECK-NEXT: REPLICATE ir<%load2> = load ir<%gep2>
-; CHECK-NEXT: EMIT-SCALAR ir<%load2.zext> = zext ir<%load2> to i64
+; CHECK-NEXT: EMIT ir<%load2.zext> = zext ir<%load2> to i64
; CHECK-NEXT: EMIT ir<%add> = add ir<%load1>, ir<%load2.zext>
; CHECK-NEXT: EMIT store ir<%add>, ir<%gep1>
; CHECK-NEXT: EMIT ir<%iv.next> = add ir<%iv>, ir<1>
@@ -44,7 +44,7 @@ define void @scalarize_irregular_types(ptr noalias %p1, ptr noalias %p2) {
; ALL-MEMOP-WIDEN-NEXT: WIDEN ir<%load1> = load vp<[[VP4]]>
; ALL-MEMOP-WIDEN-NEXT: EMIT ir<%gep2> = getelementptr ir<%p2>, ir<%iv>
; ALL-MEMOP-WIDEN-NEXT: REPLICATE ir<%load2> = load ir<%gep2>
-; ALL-MEMOP-WIDEN-NEXT: EMIT-SCALAR ir<%load2.zext> = zext ir<%load2> to i64
+; ALL-MEMOP-WIDEN-NEXT: EMIT ir<%load2.zext> = zext ir<%load2> to i64
; ALL-MEMOP-WIDEN-NEXT: EMIT ir<%add> = add ir<%load1>, ir<%load2.zext>
; ALL-MEMOP-WIDEN-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer i64, ir<%gep1>, ir<1>
; ALL-MEMOP-WIDEN-NEXT: WIDEN store vp<[[VP5]]>, ir<%add>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
index 7f44bc7c68294..db97c840f06e8 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
@@ -1048,7 +1048,7 @@ define void @byte_dependent_byte_geps(ptr noalias %p.out, ptr %p0, ptr %p1, i64
; CHECK-NEXT: EMIT-SCALAR ir<%ld0> = load ir<%gep.ld0>
; CHECK-NEXT: EMIT ir<%gep.ld1> = getelementptr ir<%p1>, ir<%idx>
; CHECK-NEXT: EMIT-SCALAR ir<%ld1> = load ir<%gep.ld1>
-; CHECK-NEXT: EMIT-SCALAR ir<%ld1.ext> = sext ir<%ld1> to i64
+; CHECK-NEXT: EMIT ir<%ld1.ext> = sext ir<%ld1> to i64
; CHECK-NEXT: EMIT ir<%val> = add ir<%ld0>, ir<%ld1.ext>
; CHECK-NEXT: EMIT ir<%gep.st> = getelementptr ir<%p.out>, ir<%iv>
; CHECK-NEXT: EMIT store ir<%val>, ir<%gep.st>
@@ -1124,7 +1124,7 @@ define void @byte_dependent_byte_geps_reverse_order(ptr noalias %p.out, ptr %p0,
; CHECK-NEXT: EMIT ir<%idx> = mul ir<%iv>, ir<%stride>
; CHECK-NEXT: EMIT ir<%gep.ld1> = getelementptr ir<%p1>, ir<%idx>
; CHECK-NEXT: EMIT-SCALAR ir<%ld1> = load ir<%gep.ld1>
-; CHECK-NEXT: EMIT-SCALAR ir<%ld1.ext> = sext ir<%ld1> to i64
+; CHECK-NEXT: EMIT ir<%ld1.ext> = sext ir<%ld1> to i64
; CHECK-NEXT: EMIT ir<%gep.ld0> = getelementptr ir<%p0>, ir<%idx>
; CHECK-NEXT: EMIT-SCALAR ir<%ld0> = load ir<%gep.ld0>
; CHECK-NEXT: EMIT ir<%val> = add ir<%ld0>, ir<%ld1.ext>
@@ -2316,7 +2316,7 @@ define void @sext_stride(ptr noalias %p.out, ptr %p, i32 %stride.i32) {
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
-; CHECK-NEXT: EMIT-SCALAR ir<%stride> = sext ir<%stride.i32> to i64
+; CHECK-NEXT: EMIT ir<%stride> = sext ir<%stride.i32> to i64
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%idx> = mul ir<%iv>, ir<%stride>
; CHECK-NEXT: EMIT ir<%gep.ld> = getelementptr ir<%p>, ir<%idx>
@@ -2537,7 +2537,7 @@ define void @trunc_stride(ptr noalias %p.out, ptr %p, i64 %stride.i64) {
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
-; CHECK-NEXT: EMIT-SCALAR ir<%stride> = trunc ir<%stride.i64> to i32
+; CHECK-NEXT: EMIT ir<%stride> = trunc ir<%stride.i64> to i32
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%idx> = mul ir<%iv>, ir<%stride>
; CHECK-NEXT: EMIT ir<%gep.ld> = getelementptr ir<%p>, ir<%idx>
@@ -2607,7 +2607,7 @@ define void @trunc_stride_extra_narrow_use(ptr noalias %p.out, ptr %p, i64 %stri
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
-; CHECK-NEXT: EMIT-SCALAR ir<%stride> = trunc ir<%stride.i64> to i32
+; CHECK-NEXT: EMIT ir<%stride> = trunc ir<%stride.i64> to i32
; CHECK-NEXT: EMIT ir<%stride.byte> = mul ir<%stride>, ir<4>
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
; CHECK-NEXT: EMIT ir<%idx> = mul ir<%iv>, ir<%stride.byte>
@@ -2688,8 +2688,8 @@ define void @trunc_ext_stride(ptr noalias %p.out, ptr %p0, ptr %p1, i32 %stride)
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.trunc> = trunc ir<%iv> to i16
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.ext> = sext ir<%iv> to i64
+; CHECK-NEXT: EMIT ir<%iv.trunc> = trunc ir<%iv> to i16
+; CHECK-NEXT: EMIT ir<%iv.ext> = sext ir<%iv> to i64
; CHECK-NEXT: EMIT ir<%idx.trunc> = mul ir<%iv.trunc>, ir<%stride.trunc>
; CHECK-NEXT: EMIT ir<%idx.ext> = mul ir<%iv.ext>, ir<%stride.ext>
; CHECK-NEXT: EMIT ir<%gep.trunc> = getelementptr ir<%p0>, ir<%idx.trunc>
@@ -3386,14 +3386,14 @@ define void @stride_mv_predicated_btc(ptr noalias %p.out, ptr %p, i32 %M, i64 %s
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]>
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.ext> = sext ir<%iv> to i64
+; CHECK-NEXT: EMIT ir<%iv.ext> = sext ir<%iv> to i64
; CHECK-NEXT: EMIT ir<%idx> = mul ir<%iv.ext>, ir<%stride>
; CHECK-NEXT: EMIT ir<%gep.ld> = getelementptr ir<%p>, ir<%idx>
; CHECK-NEXT: EMIT-SCALAR ir<%ld> = load ir<%gep.ld>
; CHECK-NEXT: EMIT ir<%gep.st> = getelementptr ir<%p.out>, ir<%iv.ext>
; CHECK-NEXT: EMIT store ir<%ld>, ir<%gep.st>
; CHECK-NEXT: EMIT ir<%iv.next> = add ir<%iv>, ir<1>
-; CHECK-NEXT: EMIT-SCALAR ir<%iv.next.ext> = sext ir<%iv.next> to i32
+; CHECK-NEXT: EMIT ir<%iv.next.ext> = sext ir<%iv.next> to i32
; CHECK-NEXT: EMIT ir<%ec> = icmp sgt ir<%iv.next.ext>, ir<%M>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
index 2a5022b2c229b..a1a3cdccf7bdf 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
@@ -42,8 +42,8 @@ define void @predicated_block(ptr noalias %a, ptr noalias %idx) {
; PREDICATE-EMPTY:
; PREDICATE-NEXT: if.then:
; PREDICATE-NEXT: EMIT ir<%add> = add ir<%i>, ir<1>, ir<%cmp> (!vplan.execution.frequency 4611686018427387903 (25%))
-; PREDICATE-NEXT: EMIT-SCALAR ir<%t> = trunc ir<%add> to i16
-; PREDICATE-NEXT: EMIT-SCALAR ir<%ext> = sext ir<%t> to i64
+; PREDICATE-NEXT: EMIT ir<%t> = trunc ir<%add> to i16
+; PREDICATE-NEXT: EMIT ir<%ext> = sext ir<%t> to i64
; PREDICATE-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%ext>
; PREDICATE-NEXT: EMIT store ir<%add>, ir<%gep.a>, ir<%cmp> (!vplan.execution.frequency 4611686018427387903 (25%))
; PREDICATE-NEXT: Successor(s): latch
@@ -85,8 +85,8 @@ define void @predicated_block(ptr noalias %a, ptr noalias %idx) {
; CONSTRUCT-EMPTY:
; CONSTRUCT-NEXT: if.then:
; CONSTRUCT-NEXT: EMIT ir<%add> = add ir<%i>, ir<1>, ir<%cmp> (!vplan.execution.frequency 4611686018427387903 (25%))
-; CONSTRUCT-NEXT: EMIT-SCALAR ir<%t> = trunc ir<%add> to i16
-; CONSTRUCT-NEXT: EMIT-SCALAR ir<%ext> = sext ir<%t> to i64
+; CONSTRUCT-NEXT: EMIT ir<%t> = trunc ir<%add> to i16
+; CONSTRUCT-NEXT: EMIT ir<%ext> = sext ir<%t> to i64
; CONSTRUCT-NEXT: EMIT ir<%gep.a> = getelementptr inbounds ir<%a>, ir<%ext>
; CONSTRUCT-NEXT: REPLICATE store ir<%add>, ir<%gep.a>, ir<%cmp> (!vplan.execution.frequency 4611686018427387903 (25%))
; CONSTRUCT-NEXT: Successor(s): latch
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
index c35a23592b768..2b60066e51b8e 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
@@ -534,7 +534,7 @@ define void @ptrtoaddr_gep(ptr noalias %A, ptr noalias %B) {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT ir<%p> = getelementptr inbounds ir<null>, ir<%iv>
-; CHECK-NEXT: EMIT-SCALAR ir<%idx> = ptrtoaddr ir<%p> to i64
+; CHECK-NEXT: EMIT ir<%idx> = ptrtoaddr ir<%p> to i64
; CHECK-NEXT: EMIT ir<%gep> = getelementptr inbounds ir<%A>, ir<%idx>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = vector-pointer inbounds i32, ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP4]]>
@@ -601,7 +601,7 @@ define void @ptrtoint_gep(ptr noalias %A, ptr noalias %B) {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT ir<%p> = getelementptr inbounds ir<null>, ir<%iv>
-; CHECK-NEXT: EMIT-SCALAR ir<%idx> = ptrtoint ir<%p> to i64
+; CHECK-NEXT: EMIT ir<%idx> = ptrtoint ir<%p> to i64
; CHECK-NEXT: EMIT ir<%gep> = getelementptr inbounds ir<%A>, ir<%idx>
; CHECK-NEXT: EMIT-SCALAR ir<%l> = load ir<%gep>
; CHECK-NEXT: EMIT ir<%gep.b> = getelementptr inbounds ir<%B>, ir<%iv>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll b/llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll
index 6c9bc6339c997..c181606eae55a 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll
@@ -23,7 +23,7 @@ define void @simple_histogram(ptr noalias %buckets, ptr readonly %indices, i64 %
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT ir<%gep.indices> = getelementptr inbounds ir<%indices>, ir<%iv>
; CHECK-NEXT: EMIT-SCALAR ir<%l.idx> = load ir<%gep.indices>
-; CHECK-NEXT: EMIT-SCALAR ir<%idxprom1> = zext ir<%l.idx> to i64
+; CHECK-NEXT: EMIT ir<%idxprom1> = zext ir<%l.idx> to i64
; CHECK-NEXT: EMIT ir<%gep.bucket> = getelementptr inbounds ir<%buckets>, ir<%idxprom1>
; CHECK-NEXT: EMIT-SCALAR ir<%l.bucket> = load ir<%gep.bucket>
; CHECK-NEXT: EMIT ir<%inc> = add nsw ir<%l.bucket>, ir<1>
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