[llvm] AMDGPU/GlobalISel: Legalize bf16 fptosi and fptoui (PR #227439)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 08:49:26 PDT 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/227439
>From 004dbca2e00ce9ccfc10bb4e49a69cddfd38cdba Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Tue, 29 Sep 2026 14:42:37 -0400
Subject: [PATCH 1/2] AMDGPU/GlobalISel: Legalize bf16 fptosi and fptoui
Legalize bf16 fptosi and fptoui by widening to f32.
Also convert MIR tests to exact integer and fp types.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +-
.../CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll | 485 ++++++++++++++++++
.../CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll | 442 ++++++++++++++++
.../AMDGPU/GlobalISel/legalize-fptosi.mir | 472 ++++++++---------
.../AMDGPU/GlobalISel/legalize-fptoui.mir | 430 ++++++++--------
5 files changed, 1381 insertions(+), 452 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e759f6eb64860..55c1fca8360e6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1264,7 +1264,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.legalFor({{I32, F32}, {I32, F64}})
.customFor({{I64, F32}, {I64, F64}})
.widenScalarFor({{I32, F16}}, changeElementSizeTo(1, F32))
- .narrowScalarFor({{I64, F16}}, changeElementSizeTo(0, I32));
+ .narrowScalarFor({{I64, F16}}, changeElementSizeTo(0, I32))
+ .widenScalarFor({{I16, BF16}, {I32, BF16}, {I64, BF16}},
+ changeElementTo(1, F32));
if (ST.has16BitInsts())
FPToI.legalFor({{I16, F16}});
else
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
new file mode 100644
index 0000000000000..9cad7b07b9167
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
@@ -0,0 +1,485 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX1250 %s
+
+define amdgpu_ps i16 @fptosi_bf16_i16_v(bfloat %a) {
+; GFX6-LABEL: fptosi_bf16_i16_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i16_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i16_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i16
+ ret i16 %r
+}
+
+define amdgpu_ps i16 @fptosi_bf16_i16_s(bfloat inreg %a) {
+; GFX6-LABEL: fptosi_bf16_i16_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i16_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i16_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i16
+ ret i16 %r
+}
+
+define amdgpu_ps i32 @fptosi_bf16_i32_v(bfloat %a) {
+; GFX6-LABEL: fptosi_bf16_i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i32
+ ret i32 %r
+}
+
+define amdgpu_ps i32 @fptosi_bf16_i32_s(bfloat inreg %a) {
+; GFX6-LABEL: fptosi_bf16_i32_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i32_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i32
+ ret i32 %r
+}
+
+define amdgpu_ps i64 @fptosi_bf16_i64_v(bfloat %a) {
+; GFX6-LABEL: fptosi_bf16_i64_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX6-NEXT: v_mul_f32_e64 v2, |v1|, v2
+; GFX6-NEXT: v_floor_f32_e32 v2, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX6-NEXT: v_fma_f32 v1, v2, v3, |v1|
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, v1, v0
+; GFX6-NEXT: v_xor_b32_e32 v2, v2, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
+; GFX6-NEXT: v_readfirstlane_b32 s0, v1
+; GFX6-NEXT: v_readfirstlane_b32 s1, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i64_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, v2
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX9-NEXT: v_fma_f32 v1, v2, v3, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v0
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v0, vcc, v2, v0, vcc
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX12-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX12-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_xor_b32_e32 v2, v2, v0
+; GFX12-NEXT: v_xor_b32_e32 v1, v1, v0
+; GFX12-NEXT: v_sub_co_u32 v1, vcc_lo, v1, v0
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v0, null, v2, v0, vcc_lo
+; GFX12-NEXT: v_readfirstlane_b32 s0, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v1, v0
+; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX1250-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX1250-NEXT: v_floor_f32_e32 v2, v2
+; GFX1250-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_bitop2_b32 v3, v2, v0 bitop3:0x14
+; GFX1250-NEXT: v_xor_b32_e32 v2, v4, v0
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i64
+ ret i64 %r
+}
+
+define amdgpu_ps i64 @fptosi_bf16_i64_s(bfloat inreg %a) {
+; GFX6-LABEL: fptosi_bf16_i64_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_trunc_f32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX6-NEXT: v_mul_f32_e64 v1, |v0|, v1
+; GFX6-NEXT: v_floor_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6-NEXT: v_fma_f32 v0, v1, v2, |v0|
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: s_ashr_i32 s2, s0, 31
+; GFX6-NEXT: s_mov_b32 s3, s2
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT: s_sub_u32 s0, s0, s2
+; GFX6-NEXT: s_subb_u32 s1, s1, s2
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_bf16_i64_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_trunc_f32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX9-NEXT: v_mul_f32_e64 v1, |v0|, v1
+; GFX9-NEXT: v_floor_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX9-NEXT: v_fma_f32 v0, v1, v2, |v0|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_ashr_i32 s2, s0, 31
+; GFX9-NEXT: s_mov_b32 s3, s2
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-NEXT: s_sub_u32 s0, s0, s2
+; GFX9-NEXT: s_subb_u32 s1, s1, s2
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_bf16_i64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_trunc_f32 s1, s0
+; GFX12-NEXT: s_ashr_i32 s0, s0, 31
+; GFX12-NEXT: s_bitset0_b32 s1, 31
+; GFX12-NEXT: s_mul_f32 s2, s1, 0x2f800000
+; GFX12-NEXT: s_floor_f32 s2, s2
+; GFX12-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX12-NEXT: s_cvt_u32_f32 s3, s2
+; GFX12-NEXT: s_cvt_u32_f32 s2, s1
+; GFX12-NEXT: s_mov_b32 s1, s0
+; GFX12-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX12-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_bf16_i64_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_trunc_f32 s1, s0
+; GFX1250-NEXT: s_ashr_i32 s0, s0, 31
+; GFX1250-NEXT: s_bitset0_b32 s1, 31
+; GFX1250-NEXT: s_mul_f32 s2, s1, 0x2f800000
+; GFX1250-NEXT: s_floor_f32 s2, s2
+; GFX1250-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX1250-NEXT: s_cvt_u32_f32 s3, s2
+; GFX1250-NEXT: s_cvt_u32_f32 s2, s1
+; GFX1250-NEXT: s_mov_b32 s1, s0
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX1250-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi bfloat %a to i64
+ ret i64 %r
+}
+
+define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_v(<2 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
+; GFX6-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshr_b32 s1, s0, 16
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6-NEXT: v_cvt_i32_f32_e32 v1, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshr_b32 s1, s0, 16
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX9-NEXT: s_lshl_b32 s0, s1, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v1, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s0, s0
+; GFX1250-NEXT: s_cvt_i32_f32 s1, s1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <4 x i32> @fptosi_v4bf16_v4i32_v(<4 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <4 x bfloat> %a to <4 x i32>
+ ret <4 x i32> %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
new file mode 100644
index 0000000000000..4388ae1217140
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
@@ -0,0 +1,442 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX1250 %s
+
+define amdgpu_ps i16 @fptoui_bf16_i16_v(bfloat %a) {
+; GFX6-LABEL: fptoui_bf16_i16_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i16_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i16_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i16
+ ret i16 %r
+}
+
+define amdgpu_ps i16 @fptoui_bf16_i16_s(bfloat inreg %a) {
+; GFX6-LABEL: fptoui_bf16_i16_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i16_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i16_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i16
+ ret i16 %r
+}
+
+define amdgpu_ps i32 @fptoui_bf16_i32_v(bfloat %a) {
+; GFX6-LABEL: fptoui_bf16_i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i32
+ ret i32 %r
+}
+
+define amdgpu_ps i32 @fptoui_bf16_i32_s(bfloat inreg %a) {
+; GFX6-LABEL: fptoui_bf16_i32_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i32_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i32
+ ret i32 %r
+}
+
+define amdgpu_ps i64 @fptoui_bf16_i64_v(bfloat %a) {
+; GFX6-LABEL: fptoui_bf16_i64_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_trunc_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_floor_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i64_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_trunc_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_floor_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX9-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_trunc_f32_e32 v0, v0
+; GFX12-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX12-NEXT: v_floor_f32_e32 v1, v1
+; GFX12-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v0, v0
+; GFX1250-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX1250-NEXT: v_floor_f32_e32 v1, v1
+; GFX1250-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i64
+ ret i64 %r
+}
+
+define amdgpu_ps i64 @fptoui_bf16_i64_s(bfloat inreg %a) {
+; GFX6-LABEL: fptoui_bf16_i64_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_trunc_f32_e32 v0, s0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_floor_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_bf16_i64_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_trunc_f32_e32 v0, s0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_floor_f32_e32 v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX9-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_bf16_i64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_trunc_f32 s0, s0
+; GFX12-NEXT: s_mul_f32 s1, s0, 0x2f800000
+; GFX12-NEXT: s_floor_f32 s1, s1
+; GFX12-NEXT: s_fmac_f32 s0, s1, 0xcf800000
+; GFX12-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_bf16_i64_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_trunc_f32 s0, s0
+; GFX1250-NEXT: s_mul_f32 s1, s0, 0x2f800000
+; GFX1250-NEXT: s_floor_f32 s1, s1
+; GFX1250-NEXT: s_fmac_f32 s0, s1, 0xcf800000
+; GFX1250-NEXT: s_cvt_u32_f32 s1, s1
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui bfloat %a to i64
+ ret i64 %r
+}
+
+define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_v(<2 x bfloat> %a) {
+; GFX6-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
+; GFX6-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_lshr_b32 s1, s0, 16
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, s0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshr_b32 s1, s0, 16
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX9-NEXT: s_lshl_b32 s0, s1, 16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, s0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: s_cvt_u32_f32 s1, s1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <4 x i32> @fptoui_v4bf16_v4i32_v(<4 x bfloat> %a) {
+; GFX6-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s2, v1
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <4 x bfloat> %a to <4 x i32>
+ ret <4 x i32> %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
index 309089c66220a..69427eab847ff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
@@ -12,17 +12,17 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s32_to_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s32) = G_FPTOSI %0
+ %1:_(i32) = G_FPTOSI %0
$vgpr0 = COPY %1
...
@@ -36,17 +36,17 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f64)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f64)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s64_to_s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f64)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f64)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_FPTOSI %0
+ %1:_(i32) = G_FPTOSI %0
$vgpr0 = COPY %1
...
@@ -61,22 +61,22 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](f32)
- ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](f32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[UV]](f32)
+ ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[UV1]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOSI]](i32), [[FPTOSI1]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
;
; VI-LABEL: name: test_fptosi_v2s32_to_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](f32)
- ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](f32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[UV]](f32)
+ ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[UV1]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOSI]](i32), [[FPTOSI1]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FPTOSI %0
+ %1:_(<2 x i32>) = G_FPTOSI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -91,22 +91,22 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](f64)
- ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](f64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[UV]](f64)
+ ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[UV1]](f64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOSI]](i32), [[FPTOSI1]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
;
; VI-LABEL: name: test_fptosi_v2s64_to_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](f64)
- ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](f64)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[UV]](f64)
+ ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[UV1]](f64)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOSI]](i32), [[FPTOSI1]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
%0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s32>) = G_FPTOSI %0
+ %1:_(<2 x i32>) = G_FPTOSI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -119,24 +119,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s16) = G_FPTOSI [[TRUNC]](f16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTOSI]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i16) = G_FPTOSI [[TRUNC]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTOSI]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s16) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i16) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -150,18 +150,18 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s32_to_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s16) = G_FPTOSI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i16) = G_FPTOSI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -175,18 +175,18 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f64)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f64)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s64_to_s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f64)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f64)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s16) = G_FPTOSI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i16) = G_FPTOSI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -235,8 +235,8 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FADD]], [[C9]], [[BITCAST1]]
; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FADD]](f64)
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](s64)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](i64)
;
; VI-LABEL: name: test_fptosi_s64_s64
; VI: liveins: $vgpr0_vgpr1
@@ -250,10 +250,10 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FFLOOR]](f64)
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FPTOSI %0
+ %1:_(i64) = G_FPTOSI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -266,8 +266,8 @@ body: |
; SI-LABEL: name: test_fptosi_s64_s64_flags
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -288,37 +288,37 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
; SI-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3DF0000000000000
; SI-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xC1F0000000000000
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[BITCAST1]], [[C8]]
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = nnan G_FMUL [[BITCAST1]], [[C8]]
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
; SI-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = nnan G_FNEG [[FMINNUM_IEEE]]
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[FMUL]], [[FNEG]]
- ; SI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FADD]], [[C9]], [[BITCAST1]]
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FADD]](s64)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](s64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](s64)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = nnan G_FADD [[FMUL]], [[FNEG]]
+ ; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = nnan G_FMA [[FADD]], [[C9]], [[BITCAST1]]
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FADD]](f64)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](i64)
;
; VI-LABEL: name: test_fptosi_s64_s64_flags
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = nnan G_INTRINSIC_TRUNC [[COPY]]
; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3DF0000000000000
; VI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xC1F0000000000000
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
- ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
- ; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FFLOOR]](s64)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](s64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = nnan G_FPTOSI %0
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
+ ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(f64) = nnan G_FFLOOR [[FMUL]]
+ ; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FFLOOR]](f64)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(i64) = nnan G_FPTOSI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -368,7 +368,7 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FADD]], [[C9]], [[BITCAST1]]
; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FADD]](f64)
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
; SI-NEXT: [[INT2:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32)
@@ -393,9 +393,9 @@ body: |
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FADD1]], [[C9]], [[BITCAST3]]
; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[FADD1]](f64)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f64)
- ; SI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOSI1]](i32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[MV3:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOSI1]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV1]](i64), [[MV3]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptosi_v2s64_to_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
@@ -410,18 +410,18 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FFLOOR]](f64)
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI]](i32), [[FPTOSI]](i32)
; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]
; VI-NEXT: [[FFLOOR1:%[0-9]+]]:_(f64) = G_FFLOOR [[FMUL1]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]
; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[FFLOOR1]](f64)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f64)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOSI1]](i32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOSI1]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV]](i64), [[MV1]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_FPTOSI %0
+ %1:_(<2 x i64>) = G_FPTOSI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -450,11 +450,11 @@ body: |
; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; SI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; SI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
- ; SI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
- ; SI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](s64)
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; SI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
+ ; SI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
+ ; SI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](i64)
;
; VI-LABEL: name: test_fptosi_s32_to_s64
; VI: liveins: $vgpr0
@@ -475,13 +475,13 @@ body: |
; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; VI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; VI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
- ; VI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](s64)
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; VI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
+ ; VI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](i64)
%0:_(f32) = COPY $vgpr0
- %1:_(s64) = G_FPTOSI %0
+ %1:_(i64) = G_FPTOSI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -511,10 +511,10 @@ body: |
; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; SI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; SI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV2]], [[ASHR]]
- ; SI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV3]], [[ASHR]], [[USUBO1]]
- ; SI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; SI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV2]], [[ASHR]]
+ ; SI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV3]], [[ASHR]], [[USUBO1]]
+ ; SI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(i32) = G_ASHR [[BITCAST1]], [[C]](i32)
@@ -527,12 +527,12 @@ body: |
; SI-NEXT: [[MV3:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR1]](i32), [[ASHR1]](i32)
; SI-NEXT: [[MV4:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
; SI-NEXT: [[XOR1:%[0-9]+]]:_(i64) = G_XOR [[MV4]], [[MV3]]
- ; SI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](i64)
- ; SI-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(i1) = G_USUBO [[UV4]], [[ASHR1]]
- ; SI-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(i1) = G_USUBE [[UV5]], [[ASHR1]], [[USUBO3]]
- ; SI-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV5]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR1]](i64)
+ ; SI-NEXT: [[USUBO2:%[0-9]+]]:_(i32), [[USUBO3:%[0-9]+]]:_(i1) = G_USUBO [[UV4]], [[ASHR1]]
+ ; SI-NEXT: [[USUBE2:%[0-9]+]]:_(i32), [[USUBE3:%[0-9]+]]:_(i1) = G_USUBE [[UV5]], [[ASHR1]], [[USUBO3]]
+ ; SI-NEXT: [[MV5:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO2]](i32), [[USUBE2]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV2]](i64), [[MV5]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptosi_v2s32_to_v2s64
; VI: liveins: $vgpr0_vgpr1
@@ -554,10 +554,10 @@ body: |
; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; VI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; VI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV2]], [[ASHR]]
- ; VI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV3]], [[ASHR]], [[USUBO1]]
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; VI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV2]], [[ASHR]]
+ ; VI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV3]], [[ASHR]], [[USUBO1]]
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(i32) = G_ASHR [[BITCAST1]], [[C]](i32)
@@ -570,14 +570,14 @@ body: |
; VI-NEXT: [[MV3:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR1]](i32), [[ASHR1]](i32)
; VI-NEXT: [[MV4:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
; VI-NEXT: [[XOR1:%[0-9]+]]:_(i64) = G_XOR [[MV4]], [[MV3]]
- ; VI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](i64)
- ; VI-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(i1) = G_USUBO [[UV4]], [[ASHR1]]
- ; VI-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(i1) = G_USUBE [[UV5]], [[ASHR1]], [[USUBO3]]
- ; VI-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV5]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR1]](i64)
+ ; VI-NEXT: [[USUBO2:%[0-9]+]]:_(i32), [[USUBO3:%[0-9]+]]:_(i1) = G_USUBO [[UV4]], [[ASHR1]]
+ ; VI-NEXT: [[USUBE2:%[0-9]+]]:_(i32), [[USUBE3:%[0-9]+]]:_(i1) = G_USUBE [[UV5]], [[ASHR1]], [[USUBO3]]
+ ; VI-NEXT: [[MV5:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO2]](i32), [[USUBE2]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV2]](i64), [[MV5]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s64>) = G_FPTOSI %0
+ %1:_(<2 x i64>) = G_FPTOSI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -590,25 +590,25 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s64
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](i64)
;
; VI-LABEL: name: test_fptosi_s16_to_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](i64)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s64) = G_FPTOSI %1
+ %2:_(i64) = G_FPTOSI %1
$vgpr0_vgpr1 = COPY %2
...
@@ -628,13 +628,13 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI]](i32)
; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT1]](f32)
- ; SI-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI1]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT1]](f32)
+ ; SI-NEXT: [[SEXT1:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI1]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[SEXT]](i64), [[SEXT1]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptosi_v2s16_to_v2s64
; VI: liveins: $vgpr0
@@ -646,15 +646,15 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI]](i32)
; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT1]](f32)
- ; VI-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI1]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT1]](f32)
+ ; VI-NEXT: [[SEXT1:%[0-9]+]]:_(i64) = G_SEXT [[FPTOSI1]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[SEXT]](i64), [[SEXT1]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f16>) = COPY $vgpr0
- %1:_(<2 x s64>) = G_FPTOSI %0
+ %1:_(<2 x i64>) = G_FPTOSI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -666,25 +666,25 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s1
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
- ; SI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[FPTOSI]](i32)
+ ; SI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](i1)
;
; VI-LABEL: name: test_fptosi_s16_to_s1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
- ; VI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](s1)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[FPTOSI]](i32)
+ ; VI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](i1)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s1) = G_FPTOSI %1
+ %2:_(i1) = G_FPTOSI %1
S_ENDPGM 0, implicit %2
...
@@ -697,24 +697,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s15
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s15
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s15) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i15) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -727,24 +727,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s17
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s17
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s17) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i17) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -773,11 +773,11 @@ body: |
; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; SI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; SI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
- ; SI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
- ; SI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](s64)
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; SI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
+ ; SI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
+ ; SI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](i64)
;
; VI-LABEL: name: test_fptosi_s32_to_s33
; VI: liveins: $vgpr0
@@ -798,14 +798,14 @@ body: |
; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[ASHR]](i32), [[ASHR]](i32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; VI-NEXT: [[XOR:%[0-9]+]]:_(i64) = G_XOR [[MV1]], [[MV]]
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](i64)
- ; VI-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
- ; VI-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](s64)
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[XOR]](i64)
+ ; VI-NEXT: [[USUBO:%[0-9]+]]:_(i32), [[USUBO1:%[0-9]+]]:_(i1) = G_USUBO [[UV]], [[ASHR]]
+ ; VI-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(i1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[USUBO]](i32), [[USUBE]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV2]](i64)
%0:_(f32) = COPY $vgpr0
- %1:_(s33) = G_FPTOSI %0
- %2:_(s64) = G_ANYEXT %1
+ %1:_(i33) = G_FPTOSI %0
+ %2:_(i64) = G_ANYEXT %1
$vgpr0_vgpr1 = COPY %2
...
@@ -818,24 +818,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s7
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s7
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s7) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i7) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -848,24 +848,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s8
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s8) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i8) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -878,24 +878,24 @@ body: |
; SI-LABEL: name: test_fptosi_s16_to_s9
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s16_to_s9
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s9) = G_FPTOSI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i9) = G_FPTOSI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -909,18 +909,18 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s32_to_s15
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s15) = G_FPTOSI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i15) = G_FPTOSI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -934,17 +934,17 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
;
; VI-LABEL: name: test_fptosi_s32_to_s17
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](s32)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOSI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s17) = G_FPTOSI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i17) = G_FPTOSI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
index 3a2015821d269..33bc33fa4c217 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
@@ -12,17 +12,17 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s32_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s32) = G_FPTOUI %0
+ %1:_(i32) = G_FPTOUI %0
$vgpr0 = COPY %1
...
@@ -36,17 +36,17 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f64)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f64)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s32_s64
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f64)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f64)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_FPTOUI %0
+ %1:_(i32) = G_FPTOUI %0
$vgpr0 = COPY %1
...
@@ -61,22 +61,22 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](f32)
- ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](f32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[UV]](f32)
+ ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[UV1]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOUI]](i32), [[FPTOUI1]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
;
; VI-LABEL: name: test_fptoui_v2s32_to_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](f32)
- ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](f32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[UV]](f32)
+ ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[UV1]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOUI]](i32), [[FPTOUI1]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FPTOUI %0
+ %1:_(<2 x i32>) = G_FPTOUI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -91,22 +91,22 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](f64)
- ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](f64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[UV]](f64)
+ ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[UV1]](f64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOUI]](i32), [[FPTOUI1]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
;
; VI-LABEL: name: test_fptoui_v2s64_to_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](f64)
- ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](f64)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[UV]](f64)
+ ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[UV1]](f64)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[FPTOUI]](i32), [[FPTOUI1]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
%0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s32>) = G_FPTOUI %0
+ %1:_(<2 x i32>) = G_FPTOUI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -119,24 +119,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s16) = G_FPTOUI [[TRUNC]](f16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTOUI]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i16) = G_FPTOUI [[TRUNC]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTOUI]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s16) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i16) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -150,18 +150,18 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s32_to_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s16) = G_FPTOUI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i16) = G_FPTOUI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -175,18 +175,18 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f64)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f64)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s64_to_s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f64)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f64)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s16) = G_FPTOUI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i16) = G_FPTOUI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -235,8 +235,8 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FADD]], [[C9]], [[BITCAST1]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FADD]](f64)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](s64)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](i64)
;
; VI-LABEL: name: test_fptoui_s64_s64
; VI: liveins: $vgpr0_vgpr1
@@ -250,10 +250,10 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f64)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
%0:_(f64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FPTOUI %0
+ %1:_(i64) = G_FPTOUI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -266,8 +266,8 @@ body: |
; SI-LABEL: name: test_fptoui_s64_s64_flags
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -288,37 +288,37 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
; SI-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3DF0000000000000
; SI-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xC1F0000000000000
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[BITCAST1]], [[C8]]
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = nnan G_FMUL [[BITCAST1]], [[C8]]
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
; SI-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = nnan G_FNEG [[FMINNUM_IEEE]]
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[FMUL]], [[FNEG]]
- ; SI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FADD]], [[C9]], [[BITCAST1]]
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FADD]](s64)
- ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](s64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](s64)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = nnan G_FADD [[FMUL]], [[FNEG]]
+ ; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = nnan G_FMA [[FADD]], [[C9]], [[BITCAST1]]
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FADD]](f64)
+ ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](i64)
;
; VI-LABEL: name: test_fptoui_s64_s64_flags
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = nnan G_INTRINSIC_TRUNC [[COPY]]
; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3DF0000000000000
; VI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xC1F0000000000000
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
- ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
- ; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](s64)
- ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](s64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = nnan G_FPTOUI %0
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
+ ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(f64) = nnan G_FFLOOR [[FMUL]]
+ ; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f64)
+ ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(i64) = nnan G_FPTOUI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -368,7 +368,7 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FADD]], [[C9]], [[BITCAST1]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FADD]](f64)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
; SI-NEXT: [[INT2:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32)
@@ -393,9 +393,9 @@ body: |
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FADD1]], [[C9]], [[BITCAST3]]
; SI-NEXT: [[FPTOUI2:%[0-9]+]]:_(i32) = G_FPTOUI [[FADD1]](f64)
; SI-NEXT: [[FPTOUI3:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f64)
- ; SI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[MV3:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV1]](i64), [[MV3]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptoui_v2s64_to_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
@@ -410,18 +410,18 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f64)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f64)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]
; VI-NEXT: [[FFLOOR1:%[0-9]+]]:_(f64) = G_FFLOOR [[FMUL1]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]
; VI-NEXT: [[FPTOUI2:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR1]](f64)
; VI-NEXT: [[FPTOUI3:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f64)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV]](i64), [[MV1]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_FPTOUI %0
+ %1:_(<2 x i64>) = G_FPTOUI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -443,8 +443,8 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
;
; VI-LABEL: name: test_fptoui_s32_to_s64
; VI: liveins: $vgpr0
@@ -458,10 +458,10 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
%0:_(f32) = COPY $vgpr0
- %1:_(s64) = G_FPTOUI %0
+ %1:_(i64) = G_FPTOUI %0
$vgpr0_vgpr1 = COPY %1
...
@@ -484,16 +484,16 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]
; SI-NEXT: [[FFLOOR1:%[0-9]+]]:_(f32) = G_FFLOOR [[FMUL1]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]
; SI-NEXT: [[FPTOUI2:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR1]](f32)
; SI-NEXT: [[FPTOUI3:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f32)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV]](i64), [[MV1]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptoui_v2s32_to_v2s64
; VI: liveins: $vgpr0_vgpr1
@@ -508,18 +508,18 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]
; VI-NEXT: [[FFLOOR1:%[0-9]+]]:_(f32) = G_FFLOOR [[FMUL1]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]
; VI-NEXT: [[FPTOUI2:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR1]](f32)
; VI-NEXT: [[FPTOUI3:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA1]](f32)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI3]](i32), [[FPTOUI2]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MV]](i64), [[MV1]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s64>) = G_FPTOUI %0
+ %1:_(<2 x i64>) = G_FPTOUI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -532,25 +532,25 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s64
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](i64)
;
; VI-LABEL: name: test_fptoui_s16_to_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](i64)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s64) = G_FPTOUI %1
+ %2:_(i64) = G_FPTOUI %1
$vgpr0_vgpr1 = COPY %2
...
@@ -570,13 +570,13 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI]](i32)
; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT1]](f32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI1]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT1]](f32)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI1]](i32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[ZEXT]](i64), [[ZEXT1]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
;
; VI-LABEL: name: test_fptoui_v2s16_to_v2s64
; VI: liveins: $vgpr0
@@ -588,15 +588,15 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI]](i32)
; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
- ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT1]](f32)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI1]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT1]](f32)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[FPTOUI1]](i32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[ZEXT]](i64), [[ZEXT1]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x i64>)
%0:_(<2 x f16>) = COPY $vgpr0
- %1:_(<2 x s64>) = G_FPTOUI %0
+ %1:_(<2 x i64>) = G_FPTOUI %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -608,25 +608,25 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s1
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
- ; SI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[FPTOSI]](i32)
+ ; SI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](i1)
;
; VI-LABEL: name: test_fptoui_s16_to_s1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
- ; VI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](s1)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s1) = G_FPTOSI %1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[FPEXT]](f32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[FPTOSI]](i32)
+ ; VI-NEXT: S_ENDPGM 0, implicit [[TRUNC1]](i1)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0
+ %2:_(i1) = G_FPTOSI %1
S_ENDPGM 0, implicit %2
...
@@ -639,24 +639,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s15
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s15
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s15) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i15) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -669,24 +669,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s17
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s17
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s17) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i17) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -708,8 +708,8 @@ body: |
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; SI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; SI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
;
; VI-LABEL: name: test_fptoui_s32_to_s33
; VI: liveins: $vgpr0
@@ -723,11 +723,11 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FFLOOR]](f32)
; VI-NEXT: [[FPTOUI1:%[0-9]+]]:_(i32) = G_FPTOUI [[FMA]](f32)
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[FPTOUI1]](i32), [[FPTOUI]](i32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
%0:_(f32) = COPY $vgpr0
- %1:_(s33) = G_FPTOUI %0
- %2:_(s64) = G_ANYEXT %1
+ %1:_(i33) = G_FPTOUI %0
+ %2:_(i64) = G_ANYEXT %1
$vgpr0_vgpr1 = COPY %2
...
@@ -740,24 +740,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s7
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s7
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s7) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i7) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -770,24 +770,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s8
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s8) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i8) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -800,24 +800,24 @@ body: |
; SI-LABEL: name: test_fptoui_s16_to_s9
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s16_to_s9
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
- %0:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[FPEXT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
+ %0:_(i32) = COPY $vgpr0
%1:_(f16) = G_TRUNC %0
- %2:_(s9) = G_FPTOUI %1
- %3:_(s32) = G_ANYEXT %2
+ %2:_(i9) = G_FPTOUI %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -831,18 +831,18 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s32_to_s15
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s15) = G_FPTOUI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i15) = G_FPTOUI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -856,17 +856,17 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
;
; VI-LABEL: name: test_fptoui_s32_to_s17
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](f32)
- ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](s32)
+ ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(i32) = G_FPTOUI [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[FPTOUI]](i32)
%0:_(f32) = COPY $vgpr0
- %1:_(s17) = G_FPTOUI %0
- %2:_(s32) = G_ANYEXT %1
+ %1:_(i17) = G_FPTOUI %0
+ %2:_(i32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
>From f07ea42117fd98fa15f9dca8beaf419cbfeffd9c Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Wed, 30 Sep 2026 11:22:54 -0400
Subject: [PATCH 2/2] Add common check prefixes, more vector tests
---
.../CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll | 934 +++++++++++++++---
.../CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll | 759 ++++++++++----
2 files changed, 1358 insertions(+), 335 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
index 9cad7b07b9167..3ed163cde3ac9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptosi.bf16.ll
@@ -1,30 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX6789,GFX6 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX6789,GFX9 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX12 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX1250 %s
define amdgpu_ps i16 @fptosi_bf16_i16_v(bfloat %a) {
-; GFX6-LABEL: fptosi_bf16_i16_v:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptosi_bf16_i16_v:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fptosi_bf16_i16_v:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fptosi_bf16_i16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fptosi_bf16_i16_v:
; GFX1250: ; %bb.0:
@@ -41,19 +27,12 @@ define amdgpu_ps i16 @fptosi_bf16_i16_v(bfloat %a) {
}
define amdgpu_ps i16 @fptosi_bf16_i16_s(bfloat inreg %a) {
-; GFX6-LABEL: fptosi_bf16_i16_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, s0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptosi_bf16_i16_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptosi_bf16_i16_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptosi_bf16_i16_s:
; GFX12: ; %bb.0:
@@ -75,26 +54,12 @@ define amdgpu_ps i16 @fptosi_bf16_i16_s(bfloat inreg %a) {
}
define amdgpu_ps i32 @fptosi_bf16_i32_v(bfloat %a) {
-; GFX6-LABEL: fptosi_bf16_i32_v:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptosi_bf16_i32_v:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fptosi_bf16_i32_v:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fptosi_bf16_i32_v:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fptosi_bf16_i32_v:
; GFX1250: ; %bb.0:
@@ -111,19 +76,12 @@ define amdgpu_ps i32 @fptosi_bf16_i32_v(bfloat %a) {
}
define amdgpu_ps i32 @fptosi_bf16_i32_s(bfloat inreg %a) {
-; GFX6-LABEL: fptosi_bf16_i32_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, s0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptosi_bf16_i32_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptosi_bf16_i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptosi_bf16_i32_s:
; GFX12: ; %bb.0:
@@ -228,45 +186,25 @@ define amdgpu_ps i64 @fptosi_bf16_i64_v(bfloat %a) {
}
define amdgpu_ps i64 @fptosi_bf16_i64_s(bfloat inreg %a) {
-; GFX6-LABEL: fptosi_bf16_i64_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_trunc_f32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x2f800000
-; GFX6-NEXT: v_mul_f32_e64 v1, |v0|, v1
-; GFX6-NEXT: v_floor_f32_e32 v1, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX6-NEXT: v_fma_f32 v0, v1, v2, |v0|
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_ashr_i32 s2, s0, 31
-; GFX6-NEXT: s_mov_b32 s3, s2
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX6-NEXT: s_sub_u32 s0, s0, s2
-; GFX6-NEXT: s_subb_u32 s1, s1, s2
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptosi_bf16_i64_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_trunc_f32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x2f800000
-; GFX9-NEXT: v_mul_f32_e64 v1, |v0|, v1
-; GFX9-NEXT: v_floor_f32_e32 v1, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX9-NEXT: v_fma_f32 v0, v1, v2, |v0|
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s2, s0, 31
-; GFX9-NEXT: s_mov_b32 s3, s2
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX9-NEXT: s_sub_u32 s0, s0, s2
-; GFX9-NEXT: s_subb_u32 s1, s1, s2
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptosi_bf16_i64_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v0, s0
+; GFX6789-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX6789-NEXT: v_mul_f32_e64 v1, |v0|, v1
+; GFX6789-NEXT: v_floor_f32_e32 v1, v1
+; GFX6789-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6789-NEXT: v_fma_f32 v0, v1, v2, |v0|
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: s_ashr_i32 s2, s0, 31
+; GFX6789-NEXT: s_mov_b32 s3, s2
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6789-NEXT: s_sub_u32 s0, s0, s2
+; GFX6789-NEXT: s_subb_u32 s1, s1, s2
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptosi_bf16_i64_s:
; GFX12: ; %bb.0:
@@ -308,40 +246,180 @@ define amdgpu_ps i64 @fptosi_bf16_i64_s(bfloat inreg %a) {
}
define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_v(<2 x bfloat> %a) {
-; GFX6-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX6789-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshr_b32 s1, s0, 16
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v1, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s0, s0
+; GFX1250-NEXT: s_cvt_i32_f32 s1, s1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <4 x i32> @fptosi_v4bf16_v4i32_v(<4 x bfloat> %a) {
+; GFX6789-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6789-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <4 x bfloat> %a to <4 x i32>
+ ret <4 x i32> %r
+}
+
+define amdgpu_ps <2 x i16> @fptosi_v2bf16_v2i16_v(<2 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v2bf16_v2i16_v:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX9-LABEL: fptosi_v2bf16_v2i16_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_i32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX12-LABEL: fptosi_v2bf16_v2i16_v:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptosi_v2bf16_v2i32_v:
+; GFX1250-LABEL: fptosi_v2bf16_v2i16_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
@@ -351,15 +429,15 @@ define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_v(<2 x bfloat> %a) {
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptosi <2 x bfloat> %a to <2 x i32>
- ret <2 x i32> %r
+ %r = fptosi <2 x bfloat> %a to <2 x i16>
+ ret <2 x i16> %r
}
-define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
-; GFX6-LABEL: fptosi_v2bf16_v2i32_s:
+define amdgpu_ps <2 x i16> @fptosi_v2bf16_v2i16_s(<2 x bfloat> inreg %a) {
+; GFX6-LABEL: fptosi_v2bf16_v2i16_s:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
@@ -367,10 +445,14 @@ define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_cvt_i32_f32_e32 v1, s0
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: s_lshl_b32 s1, s1, 16
+; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX9-LABEL: fptosi_v2bf16_v2i16_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s1, s0, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
@@ -379,18 +461,20 @@ define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, s0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX12-LABEL: fptosi_v2bf16_v2i16_s:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-NEXT: s_lshl_b32 s0, s0, 16
; GFX12-NEXT: s_lshl_b32 s1, s1, 16
; GFX12-NEXT: s_cvt_i32_f32 s0, s0
; GFX12-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptosi_v2bf16_v2i32_s:
+; GFX1250-LABEL: fptosi_v2bf16_v2i16_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
@@ -401,85 +485,615 @@ define amdgpu_ps <2 x i32> @fptosi_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_cvt_i32_f32 s0, s0
; GFX1250-NEXT: s_cvt_i32_f32 s1, s1
+; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptosi <2 x bfloat> %a to <2 x i32>
- ret <2 x i32> %r
+ %r = fptosi <2 x bfloat> %a to <2 x i16>
+ ret <2 x i16> %r
}
-define amdgpu_ps <4 x i32> @fptosi_v4bf16_v4i32_v(<4 x bfloat> %a) {
-; GFX6-LABEL: fptosi_v4bf16_v4i32_v:
+define amdgpu_ps <2 x i64> @fptosi_v2bf16_v2i64_v(<2 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v2bf16_v2i64_v:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_trunc_f32_e32 v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, 0x2f800000
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_mul_f32_e64 v4, |v2|, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_floor_f32_e32 v4, v4
+; GFX6-NEXT: v_mov_b32_e32 v5, 0xcf800000
+; GFX6-NEXT: v_trunc_f32_e32 v6, v0
+; GFX6-NEXT: v_fma_f32 v2, v4, v5, |v2|
+; GFX6-NEXT: v_mul_f32_e64 v3, |v6|, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_floor_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_fma_f32 v5, v3, v5, |v6|
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX6-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v1
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v4, v5, v0
+; GFX6-NEXT: v_xor_b32_e32 v3, v3, v0
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v0
+; GFX6-NEXT: v_subb_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_readfirstlane_b32 s0, v2
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_readfirstlane_b32 s2, v4
+; GFX6-NEXT: v_readfirstlane_b32 s3, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_v2bf16_v2i64_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX9-NEXT: v_trunc_f32_e32 v2, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x2f800000
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_mul_f32_e64 v4, |v2|, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_floor_f32_e32 v4, v4
+; GFX9-NEXT: v_mov_b32_e32 v5, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v6, v0
+; GFX9-NEXT: v_fma_f32 v2, v4, v5, |v2|
+; GFX9-NEXT: v_mul_f32_e64 v3, |v6|, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_floor_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_fma_f32 v5, v3, v5, |v6|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, v5, v0
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v4, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v4
+; GFX9-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_trunc_f32_e32 v2, v0
+; GFX12-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX12-NEXT: v_trunc_f32_e32 v3, v1
+; GFX12-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v2|
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX12-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v3|
+; GFX12-NEXT: v_floor_f32_e32 v4, v4
+; GFX12-NEXT: v_floor_f32_e32 v5, v5
+; GFX12-NEXT: v_fma_f32 v2, 0xcf800000, v4, |v2|
+; GFX12-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-NEXT: v_fma_f32 v3, 0xcf800000, v5, |v3|
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-NEXT: v_xor_b32_e32 v4, v4, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_xor_b32_e32 v2, v2, v0
+; GFX12-NEXT: v_xor_b32_e32 v5, v5, v1
+; GFX12-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX12-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v0
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v0, null, v4, v0, vcc_lo
+; GFX12-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v1
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v5, v1, vcc_lo
+; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-NEXT: v_readfirstlane_b32 s2, v3
+; GFX12-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v2, 16, v1
+; GFX1250-NEXT: v_trunc_f32_e32 v1, v0
+; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v3, v2
+; GFX1250-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v1|
+; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX1250-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v3|
+; GFX1250-NEXT: v_floor_f32_e32 v4, v4
+; GFX1250-NEXT: v_floor_f32_e32 v5, v5
+; GFX1250-NEXT: v_fma_f32 v6, 0xcf800000, v4, |v1|
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_fma_f32 v3, 0xcf800000, v5, |v3|
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v7, v5
+; GFX1250-NEXT: v_xor_b32_e32 v5, v4, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v8, v3
+; GFX1250-NEXT: v_mov_b32_e32 v3, v2
+; GFX1250-NEXT: v_xor_b32_e32 v4, v6, v0
+; GFX1250-NEXT: v_xor_b32_e32 v7, v7, v2
+; GFX1250-NEXT: v_xor_b32_e32 v6, v8, v2
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[4:5], v[0:1]
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[2:3], v[6:7], v[2:3]
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i64>
+ ret <2 x i64> %r
+}
+
+define amdgpu_ps <2 x i64> @fptosi_v2bf16_v2i64_s(<2 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptosi_v2bf16_v2i64_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s1, s0, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v0, s1
+; GFX6789-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX6789-NEXT: v_mul_f32_e64 v2, |v0|, v1
+; GFX6789-NEXT: v_floor_f32_e32 v2, v2
+; GFX6789-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX6789-NEXT: v_fma_f32 v0, v2, v3, |v0|
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: s_ashr_i32 s2, s1, 31
+; GFX6789-NEXT: s_lshr_b32 s4, s0, 16
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: s_mov_b32 s3, s2
+; GFX6789-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6789-NEXT: s_sub_u32 s0, s0, s2
+; GFX6789-NEXT: s_subb_u32 s1, s1, s2
+; GFX6789-NEXT: s_lshl_b32 s2, s4, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v0, s2
+; GFX6789-NEXT: v_mul_f32_e64 v1, |v0|, v1
+; GFX6789-NEXT: v_floor_f32_e32 v1, v1
+; GFX6789-NEXT: v_fma_f32 v0, v1, v3, |v0|
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: s_ashr_i32 s4, s2, 31
+; GFX6789-NEXT: s_mov_b32 s5, s4
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v0
+; GFX6789-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX6789-NEXT: s_sub_u32 s2, s2, s4
+; GFX6789-NEXT: s_subb_u32 s3, s3, s4
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v2bf16_v2i64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_trunc_f32 s2, s0
+; GFX12-NEXT: s_trunc_f32 s3, s1
+; GFX12-NEXT: s_ashr_i32 s0, s0, 31
+; GFX12-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX12-NEXT: s_bitset0_b32 s3, 31
+; GFX12-NEXT: s_mul_f32 s2, s4, 0x2f800000
+; GFX12-NEXT: s_mul_f32 s5, s3, 0x2f800000
+; GFX12-NEXT: s_floor_f32 s6, s2
+; GFX12-NEXT: s_floor_f32 s7, s5
+; GFX12-NEXT: s_ashr_i32 s2, s1, 31
+; GFX12-NEXT: s_mov_b32 s1, s0
+; GFX12-NEXT: s_fmac_f32 s4, s6, 0xcf800000
+; GFX12-NEXT: s_fmac_f32 s3, s7, 0xcf800000
+; GFX12-NEXT: s_cvt_u32_f32 s5, s6
+; GFX12-NEXT: s_cvt_u32_f32 s7, s7
+; GFX12-NEXT: s_cvt_u32_f32 s4, s4
+; GFX12-NEXT: s_cvt_u32_f32 s6, s3
+; GFX12-NEXT: s_mov_b32 s3, s2
+; GFX12-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]
+; GFX12-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]
+; GFX12-NEXT: s_sub_nc_u64 s[0:1], s[4:5], s[0:1]
+; GFX12-NEXT: s_sub_nc_u64 s[2:3], s[6:7], s[2:3]
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v2bf16_v2i64_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_trunc_f32 s2, s0
+; GFX1250-NEXT: s_trunc_f32 s3, s1
+; GFX1250-NEXT: s_ashr_i32 s0, s0, 31
+; GFX1250-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX1250-NEXT: s_bitset0_b32 s3, 31
+; GFX1250-NEXT: s_mul_f32 s2, s4, 0x2f800000
+; GFX1250-NEXT: s_mul_f32 s5, s3, 0x2f800000
+; GFX1250-NEXT: s_floor_f32 s6, s2
+; GFX1250-NEXT: s_floor_f32 s7, s5
+; GFX1250-NEXT: s_ashr_i32 s2, s1, 31
+; GFX1250-NEXT: s_mov_b32 s1, s0
+; GFX1250-NEXT: s_fmac_f32 s4, s6, 0xcf800000
+; GFX1250-NEXT: s_fmac_f32 s3, s7, 0xcf800000
+; GFX1250-NEXT: s_cvt_u32_f32 s5, s6
+; GFX1250-NEXT: s_cvt_u32_f32 s7, s7
+; GFX1250-NEXT: s_cvt_u32_f32 s4, s4
+; GFX1250-NEXT: s_cvt_u32_f32 s6, s3
+; GFX1250-NEXT: s_mov_b32 s3, s2
+; GFX1250-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]
+; GFX1250-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]
+; GFX1250-NEXT: s_sub_nc_u64 s[0:1], s[4:5], s[0:1]
+; GFX1250-NEXT: s_sub_nc_u64 s[2:3], s[6:7], s[2:3]
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <2 x bfloat> %a to <2 x i64>
+ ret <2 x i64> %r
+}
+
+define amdgpu_ps <3 x i16> @fptosi_v3bf16_v3i16_v(<3 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v3bf16_v3i16_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v2
-; GFX6-NEXT: v_readfirstlane_b32 s2, v1
-; GFX6-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX9-LABEL: fptosi_v3bf16_v3i16_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_i32_f32_sdwa v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v2
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX12-LABEL: fptosi_v3bf16_v3i16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v3bf16_v3i16_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <3 x bfloat> %a to <3 x i16>
+ ret <3 x i16> %r
+}
+
+define amdgpu_ps <3 x i32> @fptosi_v3bf16_v3i32_v(<3 x bfloat> %a) {
+; GFX6789-LABEL: fptosi_v3bf16_v3i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v3bf16_v3i32_v:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
-; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX12-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX12-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX12-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX12-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
-; GFX12-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptosi_v4bf16_v4i32_v:
+; GFX1250-LABEL: fptosi_v3bf16_v3i32_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
-; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX1250-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
-; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptosi <4 x bfloat> %a to <4 x i32>
- ret <4 x i32> %r
+ %r = fptosi <3 x bfloat> %a to <3 x i32>
+ ret <3 x i32> %r
+}
+
+define amdgpu_ps <3 x i32> @fptosi_v3bf16_v3i32_s(<3 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptosi_v3bf16_v3i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshr_b32 s2, s0, 16
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v0, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s2, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v1, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6789-NEXT: v_cvt_i32_f32_e32 v2, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v3bf16_v3i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s2, s0, 16
+; GFX12-NEXT: s_lshr_b32 s3, s0, 16
+; GFX12-NEXT: s_cvt_i32_f32 s0, s2
+; GFX12-NEXT: s_lshl_b32 s2, s3, 16
+; GFX12-NEXT: s_lshl_b32 s3, s1, 16
+; GFX12-NEXT: s_cvt_i32_f32 s1, s2
+; GFX12-NEXT: s_cvt_i32_f32 s2, s3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v3bf16_v3i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s2, s0, 16
+; GFX1250-NEXT: s_lshr_b32 s3, s0, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s0, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s3, 16
+; GFX1250-NEXT: s_lshl_b32 s3, s1, 16
+; GFX1250-NEXT: s_cvt_i32_f32 s1, s2
+; GFX1250-NEXT: s_cvt_i32_f32 s2, s3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <3 x bfloat> %a to <3 x i32>
+ ret <3 x i32> %r
+}
+
+define amdgpu_ps <3 x i64> @fptosi_v3bf16_v3i64_v(<3 x bfloat> %a) {
+; GFX6-LABEL: fptosi_v3bf16_v3i64_v:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX6-NEXT: v_trunc_f32_e32 v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x2f800000
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_mul_f32_e64 v5, |v3|, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_floor_f32_e32 v5, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, 0xcf800000
+; GFX6-NEXT: v_trunc_f32_e32 v7, v0
+; GFX6-NEXT: v_fma_f32 v3, v5, v6, |v3|
+; GFX6-NEXT: v_mul_f32_e64 v8, |v7|, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_floor_f32_e32 v8, v8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT: v_fma_f32 v7, v8, v6, |v7|
+; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX6-NEXT: v_xor_b32_e32 v3, v3, v2
+; GFX6-NEXT: v_xor_b32_e32 v5, v5, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v5, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v5, v7, v0
+; GFX6-NEXT: v_xor_b32_e32 v7, v8, v0
+; GFX6-NEXT: v_trunc_f32_e32 v8, v1
+; GFX6-NEXT: v_mul_f32_e64 v4, |v8|, v4
+; GFX6-NEXT: v_floor_f32_e32 v4, v4
+; GFX6-NEXT: v_fma_f32 v6, v4, v6, |v8|
+; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX6-NEXT: v_subb_u32_e32 v0, vcc, v7, v0, vcc
+; GFX6-NEXT: v_xor_b32_e32 v6, v6, v1
+; GFX6-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v1
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
+; GFX6-NEXT: v_readfirstlane_b32 s0, v3
+; GFX6-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6-NEXT: v_readfirstlane_b32 s2, v5
+; GFX6-NEXT: v_readfirstlane_b32 s3, v0
+; GFX6-NEXT: v_readfirstlane_b32 s4, v6
+; GFX6-NEXT: v_readfirstlane_b32 s5, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: fptosi_v3bf16_v3i64_v:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x2f800000
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_mul_f32_e64 v5, |v3|, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_floor_f32_e32 v5, v5
+; GFX9-NEXT: v_mov_b32_e32 v6, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v7, v0
+; GFX9-NEXT: v_fma_f32 v3, v5, v6, |v3|
+; GFX9-NEXT: v_mul_f32_e64 v8, |v7|, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_floor_f32_e32 v8, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_fma_f32 v7, v8, v6, |v7|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v2
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v2
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, v3, v2
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
+; GFX9-NEXT: v_xor_b32_e32 v5, v7, v0
+; GFX9-NEXT: v_xor_b32_e32 v7, v8, v0
+; GFX9-NEXT: v_trunc_f32_e32 v8, v1
+; GFX9-NEXT: v_mul_f32_e64 v4, |v8|, v4
+; GFX9-NEXT: v_floor_f32_e32 v4, v4
+; GFX9-NEXT: v_fma_f32 v6, v4, v6, |v8|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, v5, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v0, vcc, v7, v0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v6, v6, v1
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v6, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc
+; GFX9-NEXT: v_readfirstlane_b32 s0, v3
+; GFX9-NEXT: v_readfirstlane_b32 s1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s2, v5
+; GFX9-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9-NEXT: v_readfirstlane_b32 s5, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptosi_v3bf16_v3i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_trunc_f32_e32 v3, v2
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_trunc_f32_e32 v4, v1
+; GFX12-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX12-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v3|
+; GFX12-NEXT: v_trunc_f32_e32 v6, v0
+; GFX12-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v4|
+; GFX12-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX12-NEXT: v_floor_f32_e32 v5, v5
+; GFX12-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v6|
+; GFX12-NEXT: v_floor_f32_e32 v7, v7
+; GFX12-NEXT: v_fma_f32 v3, 0xcf800000, v5, |v3|
+; GFX12-NEXT: v_floor_f32_e32 v8, v8
+; GFX12-NEXT: v_fma_f32 v4, 0xcf800000, v7, |v4|
+; GFX12-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_fma_f32 v6, 0xcf800000, v8, |v6|
+; GFX12-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-NEXT: v_xor_b32_e32 v5, v5, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-NEXT: v_xor_b32_e32 v3, v3, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX12-NEXT: v_xor_b32_e32 v7, v7, v1
+; GFX12-NEXT: v_xor_b32_e32 v8, v8, v0
+; GFX12-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v2
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v2, null, v5, v2, vcc_lo
+; GFX12-NEXT: v_xor_b32_e32 v5, v6, v0
+; GFX12-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v1
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v7, v1, vcc_lo
+; GFX12-NEXT: v_sub_co_u32 v5, vcc_lo, v5, v0
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_sub_co_ci_u32_e64 v0, null, v8, v0, vcc_lo
+; GFX12-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s4, v4
+; GFX12-NEXT: v_readfirstlane_b32 s5, v1
+; GFX12-NEXT: v_readfirstlane_b32 s2, v5
+; GFX12-NEXT: v_readfirstlane_b32 s3, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptosi_v3bf16_v3i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX1250-NEXT: v_trunc_f32_e32 v6, v0
+; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v7, v1
+; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX1250-NEXT: v_trunc_f32_e32 v8, v3
+; GFX1250-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v6|
+; GFX1250-NEXT: v_mov_b32_e32 v1, v0
+; GFX1250-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v7|
+; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_ashrrev_i32 v4, 31, v3
+; GFX1250-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v8|
+; GFX1250-NEXT: v_floor_f32_e32 v11, v5
+; GFX1250-NEXT: v_floor_f32_e32 v9, v9
+; GFX1250-NEXT: v_floor_f32_e32 v10, v10
+; GFX1250-NEXT: v_fma_f32 v6, 0xcf800000, v11, |v6|
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX1250-NEXT: v_fma_f32 v12, 0xcf800000, v9, |v7|
+; GFX1250-NEXT: v_mov_b32_e32 v5, v4
+; GFX1250-NEXT: v_fma_f32 v8, 0xcf800000, v10, |v8|
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX1250-NEXT: v_xor_b32_e32 v7, v11, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v11, v12
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v12, v8
+; GFX1250-NEXT: v_xor_b32_e32 v6, v6, v0
+; GFX1250-NEXT: v_xor_b32_e32 v9, v9, v2
+; GFX1250-NEXT: v_xor_b32_e32 v8, v11, v2
+; GFX1250-NEXT: v_xor_b32_e32 v11, v10, v4
+; GFX1250-NEXT: v_xor_b32_e32 v10, v12, v4
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[6:7], v[0:1]
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[2:3], v[8:9], v[2:3]
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[4:5], v[10:11], v[4:5]
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptosi <3 x bfloat> %a to <3 x i64>
+ ret <3 x i64> %r
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
index 4388ae1217140..f978e7229bdda 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptoui.bf16.ll
@@ -1,30 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX6789,GFX6 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX6789,GFX9 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GCN,GFX12 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX1250 %s
define amdgpu_ps i16 @fptoui_bf16_i16_v(bfloat %a) {
-; GFX6-LABEL: fptoui_bf16_i16_v:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i16_v:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fptoui_bf16_i16_v:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fptoui_bf16_i16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fptoui_bf16_i16_v:
; GFX1250: ; %bb.0:
@@ -41,19 +27,12 @@ define amdgpu_ps i16 @fptoui_bf16_i16_v(bfloat %a) {
}
define amdgpu_ps i16 @fptoui_bf16_i16_s(bfloat inreg %a) {
-; GFX6-LABEL: fptoui_bf16_i16_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, s0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i16_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptoui_bf16_i16_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptoui_bf16_i16_s:
; GFX12: ; %bb.0:
@@ -75,26 +54,12 @@ define amdgpu_ps i16 @fptoui_bf16_i16_s(bfloat inreg %a) {
}
define amdgpu_ps i32 @fptoui_bf16_i32_v(bfloat %a) {
-; GFX6-LABEL: fptoui_bf16_i32_v:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i32_v:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: fptoui_bf16_i32_v:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GCN-LABEL: fptoui_bf16_i32_v:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fptoui_bf16_i32_v:
; GFX1250: ; %bb.0:
@@ -111,19 +76,12 @@ define amdgpu_ps i32 @fptoui_bf16_i32_v(bfloat %a) {
}
define amdgpu_ps i32 @fptoui_bf16_i32_s(bfloat inreg %a) {
-; GFX6-LABEL: fptoui_bf16_i32_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, s0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i32_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptoui_bf16_i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptoui_bf16_i32_s:
; GFX12: ; %bb.0:
@@ -145,33 +103,19 @@ define amdgpu_ps i32 @fptoui_bf16_i32_s(bfloat inreg %a) {
}
define amdgpu_ps i64 @fptoui_bf16_i64_v(bfloat %a) {
-; GFX6-LABEL: fptoui_bf16_i64_v:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_trunc_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_floor_f32_e32 v1, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX6-NEXT: v_fma_f32 v0, v1, v2, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i64_v:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_trunc_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_floor_f32_e32 v1, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX9-NEXT: v_fma_f32 v0, v1, v2, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptoui_bf16_i64_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_trunc_f32_e32 v0, v0
+; GFX6789-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6789-NEXT: v_floor_f32_e32 v1, v1
+; GFX6789-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6789-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptoui_bf16_i64_v:
; GFX12: ; %bb.0:
@@ -207,33 +151,19 @@ define amdgpu_ps i64 @fptoui_bf16_i64_v(bfloat %a) {
}
define amdgpu_ps i64 @fptoui_bf16_i64_s(bfloat inreg %a) {
-; GFX6-LABEL: fptoui_bf16_i64_s:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: v_trunc_f32_e32 v0, s0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_floor_f32_e32 v1, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX6-NEXT: v_fma_f32 v0, v1, v2, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: fptoui_bf16_i64_s:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: v_trunc_f32_e32 v0, s0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_floor_f32_e32 v1, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xcf800000
-; GFX9-NEXT: v_fma_f32 v0, v1, v2, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX6789-LABEL: fptoui_bf16_i64_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v0, s0
+; GFX6789-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6789-NEXT: v_floor_f32_e32 v1, v1
+; GFX6789-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6789-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptoui_bf16_i64_s:
; GFX12: ; %bb.0:
@@ -265,40 +195,180 @@ define amdgpu_ps i64 @fptoui_bf16_i64_s(bfloat inreg %a) {
}
define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_v(<2 x bfloat> %a) {
-; GFX6-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX6789-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshr_b32 s1, s0, 16
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: s_cvt_u32_f32 s1, s1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i32>
+ ret <2 x i32> %r
+}
+
+define amdgpu_ps <4 x i32> @fptoui_v4bf16_v4i32_v(<4 x bfloat> %a) {
+; GFX6789-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6789-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <4 x bfloat> %a to <4 x i32>
+ ret <4 x i32> %r
+}
+
+define amdgpu_ps <2 x i16> @fptoui_v2bf16_v2i16_v(<2 x bfloat> %a) {
+; GFX6-LABEL: fptoui_v2bf16_v2i16_v:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX9-LABEL: fptoui_v2bf16_v2i16_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX12-LABEL: fptoui_v2bf16_v2i16_v:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptoui_v2bf16_v2i32_v:
+; GFX1250-LABEL: fptoui_v2bf16_v2i16_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
@@ -308,15 +378,15 @@ define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_v(<2 x bfloat> %a) {
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptoui <2 x bfloat> %a to <2 x i32>
- ret <2 x i32> %r
+ %r = fptoui <2 x bfloat> %a to <2 x i16>
+ ret <2 x i16> %r
}
-define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
-; GFX6-LABEL: fptoui_v2bf16_v2i32_s:
+define amdgpu_ps <2 x i16> @fptoui_v2bf16_v2i16_s(<2 x bfloat> inreg %a) {
+; GFX6-LABEL: fptoui_v2bf16_v2i16_s:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
@@ -324,10 +394,14 @@ define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, s0
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: s_lshl_b32 s1, s1, 16
+; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX9-LABEL: fptoui_v2bf16_v2i16_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s1, s0, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
@@ -336,18 +410,20 @@ define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, s0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX12-LABEL: fptoui_v2bf16_v2i16_s:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-NEXT: s_lshl_b32 s0, s0, 16
; GFX12-NEXT: s_lshl_b32 s1, s1, 16
; GFX12-NEXT: s_cvt_u32_f32 s0, s0
; GFX12-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptoui_v2bf16_v2i32_s:
+; GFX1250-LABEL: fptoui_v2bf16_v2i16_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
@@ -358,85 +434,418 @@ define amdgpu_ps <2 x i32> @fptoui_v2bf16_v2i32_s(<2 x bfloat> inreg %a) {
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
; GFX1250-NEXT: s_cvt_u32_f32 s1, s1
+; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptoui <2 x bfloat> %a to <2 x i32>
- ret <2 x i32> %r
+ %r = fptoui <2 x bfloat> %a to <2 x i16>
+ ret <2 x i16> %r
}
-define amdgpu_ps <4 x i32> @fptoui_v4bf16_v4i32_v(<4 x bfloat> %a) {
-; GFX6-LABEL: fptoui_v4bf16_v4i32_v:
+define amdgpu_ps <2 x i64> @fptoui_v2bf16_v2i64_v(<2 x bfloat> %a) {
+; GFX6789-LABEL: fptoui_v2bf16_v2i64_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_trunc_f32_e32 v0, v0
+; GFX6789-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6789-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX6789-NEXT: v_mul_f32_e32 v4, 0x2f800000, v1
+; GFX6789-NEXT: v_floor_f32_e32 v2, v2
+; GFX6789-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX6789-NEXT: v_floor_f32_e32 v4, v4
+; GFX6789-NEXT: v_fma_f32 v0, v2, v3, v0
+; GFX6789-NEXT: v_fma_f32 v1, v4, v3, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v3, v4
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_trunc_f32_e32 v1, v1
+; GFX12-NEXT: v_dual_mul_f32 v3, 0x2f800000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX12-NEXT: v_trunc_f32_e32 v0, v0
+; GFX12-NEXT: v_floor_f32_e32 v3, v3
+; GFX12-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX12-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v3
+; GFX12-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_readfirstlane_b32 s3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v2
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_trunc_f32_e32 v0, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v1, v1
+; GFX1250-NEXT: v_dual_mul_f32 v2, 0x2f800000, v0 :: v_dual_mul_f32 v3, 0x2f800000, v1
+; GFX1250-NEXT: v_floor_f32_e32 v2, v2
+; GFX1250-NEXT: v_floor_f32_e32 v3, v3
+; GFX1250-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v3
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i64>
+ ret <2 x i64> %r
+}
+
+define amdgpu_ps <2 x i64> @fptoui_v2bf16_v2i64_s(<2 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptoui_v2bf16_v2i64_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshr_b32 s1, s0, 16
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v0, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6789-NEXT: v_trunc_f32_e32 v3, s0
+; GFX6789-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6789-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX6789-NEXT: v_floor_f32_e32 v1, v1
+; GFX6789-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX6789-NEXT: v_floor_f32_e32 v4, v4
+; GFX6789-NEXT: v_fma_f32 v0, v1, v2, v0
+; GFX6789-NEXT: v_fma_f32 v2, v4, v2, v3
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v3, v4
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v2bf16_v2i64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_trunc_f32 s0, s0
+; GFX12-NEXT: s_trunc_f32 s2, s1
+; GFX12-NEXT: s_mul_f32 s1, s0, 0x2f800000
+; GFX12-NEXT: s_mul_f32 s3, s2, 0x2f800000
+; GFX12-NEXT: s_floor_f32 s1, s1
+; GFX12-NEXT: s_floor_f32 s3, s3
+; GFX12-NEXT: s_fmac_f32 s0, s1, 0xcf800000
+; GFX12-NEXT: s_fmac_f32 s2, s3, 0xcf800000
+; GFX12-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-NEXT: s_cvt_u32_f32 s3, s3
+; GFX12-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-NEXT: s_cvt_u32_f32 s2, s2
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v2bf16_v2i64_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_trunc_f32 s0, s0
+; GFX1250-NEXT: s_trunc_f32 s2, s1
+; GFX1250-NEXT: s_mul_f32 s1, s0, 0x2f800000
+; GFX1250-NEXT: s_mul_f32 s3, s2, 0x2f800000
+; GFX1250-NEXT: s_floor_f32 s1, s1
+; GFX1250-NEXT: s_floor_f32 s3, s3
+; GFX1250-NEXT: s_fmac_f32 s0, s1, 0xcf800000
+; GFX1250-NEXT: s_fmac_f32 s2, s3, 0xcf800000
+; GFX1250-NEXT: s_cvt_u32_f32 s1, s1
+; GFX1250-NEXT: s_cvt_u32_f32 s3, s3
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s0
+; GFX1250-NEXT: s_cvt_u32_f32 s2, s2
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <2 x bfloat> %a to <2 x i64>
+ ret <2 x i64> %r
+}
+
+define amdgpu_ps <3 x i16> @fptoui_v3bf16_v3i16_v(<3 x bfloat> %a) {
+; GFX6-LABEL: fptoui_v3bf16_v3i16_v:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v2
-; GFX6-NEXT: v_readfirstlane_b32 s2, v1
-; GFX6-NEXT: v_readfirstlane_b32 s3, v3
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX9-LABEL: fptoui_v3bf16_v3i16_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_sdwa v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v2
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX12-LABEL: fptoui_v3bf16_v3i16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v3bf16_v3i16_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <3 x bfloat> %a to <3 x i16>
+ ret <3 x i16> %r
+}
+
+define amdgpu_ps <3 x i32> @fptoui_v3bf16_v3i32_v(<3 x bfloat> %a) {
+; GFX6789-LABEL: fptoui_v3bf16_v3i32_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v1
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v3bf16_v3i32_v:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
-; GFX12-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
-; GFX12-NEXT: v_readfirstlane_b32 s3, v3
; GFX12-NEXT: ; return to shader part epilog
;
-; GFX1250-LABEL: fptoui_v4bf16_v4i32_v:
+; GFX1250-LABEL: fptoui_v3bf16_v3i32_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
-; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
-; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
; GFX1250-NEXT: ; return to shader part epilog
- %r = fptoui <4 x bfloat> %a to <4 x i32>
- ret <4 x i32> %r
+ %r = fptoui <3 x bfloat> %a to <3 x i32>
+ ret <3 x i32> %r
+}
+
+define amdgpu_ps <3 x i32> @fptoui_v3bf16_v3i32_s(<3 x bfloat> inreg %a) {
+; GFX6789-LABEL: fptoui_v3bf16_v3i32_s:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: s_lshr_b32 s2, s0, 16
+; GFX6789-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s2, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, s0
+; GFX6789-NEXT: s_lshl_b32 s0, s1, 16
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, s0
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v3bf16_v3i32_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s2, s0, 16
+; GFX12-NEXT: s_lshr_b32 s3, s0, 16
+; GFX12-NEXT: s_cvt_u32_f32 s0, s2
+; GFX12-NEXT: s_lshl_b32 s2, s3, 16
+; GFX12-NEXT: s_lshl_b32 s3, s1, 16
+; GFX12-NEXT: s_cvt_u32_f32 s1, s2
+; GFX12-NEXT: s_cvt_u32_f32 s2, s3
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v3bf16_v3i32_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_lshl_b32 s2, s0, 16
+; GFX1250-NEXT: s_lshr_b32 s3, s0, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s0, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s3, 16
+; GFX1250-NEXT: s_lshl_b32 s3, s1, 16
+; GFX1250-NEXT: s_cvt_u32_f32 s1, s2
+; GFX1250-NEXT: s_cvt_u32_f32 s2, s3
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <3 x bfloat> %a to <3 x i32>
+ ret <3 x i32> %r
+}
+
+define amdgpu_ps <3 x i64> @fptoui_v3bf16_v3i64_v(<3 x bfloat> %a) {
+; GFX6789-LABEL: fptoui_v3bf16_v3i64_v:
+; GFX6789: ; %bb.0:
+; GFX6789-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6789-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6789-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6789-NEXT: v_trunc_f32_e32 v0, v0
+; GFX6789-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6789-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6789-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
+; GFX6789-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GFX6789-NEXT: v_mul_f32_e32 v6, 0x2f800000, v1
+; GFX6789-NEXT: v_floor_f32_e32 v3, v3
+; GFX6789-NEXT: v_mov_b32_e32 v4, 0xcf800000
+; GFX6789-NEXT: v_floor_f32_e32 v5, v5
+; GFX6789-NEXT: v_floor_f32_e32 v6, v6
+; GFX6789-NEXT: v_fma_f32 v0, v3, v4, v0
+; GFX6789-NEXT: v_fma_f32 v2, v5, v4, v2
+; GFX6789-NEXT: v_fma_f32 v1, v6, v4, v1
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v4, v6
+; GFX6789-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6789-NEXT: v_readfirstlane_b32 s1, v3
+; GFX6789-NEXT: v_readfirstlane_b32 s2, v2
+; GFX6789-NEXT: v_readfirstlane_b32 s3, v5
+; GFX6789-NEXT: v_readfirstlane_b32 s4, v1
+; GFX6789-NEXT: v_readfirstlane_b32 s5, v4
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptoui_v3bf16_v3i64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-NEXT: v_trunc_f32_e32 v2, v2
+; GFX12-NEXT: v_dual_mul_f32 v5, 0x2f800000, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX12-NEXT: v_trunc_f32_e32 v0, v0
+; GFX12-NEXT: v_floor_f32_e32 v5, v5
+; GFX12-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
+; GFX12-NEXT: v_fmac_f32_e32 v2, 0xcf800000, v5
+; GFX12-NEXT: v_floor_f32_e32 v3, v3
+; GFX12-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v3
+; GFX12-NEXT: v_trunc_f32_e32 v1, v1
+; GFX12-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
+; GFX12-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-NEXT: v_mul_f32_e32 v4, 0x2f800000, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_floor_f32_e32 v4, v4
+; GFX12-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v4
+; GFX12-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-NEXT: v_readfirstlane_b32 s5, v4
+; GFX12-NEXT: v_readfirstlane_b32 s4, v1
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptoui_v3bf16_v3i64_v:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_trunc_f32_e32 v0, v0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX1250-NEXT: v_trunc_f32_e32 v1, v1
+; GFX1250-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
+; GFX1250-NEXT: v_trunc_f32_e32 v2, v2
+; GFX1250-NEXT: v_mul_f32_e32 v4, 0x2f800000, v1
+; GFX1250-NEXT: v_floor_f32_e32 v3, v3
+; GFX1250-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
+; GFX1250-NEXT: v_floor_f32_e32 v4, v4
+; GFX1250-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v3
+; GFX1250-NEXT: v_floor_f32_e32 v5, v5
+; GFX1250-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v4
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_fmac_f32_e32 v2, 0xcf800000, v5
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-NEXT: v_readfirstlane_b32 s5, v4
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-NEXT: ; return to shader part epilog
+ %r = fptoui <3 x bfloat> %a to <3 x i64>
+ ret <3 x i64> %r
}
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