[llvm] [RISCV] Fixed redundant add instructions generated during the fold of vscale add in rvv. (PR #225266)

[Kamlesh Kumar via llvm-commits]

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@@ -3329,9 +3329,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
   if (N0.getOpcode() == ISD::ADD &&
       N0.getOperand(1).getOpcode() == ISD::VSCALE &&
-      N1.getOpcode() == ISD::VSCALE) {
+      N1.getOpcode() == ISD::VSCALE && (TLI.isProfitableToFoldVScaleAdd(N0))) {
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kamleshbhalui wrote:

extra parenthesis not required

https://github.com/llvm/llvm-project/pull/225266