[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jessica Clarke via llvm-commits]

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@@ -84,74 +103,76 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
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jrtc27 wrote:

I would highly recommend doing what we've done for RISC-V and using the numbered register names for things like MIR. Printing an ABI name that doesn't match the current ABI would be way too confusing, and having different register names between ABIs sounds like unnecessary complexity.

https://github.com/llvm/llvm-project/pull/224284