[llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Gheorghe-Teodor Bercea via llvm-commits]

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@@ -379,6 +385,84 @@ bool AMDGPULowerVGPREncoding::runOnMachineInstr(MachineInstr &MI) {
   return false;
 }
 
+void AMDGPULowerVGPREncoding::lowerLoadStoreIdx(MachineInstr &MI) {
+  auto &LdSt = cast<AMDGPUMI::VLoadStoreIdxInst>(MI);
+  MachineBasicBlock &BB = *MI.getParent();
+  const DebugLoc &DL = MI.getDebugLoc();
+  const bool IsStore = LdSt.mayStore();
+
+  Register Data = LdSt.getDataOp().getReg();
+  unsigned Offset = LdSt.getOffsetOp().getImm();
+  unsigned NumDwords = LdSt.getBitWidth() / 32;
+
+  // A statically out-of-range offset is undefined behavior; mask it into the
+  // addressable range below rather than emit an invalid register.
+  unsigned NumAddressableVGPRs = ST->getAddressableNumVGPRs(
+      MI.getMF()->getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize());
+#ifndef NDEBUG
+  bool AllowOffsetWrap = NumAddressableVGPRs == ST->getTotalNumVGPRs();
+  assert((AllowOffsetWrap || Offset + NumDwords <= NumAddressableVGPRs) &&
+         "out of bounds VGPR 'as memory' (address space 13) access");
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doru1004 wrote:

Removed; and is now tested in `as-vgpr-out-of-range.ll`.


https://github.com/llvm/llvm-project/pull/209541