[llvm] Mips: Mark the assembler temporary def dead in FastISel branches (PR #227689)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-mips

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

The conditional branch emitted by FastISel reserves $at for long branch
expansion, which only uses it as a scratch.

Co-Authored-By: Claude Opus 5 <noreply@<!-- -->anthropic.com>

---
Full diff: https://github.com/llvm/llvm-project/pull/227689.diff


2 Files Affected:

- (modified) llvm/lib/Target/Mips/MipsFastISel.cpp (+2-1) 
- (added) llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll (+31) 


``````````diff
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 7d1f024002eaf..c25f1d71090a7 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -983,7 +983,8 @@ bool MipsFastISel::selectBranch(const Instruction *I) {
 
   BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::BGTZ))
       .addReg(ZExtCondReg)
-      .addMBB(TBB);
+      .addMBB(TBB)
+      .setOperandDead(2); // implicit-def $at
   finishCondBranch(BI->getParent(), TBB, FBB);
   return true;
 }
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll b/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll
new file mode 100644
index 0000000000000..5f1f63b205a58
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN:     -stop-after=finalize-isel < %s | FileCheck %s
+
+; The assembler temporary clobbered by long branch expansion is dead.
+
+define void @cond_br(i1 %c) {
+  ; CHECK-LABEL: name: cond_br
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $a0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+  ; CHECK-NEXT:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY1]], 1
+  ; CHECK-NEXT:   BGTZ [[ANDi]], %bb.1, implicit-def dead $at
+  ; CHECK-NEXT:   B %bb.2, implicit-def $at
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1 (%ir-block.1):
+  ; CHECK-NEXT:   RetRA
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2 (%ir-block.2):
+  ; CHECK-NEXT:   RetRA
+  br i1 %c, label %1, label %2
+
+1:
+  ret void
+
+2:
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/227689