[clang] [llvm] [WIP][X86] Replace SSE pmulhw/pmulhuw target intrinsics with generic smulh/umulh (PR #227663)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 04:27:41 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/227663
Fixes #223627
>From ff098f4fba2ec291d7a777c05338d62936a92e3a Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 30 Sep 2026 12:19:54 +0100
Subject: [PATCH] [X86] Replace SSE pmulhw/pmulhuw target intrinsics with
generic smulh/umulh
Fixes #223627
---
clang/lib/CodeGen/TargetBuiltins/X86.cpp | 14 +
clang/test/CodeGen/X86/avx2-builtins.c | 4 +-
clang/test/CodeGen/X86/avx512bw-builtins.c | 12 +-
clang/test/CodeGen/X86/avx512vlbw-builtins.c | 16 +-
clang/test/CodeGen/X86/mmx-builtins.c | 4 +-
clang/test/CodeGen/X86/sse2-builtins.c | 4 +-
llvm/include/llvm/IR/IntrinsicsX86.td | 18 --
llvm/lib/Analysis/ValueTracking.cpp | 14 -
llvm/lib/IR/AutoUpgrade.cpp | 40 +--
.../Target/X86/X86InstCombineIntrinsic.cpp | 68 +----
llvm/lib/Target/X86/X86IntrinsicsInfo.h | 6 -
.../CodeGen/X86/avx2-intrinsics-fast-isel.ll | 8 +-
.../X86/avx2-intrinsics-x86-upgrade.ll | 22 ++
llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll | 32 ---
.../X86/avx512bw-intrinsics-upgrade.ll | 63 ++++
llvm/test/CodeGen/X86/avx512bw-intrinsics.ll | 62 ----
.../X86/avx512bwvl-intrinsics-upgrade.ll | 90 ++++++
.../test/CodeGen/X86/avx512bwvl-intrinsics.ll | 90 ------
.../CodeGen/X86/sse2-intrinsics-fast-isel.ll | 8 +-
.../X86/sse2-intrinsics-x86-upgrade.ll | 42 +++
llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll | 42 ---
.../Transforms/InstCombine/X86/x86-pmulh.ll | 272 ------------------
.../Transforms/InstCombine/X86/x86-pmulhu.ll | 266 -----------------
23 files changed, 294 insertions(+), 903 deletions(-)
delete mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll
delete mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pmulhu.ll
diff --git a/clang/lib/CodeGen/TargetBuiltins/X86.cpp b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
index 5771f10da1d5f..e9b7e28eba31c 100644
--- a/clang/lib/CodeGen/TargetBuiltins/X86.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/X86.cpp
@@ -2362,6 +2362,20 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
}
}
+ case X86::BI__builtin_ia32_pmulhw128:
+ case X86::BI__builtin_ia32_pmulhw256:
+ case X86::BI__builtin_ia32_pmulhw512: {
+ Function *F = CGM.getIntrinsic(Intrinsic::smulh, Ops[0]->getType());
+ return Builder.CreateCall(F, {Ops[0], Ops[1]});
+ }
+
+ case X86::BI__builtin_ia32_pmulhuw128:
+ case X86::BI__builtin_ia32_pmulhuw256:
+ case X86::BI__builtin_ia32_pmulhuw512: {
+ Function *F = CGM.getIntrinsic(Intrinsic::umulh, Ops[0]->getType());
+ return Builder.CreateCall(F, {Ops[0], Ops[1]});
+ }
+
case X86::BI__builtin_ia32_pmuludq128:
case X86::BI__builtin_ia32_pmuludq256:
case X86::BI__builtin_ia32_pmuludq512:
diff --git a/clang/test/CodeGen/X86/avx2-builtins.c b/clang/test/CodeGen/X86/avx2-builtins.c
index a8df1a279ec37..1e6a5eb47fcd4 100644
--- a/clang/test/CodeGen/X86/avx2-builtins.c
+++ b/clang/test/CodeGen/X86/avx2-builtins.c
@@ -1051,14 +1051,14 @@ TEST_CONSTEXPR(match_m256i(_mm256_mul_epu32((__m256i)(__v8si){+1, -2, +3, -4, +5
__m256i test_mm256_mulhi_epu16(__m256i a, __m256i b) {
// CHECK-LABEL: test_mm256_mulhi_epu16
- // CHECK: call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
+ // CHECK: call <16 x i16> @llvm.umulh.v16i16(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
return _mm256_mulhi_epu16(a, b);
}
TEST_CONSTEXPR(match_v16hi(_mm256_mulhi_epu16((__m256i)(__v16hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16}, (__m256i)(__v16hi){-32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), 0, -32, 0, 25, 4, -28, 0, 17, 8, -24, 0, 9, 12, 5, 14, 1));
__m256i test_mm256_mulhi_epi16(__m256i a, __m256i b) {
// CHECK-LABEL: test_mm256_mulhi_epi16
- // CHECK: call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
+ // CHECK: call <16 x i16> @llvm.smulh.v16i16(<16 x i16> %{{.*}}, <16 x i16> %{{.*}})
return _mm256_mulhi_epi16(a, b);
}
TEST_CONSTEXPR(match_v16hi(_mm256_mulhi_epi16((__m256i)(__v16hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16}, (__m256i)(__v16hi){-32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, -1, -1, -1));
diff --git a/clang/test/CodeGen/X86/avx512bw-builtins.c b/clang/test/CodeGen/X86/avx512bw-builtins.c
index 427efbbb99af8..26136602c968b 100644
--- a/clang/test/CodeGen/X86/avx512bw-builtins.c
+++ b/clang/test/CodeGen/X86/avx512bw-builtins.c
@@ -1959,14 +1959,14 @@ TEST_CONSTEXPR(match_v32hi(_mm512_maskz_mulhrs_epi16(0x0000FFFF, (__m512i)(__v32
__m512i test_mm512_mulhi_epi16(__m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
return _mm512_mulhi_epi16(__A,__B);
}
TEST_CONSTEXPR(match_v32hi(_mm512_mulhi_epi16((__m512i)(__v32hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16, +17, -18, +19, -20, +21, -22, +23, -24, +25, -26, +27, -28, +29, -30, +31, -32}, (__m512i)(__v32hi){-64, -62, +60, +58, -56, -54, +52, +50, -48, -46, +44, +42, -40, -38, +36, +34, -32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, 0, 0, -1, -1, -1, -1, -1));
__m512i test_mm512_mask_mulhi_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mask_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_mask_mulhi_epi16(__W,__U,__A,__B);
}
@@ -1974,7 +1974,7 @@ TEST_CONSTEXPR(match_v32hi(_mm512_mask_mulhi_epi16(_mm512_set1_epi16(1), 0xF00FF
__m512i test_mm512_maskz_mulhi_epi16(__mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_maskz_mulhi_epi16
- // CHECK: @llvm.x86.avx512.pmulh.w.512
+ // CHECK: @llvm.smulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_maskz_mulhi_epi16(__U,__A,__B);
}
@@ -1982,14 +1982,14 @@ TEST_CONSTEXPR(match_v32hi(_mm512_maskz_mulhi_epi16(0x0FF00FF0, (__m512i)(__v32h
__m512i test_mm512_mulhi_epu16(__m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
return _mm512_mulhi_epu16(__A,__B);
}
TEST_CONSTEXPR(match_v32hi(_mm512_mulhi_epu16((__m512i)(__v32hi){+1, -2, +3, -4, +5, -6, +7, -8, +9, -10, +11, -12, +13, -14, +15, -16, +17, -18, +19, -20, +21, -22, +23, -24, +25, -26, +27, -28, +29, -30, +31, -32}, (__m512i)(__v32hi){-64, -62, +60, +58, -56, -54, +52, +50, -48, -46, +44, +42, -40, -38, +36, +34, -32, -30, +28, +26, -24, -22, +20, +18, -16, -14, +12, +10, -8, +6, -4, +2}), 0, -64, 0, 57, 4, -60, 0, 49, 8, -56, 0, 41, 12, -52, 0, 33, 16, -48, 0, 25, 20, -44, 0, 17, 24, -40, 0, 9, 28, 5, 30, 1));
__m512i test_mm512_mask_mulhi_epu16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_mask_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_mask_mulhi_epu16(__W,__U,__A,__B);
}
@@ -1997,7 +1997,7 @@ TEST_CONSTEXPR(match_v32hi(_mm512_mask_mulhi_epu16(_mm512_set1_epi16(1), 0x0FF00
__m512i test_mm512_maskz_mulhi_epu16(__mmask32 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: test_mm512_maskz_mulhi_epu16
- // CHECK: @llvm.x86.avx512.pmulhu.w.512
+ // CHECK: @llvm.umulh.v32i16
// CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
return _mm512_maskz_mulhi_epu16(__U,__A,__B);
}
diff --git a/clang/test/CodeGen/X86/avx512vlbw-builtins.c b/clang/test/CodeGen/X86/avx512vlbw-builtins.c
index 048a424f8ac2b..f8ac120752bf1 100644
--- a/clang/test/CodeGen/X86/avx512vlbw-builtins.c
+++ b/clang/test/CodeGen/X86/avx512vlbw-builtins.c
@@ -2223,7 +2223,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_maskz_mulhrs_epi16(0xF00F, (__m256i)(__v16hi){
__m128i test_mm_mask_mulhi_epu16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_mask_mulhi_epu16
- // CHECK: @llvm.x86.sse2.pmulhu.w
+ // CHECK: @llvm.umulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_mulhi_epu16(__W, __U, __A, __B);
}
@@ -2231,7 +2231,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_mask_mulhi_epu16(_mm_set1_epi16(1), 0x3C, (__m128i
__m128i test_mm_maskz_mulhi_epu16(__mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_maskz_mulhi_epu16
- // CHECK: @llvm.x86.sse2.pmulhu.w
+ // CHECK: @llvm.umulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_maskz_mulhi_epu16(__U, __A, __B);
}
@@ -2239,7 +2239,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_maskz_mulhi_epu16(0x87, (__m128i)(__v8hi){+1, -2,
__m256i test_mm256_mask_mulhi_epu16(__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_mask_mulhi_epu16
- // CHECK: @llvm.x86.avx2.pmulhu.w
+ // CHECK: @llvm.umulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_mulhi_epu16(__W, __U, __A, __B);
}
@@ -2247,7 +2247,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_mask_mulhi_epu16(_mm256_set1_epi16(1), 0xF00F,
__m256i test_mm256_maskz_mulhi_epu16(__mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_maskz_mulhi_epu16
- // CHECK: @llvm.x86.avx2.pmulhu.w
+ // CHECK: @llvm.umulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_maskz_mulhi_epu16(__U, __A, __B);
}
@@ -2255,7 +2255,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_maskz_mulhi_epu16(0x0FF0, (__m256i)(__v16hi){+
__m128i test_mm_mask_mulhi_epi16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_mask_mulhi_epi16
- // CHECK: @llvm.x86.sse2.pmulh.w
+ // CHECK: @llvm.smulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_mulhi_epi16(__W, __U, __A, __B);
}
@@ -2263,7 +2263,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_mask_mulhi_epu16(_mm_set1_epi16(1), 0x78, (__m128i
__m128i test_mm_maskz_mulhi_epi16(__mmask8 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: test_mm_maskz_mulhi_epi16
- // CHECK: @llvm.x86.sse2.pmulh.w
+ // CHECK: @llvm.smulh.v8i16
// CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_maskz_mulhi_epi16(__U, __A, __B);
}
@@ -2271,7 +2271,7 @@ TEST_CONSTEXPR(match_v8hi(_mm_maskz_mulhi_epi16(0xC3, (__m128i)(__v8hi){+1, -2,
__m256i test_mm256_mask_mulhi_epi16(__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_mask_mulhi_epi16
- // CHECK: @llvm.x86.avx2.pmulh.w
+ // CHECK: @llvm.smulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_mulhi_epi16(__W, __U, __A, __B);
}
@@ -2279,7 +2279,7 @@ TEST_CONSTEXPR(match_v16hi(_mm256_mask_mulhi_epi16(_mm256_set1_epi16(1), 0x0FF0,
__m256i test_mm256_maskz_mulhi_epi16(__mmask16 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: test_mm256_maskz_mulhi_epi16
- // CHECK: @llvm.x86.avx2.pmulh.w
+ // CHECK: @llvm.smulh.v16i16
// CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_maskz_mulhi_epi16(__U, __A, __B);
}
diff --git a/clang/test/CodeGen/X86/mmx-builtins.c b/clang/test/CodeGen/X86/mmx-builtins.c
index 3cae57b6500c8..8ede0eb962a1d 100644
--- a/clang/test/CodeGen/X86/mmx-builtins.c
+++ b/clang/test/CodeGen/X86/mmx-builtins.c
@@ -434,14 +434,14 @@ TEST_CONSTEXPR(match_m64(_mm_mul_su32((__m64)(__v2si){+1, -2}, (__m64)(__v2si){-
__m64 test_mm_mulhi_pi16(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_mulhi_pi16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(
+ // CHECK: call <8 x i16> @llvm.smulh.v8i16(
return _mm_mulhi_pi16(a, b);
}
TEST_CONSTEXPR(match_v4hi(_mm_mulhi_pi16((__m64)(__v4hi){+1, -2, +3, -4}, (__m64)(__v4hi){-10, +8, +6, -4}), -1, -1, 0, 0));
__m64 test_mm_mulhi_pu16(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_mulhi_pu16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulhu.w(
+ // CHECK: call <8 x i16> @llvm.umulh.v8i16(
return _mm_mulhi_pu16(a, b);
}
TEST_CONSTEXPR(match_v4hi(_mm_mulhi_pu16((__m64)(__v4hi){+1, -2, +3, -4}, (__m64)(__v4hi){-10, +8, +6, -4}), 0, 7, 0, -8));
diff --git a/clang/test/CodeGen/X86/sse2-builtins.c b/clang/test/CodeGen/X86/sse2-builtins.c
index c0c4acf2daea5..5f5adbfd59542 100644
--- a/clang/test/CodeGen/X86/sse2-builtins.c
+++ b/clang/test/CodeGen/X86/sse2-builtins.c
@@ -1020,14 +1020,14 @@ TEST_CONSTEXPR(match_m128d(_mm_mul_sd((__m128d){+1.0, -3.0}, (__m128d){+5.0, -5.
__m128i test_mm_mulhi_epi16(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_mulhi_epi16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
+ // CHECK: call <8 x i16> @llvm.smulh.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
return _mm_mulhi_epi16(A, B);
}
TEST_CONSTEXPR(match_v8hi(_mm_mulhi_epi16((__m128i)(__v8hi){+1, -2, +3, -4, +5, -6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -8, +6, -4, +2}), -1, 0, 0, -1, -1, -1, -1, -1));
__m128i test_mm_mulhi_epu16(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_mulhi_epu16
- // CHECK: call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
+ // CHECK: call <8 x i16> @llvm.umulh.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
return _mm_mulhi_epu16(A, B);
}
TEST_CONSTEXPR(match_v8hi(_mm_mulhi_epu16((__m128i)(__v8hi){+1, -2, +3, -4, +5, -6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -8, +6, -4, +2}), 0, -16, 0, 9, 4, 5, 6, 1));
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index a315b234a39cf..3617008d2ee8e 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -329,12 +329,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_sse2_pmulhu_w : ClangBuiltin<"__builtin_ia32_pmulhuw128">,
- DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_sse2_pmulh_w : ClangBuiltin<"__builtin_ia32_pmulhw128">,
- DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- llvm_v8i16_ty], [IntrNoMem, Commutative]>;
def int_x86_sse2_pmadd_wd : ClangBuiltin<"__builtin_ia32_pmaddwd128">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
@@ -1336,12 +1330,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_avx2_pmulhu_w : ClangBuiltin<"__builtin_ia32_pmulhuw256">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
- llvm_v16i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_avx2_pmulh_w : ClangBuiltin<"__builtin_ia32_pmulhw256">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
- llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmadd_wd : ClangBuiltin<"__builtin_ia32_pmaddwd256">,
DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
@@ -3760,12 +3748,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
}
// Integer arithmetic ops
let TargetPrefix = "x86" in {
- def int_x86_avx512_pmulhu_w_512 : ClangBuiltin<"__builtin_ia32_pmulhuw512">,
- DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty],
- [IntrNoMem, Commutative]>;
- def int_x86_avx512_pmulh_w_512 : ClangBuiltin<"__builtin_ia32_pmulhw512">,
- DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty],
- [IntrNoMem, Commutative]>;
def int_x86_avx512_pavg_b_512 : ClangBuiltin<"__builtin_ia32_pavgb512">,
DefaultAttrsIntrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty, llvm_v64i8_ty],
[IntrNoMem]>;
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 650d07364bee1..eb3d7f50ae40a 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -2277,20 +2277,6 @@ static void computeKnownBitsFromOperator(const Operator *I,
Known &= Known2.anyextOrTrunc(BitWidth);
break;
}
- case Intrinsic::x86_sse2_pmulh_w:
- case Intrinsic::x86_avx2_pmulh_w:
- case Intrinsic::x86_avx512_pmulh_w_512:
- computeKnownBits(I->getOperand(0), DemandedElts, Known, Q, Depth + 1);
- computeKnownBits(I->getOperand(1), DemandedElts, Known2, Q, Depth + 1);
- Known = KnownBits::mulhs(Known, Known2);
- break;
- case Intrinsic::x86_sse2_pmulhu_w:
- case Intrinsic::x86_avx2_pmulhu_w:
- case Intrinsic::x86_avx512_pmulhu_w_512:
- computeKnownBits(I->getOperand(0), DemandedElts, Known, Q, Depth + 1);
- computeKnownBits(I->getOperand(1), DemandedElts, Known2, Q, Depth + 1);
- Known = KnownBits::mulhu(Known, Known2);
- break;
case Intrinsic::x86_sse42_crc32_64_64:
Known.Zero.setBitsFrom(32);
break;
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 43651371e730d..526ec7f6ee3b7 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -212,6 +212,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name.starts_with("pmin") || // Added in 3.9
Name.starts_with("pmovsx") || // Added in 3.9
Name.starts_with("pmovzx") || // Added in 3.9
+ Name.starts_with("pmulh.w") || // Added in 24.0
+ Name.starts_with("pmulhu.w") || // Added in 24.0
Name == "pmul.dq" || // Added in 7.0
Name == "pmulu.dq" || // Added in 7.0
Name.starts_with("psll.dq") || // Added in 3.7
@@ -438,6 +440,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name == "kxor.w" || // Added in 7.0
Name.starts_with("padds.") || // Added in 8.0
Name.starts_with("pbroadcast") || // Added in 3.9
+ Name.starts_with("pmulh.w") || // Added in 24.0
+ Name.starts_with("pmulhu.w") || // Added in 24.0
Name.starts_with("prol") || // Added in 8.0
Name.starts_with("pror") || // Added in 8.0
Name.starts_with("psll.dq") || // Added in 3.9
@@ -490,6 +494,8 @@ static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
Name == "pmaxu.b" || // Added in 3.9
Name == "pmins.w" || // Added in 3.9
Name == "pminu.b" || // Added in 3.9
+ Name == "pmulh.w" || // Added in 24.0
+ Name == "pmulhu.w" || // Added in 24.0
Name == "pmulu.dq" || // Added in 7.0
Name.starts_with("pshuf") || // Added in 3.9
Name.starts_with("psll.dq") || // Added in 3.7
@@ -3057,24 +3063,16 @@ static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder,
IID = Intrinsic::x86_avx512_pmul_hr_sw_512;
else
llvm_unreachable("Unexpected intrinsic");
- } else if (Name.starts_with("pmulh.w.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse2_pmulh_w;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmulh_w;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmulh_w_512;
- else
- llvm_unreachable("Unexpected intrinsic");
- } else if (Name.starts_with("pmulhu.w.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse2_pmulhu_w;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmulhu_w;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmulhu_w_512;
- else
- llvm_unreachable("Unexpected intrinsic");
+ } else if (Name.starts_with("pmulh.w")) {
+ assert((VecWidth == 128 || VecWidth == 256 || VecWidth == 512) &&
+ "Unexpected intrinsic");
+ Rep = upgradeX86BinaryIntrinsics(Builder, CI, Intrinsic::smulh);
+ return true;
+ } else if (Name.starts_with("pmulhu.w")) {
+ assert((VecWidth == 128 || VecWidth == 256 || VecWidth == 512) &&
+ "Unexpected intrinsic");
+ Rep = upgradeX86BinaryIntrinsics(Builder, CI, Intrinsic::umulh);
+ return true;
} else if (Name.starts_with("pmaddw.d.")) {
if (VecWidth == 128)
IID = Intrinsic::x86_sse2_pmadd_wd;
@@ -3773,6 +3771,12 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F,
Name == "sse41.pminud" || Name.starts_with("avx2.pminu") ||
Name.starts_with("avx512.mask.pminu")) {
Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umin);
+ } else if (Name == "sse2.pmulh.w" || Name.starts_with("avx2.pmulh.w") ||
+ Name.starts_with("avx512.pmulh.w")) {
+ Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smulh);
+ } else if (Name == "sse2.pmulhu.w" || Name.starts_with("avx2.pmulhu.w") ||
+ Name.starts_with("avx512.pmulhu.w")) {
+ Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umulh);
} else if (Name == "sse2.pmulu.dq" || Name == "avx2.pmulu.dq" ||
Name == "avx512.pmulu.dq.512" ||
Name.starts_with("avx512.mask.pmulu.dq.")) {
diff --git a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
index 55d67084b7513..07fa36594c37e 100644
--- a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
@@ -496,16 +496,14 @@ static Value *simplifyX86pack(IntrinsicInst &II,
return Builder.CreateTrunc(Shuffle, ResTy);
}
-static Value *simplifyX86pmulh(IntrinsicInst &II,
- InstCombiner::BuilderTy &Builder, bool IsSigned,
- bool IsRounding) {
+static Value *simplifyX86pmulhrsw(IntrinsicInst &II,
+ InstCombiner::BuilderTy &Builder) {
Value *Arg0 = II.getArgOperand(0);
Value *Arg1 = II.getArgOperand(1);
auto *ResTy = cast<FixedVectorType>(II.getType());
auto *ArgTy = cast<FixedVectorType>(Arg0->getType());
assert(ArgTy == ResTy && ResTy->getScalarSizeInBits() == 16 &&
"Unexpected PMULH types");
- assert((!IsRounding || IsSigned) && "PMULHRS instruction must be signed");
// Multiply by undef -> zero (NOT undef!) as other arg could still be zero.
if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))
@@ -515,42 +513,24 @@ static Value *simplifyX86pmulh(IntrinsicInst &II,
if (isa<ConstantAggregateZero>(Arg0) || isa<ConstantAggregateZero>(Arg1))
return ConstantAggregateZero::get(ResTy);
- // Multiply by one.
- if (!IsRounding) {
- if (match(Arg0, m_One()))
- return IsSigned ? Builder.CreateAShr(Arg1, 15)
- : ConstantAggregateZero::get(ResTy);
- if (match(Arg1, m_One()))
- return IsSigned ? Builder.CreateAShr(Arg0, 15)
- : ConstantAggregateZero::get(ResTy);
- }
-
// Constant folding.
if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
return nullptr;
// Extend to twice the width and multiply.
- auto Cast =
- IsSigned ? Instruction::CastOps::SExt : Instruction::CastOps::ZExt;
auto *ExtTy = FixedVectorType::getExtendedElementVectorType(ArgTy);
- Value *LHS = Builder.CreateCast(Cast, Arg0, ExtTy);
- Value *RHS = Builder.CreateCast(Cast, Arg1, ExtTy);
+ Value *LHS = Builder.CreateSExt(Arg0, ExtTy);
+ Value *RHS = Builder.CreateSExt(Arg1, ExtTy);
Value *Mul = Builder.CreateMul(LHS, RHS);
- if (IsRounding) {
- // PMULHRSW: truncate to vXi18 of the most significant bits, add one and
- // extract bits[16:1].
- auto *RndEltTy = IntegerType::get(ExtTy->getContext(), 18);
- auto *RndTy = FixedVectorType::get(RndEltTy, ExtTy);
- Mul = Builder.CreateLShr(Mul, 14);
- Mul = Builder.CreateTrunc(Mul, RndTy);
- Mul = Builder.CreateAdd(Mul, ConstantInt::get(RndTy, 1));
- Mul = Builder.CreateLShr(Mul, 1);
- } else {
- // PMULH/PMULHU: extract the vXi16 most significant bits.
- Mul = Builder.CreateLShr(Mul, 16);
- }
-
+ // PMULHRSW: truncate to vXi18 of the most significant bits, add one and
+ // extract bits[16:1].
+ auto *RndEltTy = IntegerType::get(ExtTy->getContext(), 18);
+ auto *RndTy = FixedVectorType::get(RndEltTy, ExtTy);
+ Mul = Builder.CreateLShr(Mul, 14);
+ Mul = Builder.CreateTrunc(Mul, RndTy);
+ Mul = Builder.CreateAdd(Mul, ConstantInt::get(RndTy, 1));
+ Mul = Builder.CreateLShr(Mul, 1);
return Builder.CreateTrunc(Mul, ResTy);
}
@@ -2637,26 +2617,10 @@ X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
}
break;
- case Intrinsic::x86_sse2_pmulh_w:
- case Intrinsic::x86_avx2_pmulh_w:
- case Intrinsic::x86_avx512_pmulh_w_512:
- if (Value *V = simplifyX86pmulh(II, IC.Builder, true, false)) {
- return IC.replaceInstUsesWith(II, V);
- }
- break;
-
- case Intrinsic::x86_sse2_pmulhu_w:
- case Intrinsic::x86_avx2_pmulhu_w:
- case Intrinsic::x86_avx512_pmulhu_w_512:
- if (Value *V = simplifyX86pmulh(II, IC.Builder, false, false)) {
- return IC.replaceInstUsesWith(II, V);
- }
- break;
-
case Intrinsic::x86_ssse3_pmul_hr_sw_128:
case Intrinsic::x86_avx2_pmul_hr_sw:
case Intrinsic::x86_avx512_pmul_hr_sw_512:
- if (Value *V = simplifyX86pmulh(II, IC.Builder, true, true)) {
+ if (Value *V = simplifyX86pmulhrsw(II, IC.Builder)) {
return IC.replaceInstUsesWith(II, V);
}
break;
@@ -3364,12 +3328,6 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
break;
}
- case Intrinsic::x86_sse2_pmulh_w:
- case Intrinsic::x86_avx2_pmulh_w:
- case Intrinsic::x86_avx512_pmulh_w_512:
- case Intrinsic::x86_sse2_pmulhu_w:
- case Intrinsic::x86_avx2_pmulhu_w:
- case Intrinsic::x86_avx512_pmulhu_w_512:
case Intrinsic::x86_ssse3_pmul_hr_sw_128:
case Intrinsic::x86_avx2_pmul_hr_sw:
case Intrinsic::x86_avx512_pmul_hr_sw_512: {
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 213c508b4a8b0..4b563b397c840 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -867,8 +867,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx2_pmadd_wd, INTR_TYPE_2OP, X86ISD::VPMADDWD, 0),
X86_INTRINSIC_DATA(avx2_pmovmskb, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
X86_INTRINSIC_DATA(avx2_pmul_hr_sw, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
- X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
- X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
X86_INTRINSIC_DATA(avx2_psad_bw, INTR_TYPE_2OP, X86ISD::PSADBW, 0),
X86_INTRINSIC_DATA(avx2_pshuf_b, INTR_TYPE_2OP, X86ISD::PSHUFB, 0),
X86_INTRINSIC_DATA(avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
@@ -1418,8 +1416,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
0),
X86_INTRINSIC_DATA(avx512_pmaddw_d_512, INTR_TYPE_2OP, X86ISD::VPMADDWD, 0),
X86_INTRINSIC_DATA(avx512_pmul_hr_sw_512, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
- X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
- X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
X86_INTRINSIC_DATA(avx512_pmultishift_qb_128, INTR_TYPE_2OP,
X86ISD::MULTISHIFT, 0),
X86_INTRINSIC_DATA(avx512_pmultishift_qb_256, INTR_TYPE_2OP,
@@ -2112,8 +2108,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(sse2_pavg_w, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
X86_INTRINSIC_DATA(sse2_pmadd_wd, INTR_TYPE_2OP, X86ISD::VPMADDWD, 0),
X86_INTRINSIC_DATA(sse2_pmovmskb_128, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
- X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
- X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
X86_INTRINSIC_DATA(sse2_psad_bw, INTR_TYPE_2OP, X86ISD::PSADBW, 0),
X86_INTRINSIC_DATA(sse2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
X86_INTRINSIC_DATA(sse2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
index 818065aaa57d8..5f399e8cd4d07 100644
--- a/llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
@@ -1837,11 +1837,11 @@ define <4 x i64> @test_mm256_mulhi_epi16(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
- %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %arg0, <16 x i16> %arg1)
+ %res = call <16 x i16> @llvm.smulh.v16i16(<16 x i16> %arg0, <16 x i16> %arg1)
%bc = bitcast <16 x i16> %res to <4 x i64>
ret <4 x i64> %bc
}
-declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
+declare <16 x i16> @llvm.smulh.v16i16(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhi_epu16(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: test_mm256_mulhi_epu16:
@@ -1850,11 +1850,11 @@ define <4 x i64> @test_mm256_mulhi_epu16(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
- %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %arg0, <16 x i16> %arg1)
+ %res = call <16 x i16> @llvm.umulh.v16i16(<16 x i16> %arg0, <16 x i16> %arg1)
%bc = bitcast <16 x i16> %res to <4 x i64>
ret <4 x i64> %bc
}
-declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
+declare <16 x i16> @llvm.umulh.v16i16(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhrs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: test_mm256_mulhrs_epi16:
diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
index 0cbaa4f63a74c..6c26627288e5c 100644
--- a/llvm/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
@@ -638,6 +638,28 @@ define <16 x i16> @test_x86_avx2_paddus_w(<16 x i16> %a0, <16 x i16> %a1) {
declare <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16>, <16 x i16>) nounwind readnone
+define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: test_x86_avx2_pmulh_w:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+ ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: test_x86_avx2_pmulhu_w:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+ ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
define <32 x i8> @test_x86_avx2_psubs_b(<32 x i8> %a0, <32 x i8> %a1) {
; CHECK-LABEL: test_x86_avx2_psubs_b:
; CHECK: ## %bb.0:
diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
index 6b994b0782e6f..4781b4f427428 100644
--- a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -219,38 +219,6 @@ define i32 @test_x86_avx2_pmovmskb(<32 x i8> %a0) {
declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone
-define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmulh_w:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmulh_w:
-; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
- ret <16 x i16> %res
-}
-declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
-
-
-define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmulhu_w:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
-; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
- ret <16 x i16> %res
-}
-declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
-
-
define <4 x i64> @test_x86_avx2_psad_bw(<32 x i8> %a0, <32 x i8> %a1) {
; AVX2-LABEL: test_x86_avx2_psad_bw:
; AVX2: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
index 51ffeca52a665..4ce541904936d 100644
--- a/llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
@@ -2754,6 +2754,18 @@ define <32 x i16> @test_int_x86_avx512_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %
ret <32 x i16> %res
}
+declare <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16>, <32 x i16>)
+
+define <32 x i16> @test2_int_x86_avx512_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
+; CHECK-LABEL: test2_int_x86_avx512_pmulhu_w_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmulhuw %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xe4,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1)
+ ret <32 x i16> %1
+}
+
+
define <32 x i16> @test_int_x86_avx512_mask_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) nounwind {
; X86-LABEL: test_int_x86_avx512_mask_pmulhu_w_512:
; X86: # %bb.0:
@@ -2774,6 +2786,26 @@ define <32 x i16> @test_int_x86_avx512_mask_pmulhu_w_512(<32 x i16> %x0, <32 x i
declare <32 x i16> @llvm.x86.avx512.mask.pmulh.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+define <32 x i16> @test2_int_x86_avx512_mask_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
+; X86-LABEL: test2_int_x86_avx512_mask_pmulhu_w_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vpmulhuw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe4,0xd1]
+; X86-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_mask_pmulhu_w_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhuw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe4,0xd1]
+; X64-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1)
+ %2 = bitcast i32 %x3 to <32 x i1>
+ %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %x2
+ ret <32 x i16> %3
+}
+
define <32 x i16> @test_int_x86_avx512_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) nounwind {
; CHECK-LABEL: test_int_x86_avx512_pmulh_w_512:
; CHECK: # %bb.0:
@@ -2783,6 +2815,17 @@ define <32 x i16> @test_int_x86_avx512_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x
ret <32 x i16> %res
}
+declare <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16>, <32 x i16>)
+
+define <32 x i16> @test2_int_x86_avx512_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
+; CHECK-LABEL: test2_int_x86_avx512_pmulh_w_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmulhw %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xe5,0xc1]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1)
+ ret <32 x i16> %1
+}
+
define <32 x i16> @test_int_x86_avx512_mask_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) nounwind {
; X86-LABEL: test_int_x86_avx512_mask_pmulh_w_512:
; X86: # %bb.0:
@@ -2801,6 +2844,26 @@ define <32 x i16> @test_int_x86_avx512_mask_pmulh_w_512(<32 x i16> %x0, <32 x i1
ret <32 x i16> %res
}
+define <32 x i16> @test2_int_x86_avx512_mask_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
+; X86-LABEL: test2_int_x86_avx512_mask_pmulh_w_512:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vpmulhw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe5,0xd1]
+; X86-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_mask_pmulh_w_512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe5,0xd1]
+; X64-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1)
+ %2 = bitcast i32 %x3 to <32 x i1>
+ %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %x2
+ ret <32 x i16> %3
+}
+
declare <32 x i16> @llvm.x86.avx512.mask.pmul.hr.sw.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
define <32 x i16> @test_int_x86_avx512_pmulhr_sw_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) nounwind {
diff --git a/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
index 5b58233ac51aa..b1cca9d274c8f 100644
--- a/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
@@ -872,68 +872,6 @@ define <64 x i8>@test_int_x86_avx512_pshuf_b_512_maskz(<64 x i8> %x0, <64 x i8>
ret <64 x i8> %res2
}
-declare <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16>, <32 x i16>)
-
-define <32 x i16> @test_int_x86_avx512_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
-; CHECK-LABEL: test_int_x86_avx512_pmulhu_w_512:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmulhuw %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xe4,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @test_int_x86_avx512_mask_pmulhu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulhu_w_512:
-; X86: # %bb.0:
-; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vpmulhuw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe4,0xd1]
-; X86-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulhu_w_512:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhuw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe4,0xd1]
-; X64-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1)
- %2 = bitcast i32 %x3 to <32 x i1>
- %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %x2
- ret <32 x i16> %3
-}
-
-declare <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16>, <32 x i16>)
-
-define <32 x i16> @test_int_x86_avx512_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
-; CHECK-LABEL: test_int_x86_avx512_pmulh_w_512:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpmulhw %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xe5,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @test_int_x86_avx512_mask_pmulh_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulh_w_512:
-; X86: # %bb.0:
-; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vpmulhw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe5,0xd1]
-; X86-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulh_w_512:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhw %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x49,0xe5,0xd1]
-; X64-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1)
- %2 = bitcast i32 %x3 to <32 x i1>
- %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %x2
- ret <32 x i16> %3
-}
-
declare <32 x i16> @llvm.x86.avx512.pmul.hr.sw.512(<32 x i16>, <32 x i16>)
define <32 x i16> @test_int_x86_avx512_pmulhr_sw_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2) {
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
index ae710cc40a522..3a5d0245e16df 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
@@ -6393,6 +6393,29 @@ define <8 x i16>@test_int_x86_avx512_pmulhu_w_128(<8 x i16> %x0, <8 x i16> %x1,
ret <8 x i16> %res
}
+declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test2_int_x86_avx512_pmulhu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
+; X86-LABEL: test2_int_x86_avx512_pmulhu_w_128:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
+; X86-NEXT: kmovd %eax, %k1 # encoding: [0xc5,0xfb,0x92,0xc8]
+; X86-NEXT: vpmulhuw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe4,0xd1]
+; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_pmulhu_w_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhuw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe4,0xd1]
+; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %x0, <8 x i16> %x1)
+ %2 = bitcast i8 %x3 to <8 x i1>
+ %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %x2
+ ret <8 x i16> %3
+}
+
define <8 x i16>@test_int_x86_avx512_mask_pmulhu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_pmulhu_w_128:
; X86: # %bb.0:
@@ -6414,6 +6437,28 @@ define <8 x i16>@test_int_x86_avx512_mask_pmulhu_w_128(<8 x i16> %x0, <8 x i16>
declare <16 x i16> @llvm.x86.avx512.mask.pmulhu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+define <16 x i16> @test2_int_x86_avx512_mask_pmulhu_w_128(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
+; X86-LABEL: test2_int_x86_avx512_mask_pmulhu_w_128:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vpmulhuw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe4,0xd1]
+; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_mask_pmulhu_w_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhuw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe4,0xd1]
+; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %x0, <16 x i16> %x1)
+ %2 = bitcast i16 %x3 to <16 x i1>
+ %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %x2
+ ret <16 x i16> %3
+}
+
+declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>)
+
define <16 x i16>@test_int_x86_avx512_pmulhu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2) {
; CHECK-LABEL: test_int_x86_avx512_pmulhu_w_256:
; CHECK: # %bb.0:
@@ -6473,6 +6518,29 @@ define <8 x i16>@test_int_x86_avx512_mask_pmulh_w_128(<8 x i16> %x0, <8 x i16> %
declare <16 x i16> @llvm.x86.avx512.mask.pmulh.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+define <8 x i16> @test2_int_x86_avx512_mask_pmulh_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
+; X86-LABEL: test2_int_x86_avx512_mask_pmulh_w_128:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
+; X86-NEXT: kmovd %eax, %k1 # encoding: [0xc5,0xfb,0x92,0xc8]
+; X86-NEXT: vpmulhw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe5,0xd1]
+; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_mask_pmulh_w_128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe5,0xd1]
+; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %x0, <8 x i16> %x1)
+ %2 = bitcast i8 %x3 to <8 x i1>
+ %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %x2
+ ret <8 x i16> %3
+}
+
+declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>)
+
define <16 x i16>@test_int_x86_avx512_pmulh_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2) {
; CHECK-LABEL: test_int_x86_avx512_pmulh_w_256:
; CHECK: # %bb.0:
@@ -6500,6 +6568,28 @@ define <16 x i16>@test_int_x86_avx512_mask_pmulh_w_256(<16 x i16> %x0, <16 x i16
ret <16 x i16> %res
}
+define <16 x i16> @test2_int_x86_avx512_mask_pmulh_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
+; X86-LABEL: test2_int_x86_avx512_mask_pmulh_w_256:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vpmulhw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe5,0xd1]
+; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test2_int_x86_avx512_mask_pmulh_w_256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vpmulhw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe5,0xd1]
+; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+ %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %x0, <16 x i16> %x1)
+ %2 = bitcast i16 %x3 to <16 x i1>
+ %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %x2
+ ret <16 x i16> %3
+}
+
+declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>)
+
declare <8 x i16> @llvm.x86.avx512.mask.pmul.hr.sw.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_pmulhr_sw_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2) {
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
index 01b153b4fbc61..5a28b66df6804 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
@@ -1375,96 +1375,6 @@ define <16 x i16> @test_int_x86_avx512_mask_pavg_w_256(<16 x i16> %x0, <16 x i16
ret <16 x i16> %3
}
-declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>)
-
-define <8 x i16> @test_int_x86_avx512_mask_pmulhu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulhu_w_128:
-; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
-; X86-NEXT: kmovd %eax, %k1 # encoding: [0xc5,0xfb,0x92,0xc8]
-; X86-NEXT: vpmulhuw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe4,0xd1]
-; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulhu_w_128:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhuw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe4,0xd1]
-; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %x0, <8 x i16> %x1)
- %2 = bitcast i8 %x3 to <8 x i1>
- %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %x2
- ret <8 x i16> %3
-}
-
-declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>)
-
-define <16 x i16> @test_int_x86_avx512_mask_pmulhu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulhu_w_256:
-; X86: # %bb.0:
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vpmulhuw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe4,0xd1]
-; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulhu_w_256:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhuw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe4,0xd1]
-; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %x0, <16 x i16> %x1)
- %2 = bitcast i16 %x3 to <16 x i1>
- %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %x2
- ret <16 x i16> %3
-}
-
-declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>)
-
-define <8 x i16> @test_int_x86_avx512_mask_pmulh_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulh_w_128:
-; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
-; X86-NEXT: kmovd %eax, %k1 # encoding: [0xc5,0xfb,0x92,0xc8]
-; X86-NEXT: vpmulhw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe5,0xd1]
-; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulh_w_128:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhw %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0xe5,0xd1]
-; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %x0, <8 x i16> %x1)
- %2 = bitcast i8 %x3 to <8 x i1>
- %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %x2
- ret <8 x i16> %3
-}
-
-declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>)
-
-define <16 x i16> @test_int_x86_avx512_mask_pmulh_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) {
-; X86-LABEL: test_int_x86_avx512_mask_pmulh_w_256:
-; X86: # %bb.0:
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vpmulhw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe5,0xd1]
-; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; X86-NEXT: retl # encoding: [0xc3]
-;
-; X64-LABEL: test_int_x86_avx512_mask_pmulh_w_256:
-; X64: # %bb.0:
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vpmulhw %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf1,0x7d,0x29,0xe5,0xd1]
-; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; X64-NEXT: retq # encoding: [0xc3]
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %x0, <16 x i16> %x1)
- %2 = bitcast i16 %x3 to <16 x i1>
- %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %x2
- ret <16 x i16> %3
-}
-
declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>)
define <8 x i16> @test_int_x86_avx512_mask_pmulhr_sw_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
index a48be037ebebc..19110474141d0 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
@@ -3135,11 +3135,11 @@ define <2 x i64> @test_mm_mulhi_epi16(<2 x i64> %a0, <2 x i64> %a1) {
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
- %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %arg0, <8 x i16> %arg1)
+ %res = call <8 x i16> @llvm.smulh.v8i16(<8 x i16> %arg0, <8 x i16> %arg1)
%bc = bitcast <8 x i16> %res to <2 x i64>
ret <2 x i64> %bc
}
-declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
+declare <8 x i16> @llvm.smulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
define <2 x i64> @test_mm_mulhi_epu16(<2 x i64> %a0, <2 x i64> %a1) {
; SSE-LABEL: test_mm_mulhi_epu16:
@@ -3158,11 +3158,11 @@ define <2 x i64> @test_mm_mulhi_epu16(<2 x i64> %a0, <2 x i64> %a1) {
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
- %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %arg0, <8 x i16> %arg1)
+ %res = call <8 x i16> @llvm.umulh.v8i16(<8 x i16> %arg0, <8 x i16> %arg1)
%bc = bitcast <8 x i16> %res to <2 x i64>
ret <2 x i64> %bc
}
-declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
+declare <8 x i16> @llvm.umulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
define <2 x i64> @test_mm_mullo_epi16(<2 x i64> %a0, <2 x i64> %a1) {
; SSE-LABEL: test_mm_mullo_epi16:
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
index ff295d1a71439..f95b7658c5a9e 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
@@ -926,6 +926,48 @@ define <8 x i16> @test_x86_sse2_paddus_w(<8 x i16> %a0, <8 x i16> %a1) {
declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone
+define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) {
+; SSE-LABEL: test_x86_sse2_pmulh_w:
+; SSE: ## %bb.0:
+; SSE-NEXT: pmulhw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe5,0xc1]
+; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; AVX1-LABEL: test_x86_sse2_pmulh_w:
+; AVX1: ## %bb.0:
+; AVX1-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe5,0xc1]
+; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; AVX512-LABEL: test_x86_sse2_pmulh_w:
+; AVX512: ## %bb.0:
+; AVX512-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe5,0xc1]
+; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+ %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %res
+}
+declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+
+define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) {
+; SSE-LABEL: test_x86_sse2_pmulhu_w:
+; SSE: ## %bb.0:
+; SSE-NEXT: pmulhuw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe4,0xc1]
+; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; AVX1-LABEL: test_x86_sse2_pmulhu_w:
+; AVX1: ## %bb.0:
+; AVX1-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe4,0xc1]
+; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; AVX512-LABEL: test_x86_sse2_pmulhu_w:
+; AVX512: ## %bb.0:
+; AVX512-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe4,0xc1]
+; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+ %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %res
+}
+declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+
define <16 x i8> @test_x86_sse2_psubs_b(<16 x i8> %a0, <16 x i8> %a1) {
; SSE-LABEL: test_x86_sse2_psubs_b:
; SSE: ## %bb.0:
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
index 4d5725e2504fd..0da7cf0e6194c 100644
--- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
@@ -1025,48 +1025,6 @@ define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) {
declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
-define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) {
-; SSE-LABEL: test_x86_sse2_pmulh_w:
-; SSE: ## %bb.0:
-; SSE-NEXT: pmulhw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe5,0xc1]
-; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX1-LABEL: test_x86_sse2_pmulh_w:
-; AVX1: ## %bb.0:
-; AVX1-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe5,0xc1]
-; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512-LABEL: test_x86_sse2_pmulh_w:
-; AVX512: ## %bb.0:
-; AVX512-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe5,0xc1]
-; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
- %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
- ret <8 x i16> %res
-}
-declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
-
-
-define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) {
-; SSE-LABEL: test_x86_sse2_pmulhu_w:
-; SSE: ## %bb.0:
-; SSE-NEXT: pmulhuw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe4,0xc1]
-; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX1-LABEL: test_x86_sse2_pmulhu_w:
-; AVX1: ## %bb.0:
-; AVX1-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe4,0xc1]
-; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512-LABEL: test_x86_sse2_pmulhu_w:
-; AVX512: ## %bb.0:
-; AVX512-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe4,0xc1]
-; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
- %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
- ret <8 x i16> %res
-}
-declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
-
-
define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) {
; SSE-LABEL: test_x86_sse2_psad_bw:
; SSE: ## %bb.0:
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll b/llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll
deleted file mode 100644
index 4d4d619ea7cb4..0000000000000
--- a/llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll
+++ /dev/null
@@ -1,272 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
-
-;
-; UNDEF Elts
-;
-
-define <8 x i16> @undef_pmulh_128(<8 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_128(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> undef)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @undef_pmulh_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_128_commute(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> undef, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @undef_pmulh_256(<16 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_256(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> undef)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @undef_pmulh_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_256_commute(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> undef, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @undef_pmulh_512(<32 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_512(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %a0, <32 x i16> undef)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @undef_pmulh_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulh_512_commute(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> undef, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Zero Elts
-;
-
-define <8 x i16> @zero_pmulh_128(<8 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_128(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> zeroinitializer)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @zero_pmulh_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_128_commute(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> zeroinitializer, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @zero_pmulh_256(<16 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_256(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> zeroinitializer)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @zero_pmulh_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_256_commute(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> zeroinitializer, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @zero_pmulh_512(<32 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_512(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %a0, <32 x i16> zeroinitializer)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @zero_pmulh_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulh_512_commute(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> zeroinitializer, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Multiply by One
-;
-
-define <8 x i16> @one_pmulh_128(<8 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_128(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <8 x i16> [[TMP1]]
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @one_pmulh_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_128_commute(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <8 x i16> [[TMP1]]
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @one_pmulh_256(<16 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_256(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <16 x i16> [[TMP1]]
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @one_pmulh_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_256_commute(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <16 x i16> [[TMP1]]
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @one_pmulh_512(<32 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_512(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <32 x i16> [[TMP1]]
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %a0, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @one_pmulh_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @one_pmulh_512_commute(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[A0:%.*]], splat (i16 15)
-; CHECK-NEXT: ret <32 x i16> [[TMP1]]
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Constant Folding
-;
-
-define <8 x i16> @fold_pmulh_128() {
-; CHECK-LABEL: @fold_pmulh_128(
-; CHECK-NEXT: ret <8 x i16> <i16 0, i16 0, i16 -2, i16 -2, i16 0, i16 -1, i16 -4, i16 -4>
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8>, <8 x i16> <i16 -5, i16 7, i16 -32768, i16 32765, i16 -9, i16 -11, i16 -32763, i16 32761>)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @fold_pmulh_256() {
-; CHECK-LABEL: @fold_pmulh_256(
-; CHECK-NEXT: ret <16 x i16> <i16 0, i16 -1, i16 -1, i16 1, i16 0, i16 0, i16 -3, i16 3, i16 -1, i16 -1, i16 4, i16 5, i16 -1, i16 -1, i16 6, i16 -8>
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> <i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15>, <16 x i16> <i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756>)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @fold_pmulh_512() {
-; CHECK-LABEL: @fold_pmulh_512(
-; CHECK-NEXT: ret <32 x i16> <i16 0, i16 -1, i16 -1, i16 1, i16 0, i16 0, i16 -3, i16 3, i16 -1, i16 -1, i16 4, i16 5, i16 -1, i16 -1, i16 6, i16 -8, i16 0, i16 -1, i16 -1, i16 1, i16 0, i16 0, i16 -3, i16 3, i16 -1, i16 -1, i16 4, i16 5, i16 -1, i16 -1, i16 6, i16 -8>
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> <i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15, i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756>, <32 x i16> <i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756, i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15>)
- ret <32 x i16> %1
-}
-
-;
-; Demanded Elts
-;
-
-define <8 x i16> @elts_pmulh_128(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulh_128(
-; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: ret <8 x i16> [[TMP2]]
-;
- %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>
- %2 = shufflevector <8 x i16> %a1, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
- %3 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %1, <8 x i16> %2)
- %4 = shufflevector <8 x i16> %3, <8 x i16> poison, <8 x i32> zeroinitializer
- ret <8 x i16> %4
-}
-
-define <16 x i16> @elts_pmulh_256(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulh_256(
-; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> zeroinitializer
-; CHECK-NEXT: ret <16 x i16> [[TMP2]]
-;
- %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %2 = shufflevector <16 x i16> %a1, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %3 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %1, <16 x i16> %2)
- %4 = shufflevector <16 x i16> %3, <16 x i16> poison, <16 x i32> zeroinitializer
- ret <16 x i16> %4
-}
-
-define <32 x i16> @elts_pmulh_512(<32 x i16> %a0, <32 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulh_512(
-; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> [[A0:%.*]], <32 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> poison, <32 x i32> zeroinitializer
-; CHECK-NEXT: ret <32 x i16> [[TMP2]]
-;
- %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %2 = shufflevector <32 x i16> %a1, <32 x i16> undef, <32 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %3 = call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %1, <32 x i16> %2)
- %4 = shufflevector <32 x i16> %3, <32 x i16> poison, <32 x i32> zeroinitializer
- ret <32 x i16> %4
-}
-
-;
-; Known Bits
-;
-
-define <8 x i16> @known_pmulh_128(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-; CHECK-LABEL: @known_pmulh_128(
-; CHECK-NEXT: ret <8 x i16> [[A2:%.*]]
-;
- %x0 = lshr <8 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <8 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %x0, <8 x i16> %x1)
- %r = add <8 x i16> %m, %a2
- ret <8 x i16> %r
-}
-
-define <16 x i16> @known_pmulh_256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2) {
-; CHECK-LABEL: @known_pmulh_256(
-; CHECK-NEXT: ret <16 x i16> [[A2:%.*]]
-;
- %x0 = lshr <16 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <16 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %x0, <16 x i16> %x1)
- %r = add <16 x i16> %m, %a2
- ret <16 x i16> %r
-}
-
-define <32 x i16> @known_pmulh_512(<32 x i16> %a0, <32 x i16> %a1, <32 x i16> %a2) {
-; CHECK-LABEL: @known_pmulh_512(
-; CHECK-NEXT: ret <32 x i16> [[A2:%.*]]
-;
- %x0 = lshr <32 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <32 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <32 x i16> @llvm.x86.avx512.pmulh.w.512(<32 x i16> %x0, <32 x i16> %x1)
- %r = add <32 x i16> %m, %a2
- ret <32 x i16> %r
-}
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pmulhu.ll b/llvm/test/Transforms/InstCombine/X86/x86-pmulhu.ll
deleted file mode 100644
index 560969f7c4a81..0000000000000
--- a/llvm/test/Transforms/InstCombine/X86/x86-pmulhu.ll
+++ /dev/null
@@ -1,266 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
-
-;
-; UNDEF Elts
-;
-
-define <8 x i16> @undef_pmulhu_128(<8 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_128(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> undef)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @undef_pmulhu_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_128_commute(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> undef, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @undef_pmulhu_256(<16 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_256(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> undef)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @undef_pmulhu_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_256_commute(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> undef, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @undef_pmulhu_512(<32 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_512(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %a0, <32 x i16> undef)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @undef_pmulhu_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @undef_pmulhu_512_commute(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> undef, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Zero Elts
-;
-
-define <8 x i16> @zero_pmulhu_128(<8 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_128(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> zeroinitializer)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @zero_pmulhu_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_128_commute(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> zeroinitializer, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @zero_pmulhu_256(<16 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_256(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> zeroinitializer)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @zero_pmulhu_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_256_commute(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> zeroinitializer, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @zero_pmulhu_512(<32 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_512(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %a0, <32 x i16> zeroinitializer)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @zero_pmulhu_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @zero_pmulhu_512_commute(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> zeroinitializer, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Multiply by One
-;
-
-define <8 x i16> @one_pmulhu_128(<8 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_128(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <8 x i16> %1
-}
-
-define <8 x i16> @one_pmulhu_128_commute(<8 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_128_commute(
-; CHECK-NEXT: ret <8 x i16> zeroinitializer
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @one_pmulhu_256(<16 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_256(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <16 x i16> %1
-}
-
-define <16 x i16> @one_pmulhu_256_commute(<16 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_256_commute(
-; CHECK-NEXT: ret <16 x i16> zeroinitializer
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <16 x i16> %a0)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @one_pmulhu_512(<32 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_512(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %a0, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <32 x i16> %1
-}
-
-define <32 x i16> @one_pmulhu_512_commute(<32 x i16> %a0) {
-; CHECK-LABEL: @one_pmulhu_512_commute(
-; CHECK-NEXT: ret <32 x i16> zeroinitializer
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <32 x i16> %a0)
- ret <32 x i16> %1
-}
-
-;
-; Constant Folding
-;
-
-define <8 x i16> @fold_pmulhu_128() {
-; CHECK-LABEL: @fold_pmulhu_128(
-; CHECK-NEXT: ret <8 x i16> <i16 -6, i16 0, i16 1, i16 32763, i16 -14, i16 5, i16 3, i16 32757>
-;
- %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> <i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8>, <8 x i16> <i16 -5, i16 7, i16 -32768, i16 32765, i16 -9, i16 -11, i16 -32763, i16 32761>)
- ret <8 x i16> %1
-}
-
-define <16 x i16> @fold_pmulhu_256() {
-; CHECK-LABEL: @fold_pmulhu_256(
-; CHECK-NEXT: ret <16 x i16> <i16 0, i16 6, i16 1, i16 1, i16 -13, i16 -16, i16 3, i16 3, i16 12, i16 8, i16 -32766, i16 5, i16 16, i16 12, i16 -32764, i16 32748>
-;
- %1 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> <i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15>, <16 x i16> <i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756>)
- ret <16 x i16> %1
-}
-
-define <32 x i16> @fold_pmulhu_512() {
-; CHECK-LABEL: @fold_pmulhu_512(
-; CHECK-NEXT: ret <32 x i16> <i16 0, i16 6, i16 1, i16 1, i16 -13, i16 -16, i16 3, i16 3, i16 12, i16 8, i16 -32766, i16 5, i16 16, i16 12, i16 -32764, i16 32748, i16 0, i16 6, i16 1, i16 1, i16 -13, i16 -16, i16 3, i16 3, i16 12, i16 8, i16 -32766, i16 5, i16 16, i16 12, i16 -32764, i16 32748>
-;
- %1 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> <i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15, i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756>, <32 x i16> <i16 -5, i16 7, i16 -32768, i16 32766, i16 -9, i16 -11, i16 -32764, i16 32762, i16 13, i16 -15, i16 -32760, i16 32758, i16 17, i16 -19, i16 -32756, i16 32756, i16 0, i16 -1, i16 2, i16 3, i16 -4, i16 -5, i16 6, i16 7, i16 -8, i16 9, i16 -10, i16 11, i16 -12, i16 13, i16 -14, i16 -15>)
- ret <32 x i16> %1
-}
-
-;
-; Demanded Elts
-;
-
-define <8 x i16> @elts_pmulhu_128(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulhu_128(
-; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: ret <8 x i16> [[TMP2]]
-;
- %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>
- %2 = shufflevector <8 x i16> %a1, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
- %3 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %1, <8 x i16> %2)
- %4 = shufflevector <8 x i16> %3, <8 x i16> poison, <8 x i32> zeroinitializer
- ret <8 x i16> %4
-}
-
-define <16 x i16> @elts_pmulhu_256(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulhu_256(
-; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> zeroinitializer
-; CHECK-NEXT: ret <16 x i16> [[TMP2]]
-;
- %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %2 = shufflevector <16 x i16> %a1, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %3 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %1, <16 x i16> %2)
- %4 = shufflevector <16 x i16> %3, <16 x i16> poison, <16 x i32> zeroinitializer
- ret <16 x i16> %4
-}
-
-define <32 x i16> @elts_pmulhu_512(<32 x i16> %a0, <32 x i16> %a1) {
-; CHECK-LABEL: @elts_pmulhu_512(
-; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> [[A0:%.*]], <32 x i16> [[A1:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> poison, <32 x i32> zeroinitializer
-; CHECK-NEXT: ret <32 x i16> [[TMP2]]
-;
- %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 0, i32 1, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %2 = shufflevector <32 x i16> %a1, <32 x i16> undef, <32 x i32> <i32 0, i32 1, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %3 = call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %1, <32 x i16> %2)
- %4 = shufflevector <32 x i16> %3, <32 x i16> poison, <32 x i32> zeroinitializer
- ret <32 x i16> %4
-}
-
-;
-; Known Bits
-;
-
-define <8 x i16> @known_pmulhu_128(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-; CHECK-LABEL: @known_pmulhu_128(
-; CHECK-NEXT: ret <8 x i16> [[A2:%.*]]
-;
- %x0 = lshr <8 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <8 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %x0, <8 x i16> %x1)
- %r = add <8 x i16> %m, %a2
- ret <8 x i16> %r
-}
-
-define <16 x i16> @known_pmulhu_256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2) {
-; CHECK-LABEL: @known_pmulhu_256(
-; CHECK-NEXT: ret <16 x i16> [[A2:%.*]]
-;
- %x0 = lshr <16 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <16 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %x0, <16 x i16> %x1)
- %r = add <16 x i16> %m, %a2
- ret <16 x i16> %r
-}
-
-define <32 x i16> @known_pmulhu_512(<32 x i16> %a0, <32 x i16> %a1, <32 x i16> %a2) {
-; CHECK-LABEL: @known_pmulhu_512(
-; CHECK-NEXT: ret <32 x i16> [[A2:%.*]]
-;
- %x0 = lshr <32 x i16> %a0, <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
- %x1 = and <32 x i16> %a1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
- %m = tail call <32 x i16> @llvm.x86.avx512.pmulhu.w.512(<32 x i16> %x0, <32 x i16> %x1)
- %r = add <32 x i16> %m, %a2
- ret <32 x i16> %r
-}
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