[llvm] [Gisel] smin/umin optimization rewrites (PR #203939)
Luisa Cicolini via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 04:26:02 PDT 2026
https://github.com/luisacicolini updated https://github.com/llvm/llvm-project/pull/203939
>From 775f07cb956c0e6564024df3f8a38d660b2c5dde Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Mon, 15 Jun 2026 17:13:15 +0100
Subject: [PATCH 01/13] test
---
.../include/llvm/Target/GlobalISel/Combine.td | 26 ++-
.../AArch64/GlobalISel/combine-max-min.mir | 159 ++++++++++++++++++
2 files changed, 184 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index b61e229a3a44b..bf21645317676 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2444,6 +2444,28 @@ def SubUmaxSub: GICombineRule<
MRI.hasOneNonDBGUse(${max}.getReg()); }]),
(apply (G_SUB $sub1, 0, $A),
(G_UMIN $root, $A, $sub1))>;
+
+// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
+def SubSminSub: GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $sub, 0, $A),
+ (G_SMIN $max, $A, $sub),
+ (G_SUB $root, 0, $max),
+ [{ return MRI.hasOneNonDBGUse(${sub}.getReg()) &&
+ MRI.hasOneNonDBGUse(${max}.getReg()); }]),
+ (apply (G_SUB $sub1, 0, $A),
+ (G_SMAX $root, $A, $sub1))>;
+
+// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
+def SubUminSub: GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $sub, 0, $A),
+ (G_UMIN $max, $A, $sub),
+ (G_SUB $root, 0, $max),
+ [{ return MRI.hasOneNonDBGUse(${sub}.getReg()) &&
+ MRI.hasOneNonDBGUse(${max}.getReg()); }]),
+ (apply (G_SUB $sub1, 0, $A),
+ (G_UMAX $root, $A, $sub1))>;
def integer_reassoc_combines: GICombineGroup<[
APlusBMinusCMinusB,
@@ -2469,7 +2491,9 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
- SubUmaxSub
+ SubUmaxSub,
+ SubSminSub,
+ SubUminSub
]>;
// fold (A+(shl (0-B), C)) -> (A-(shl B, C))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index cfb9f2a761cd8..717144518b97a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -156,3 +156,162 @@ body: |
%mul:_(i64) = G_MUL %max, %sub2
$x0 = COPY %mul
RET_ReallyLR implicit $x0
+
+
+...
+---
+name: ASubSMin
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubSMin
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %sub2:_(s64) = G_SMAX %a, [[SUB]]
+ ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_SMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ $x0 = COPY %sub2
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubSMinVec
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: ASubSMinVec
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: %c:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB %c1, %a
+ ; CHECK-NEXT: %sub2:_(<4 x s32>) = G_SMAX %a, [[SUB]]
+ ; CHECK-NEXT: $q0 = COPY %sub2(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %c:_(s32) = G_CONSTANT i32 0
+ %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ %sub1:_(<4 x s32>) = G_SUB %c1, %a
+ %max:_(<4 x s32>) = G_SMIN %a, %sub1
+ %sub2:_(<4 x s32>) = G_SUB %c1, %max
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: ASubSMinOneUse
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubSMinOneUse
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %sub1:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %max:_(s64) = G_SMIN %a, %sub1
+ ; CHECK-NEXT: %sub2:_(s64) = G_SUB %zero, %max
+ ; CHECK-NEXT: %mul:_(s64) = G_MUL %max, %sub2
+ ; CHECK-NEXT: $x0 = COPY %mul(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_SMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ %mul:_(s64) = G_MUL %max, %sub2
+ $x0 = COPY %mul
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubUMin
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubUMin
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %sub2:_(s64) = G_UMAX %a, [[SUB]]
+ ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_UMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ $x0 = COPY %sub2
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubUMinVec
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: ASubUMinVec
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: %c:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB %c1, %a
+ ; CHECK-NEXT: %sub2:_(<4 x s32>) = G_UMAX %a, [[SUB]]
+ ; CHECK-NEXT: $q0 = COPY %sub2(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %c:_(s32) = G_CONSTANT i32 0
+ %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ %sub1:_(<4 x s32>) = G_SUB %c1, %a
+ %max:_(<4 x s32>) = G_UMIN %a, %sub1
+ %sub2:_(<4 x s32>) = G_SUB %c1, %max
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: ASubUMinOneUse
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubUMinOneUse
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %sub1:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %max:_(s64) = G_UMIN %a, %sub1
+ ; CHECK-NEXT: %sub2:_(s64) = G_SUB %zero, %max
+ ; CHECK-NEXT: %mul:_(s64) = G_MUL %max, %sub2
+ ; CHECK-NEXT: $x0 = COPY %mul(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_UMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ %mul:_(s64) = G_MUL %max, %sub2
+ $x0 = COPY %mul
+ RET_ReallyLR implicit $x0
>From b3363b5cdaac2a10717bdc68a942b513f8027145 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Wed, 30 Sep 2026 12:05:30 +0100
Subject: [PATCH 02/13] add file
---
.../AArch64/GlobalISel/combine-max-min.ll | 171 ++++++++++++++++++
1 file changed, 171 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
new file mode 100644
index 0000000000000..43380fe76316f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -global-isel -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; 0 - smax(a, 0 - a) -> smin(a, 0 - a) (i.e. -abs(a))
+define i64 @ASubSMax(i64 %a) {
+; CHECK-SD-LABEL: ASubSMax:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubSMax:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, ge
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %max = call i64 @llvm.smax.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %max
+ ret i64 %sub2
+}
+
+; Extra use of %max blocks the combine.
+define i64 @ASubSMaxOneUse(i64 %a) {
+; CHECK-LABEL: ASubSMaxOneUse:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x0
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cneg x8, x0, le
+; CHECK-NEXT: mneg x0, x8, x8
+; CHECK-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %max = call i64 @llvm.smax.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %max
+ %mul = mul i64 %max, %sub2
+ ret i64 %mul
+}
+
+; 0 - smax(a, 0 - a) -> smin(a, 0 - a) (i.e. -abs(a))
+define <4 x i32> @ASubSMaxVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubSMaxVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %max
+ ret <4 x i32> %sub2
+}
+
+; 0 - umax(a, 0 - a) -> umin(a, 0 - a)
+define i64 @ASubUMax(i64 %a) {
+; CHECK-SD-LABEL: ASubUMax:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubUMax:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, hs
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %max = call i64 @llvm.umax.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %max
+ ret i64 %sub2
+}
+
+; 0 - umax(a, 0 - a) -> umin(a, 0 - a)
+define <4 x i32> @ASubUMaxVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubUMaxVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %max = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %max
+ ret <4 x i32> %sub2
+}
+
+define i64 @ASubSMin(i64 %a) {
+; CHECK-SD-LABEL: ASubSMin:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubSMin:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, le
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.smin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ ret i64 %sub2
+}
+
+; Extra use of %min blocks the combine.
+define i64 @ASubSMinOneUse(i64 %a) {
+; CHECK-LABEL: ASubSMinOneUse:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x0
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cneg x8, x0, ge
+; CHECK-NEXT: mneg x0, x8, x8
+; CHECK-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.smin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ %mul = mul i64 %min, %sub2
+ ret i64 %mul
+}
+
+; 0 - smin(a, 0 - a) -> smax(a, 0 - a) (i.e. -abs(a))
+define <4 x i32> @ASubSMinVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubSMinVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %min
+ ret <4 x i32> %sub2
+}
+
+; 0 - umin(a, 0 - a) -> umax(a, 0 - a)
+define i64 @ASubUMin(i64 %a) {
+; CHECK-SD-LABEL: ASubUMin:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubUMin:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, ls
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ ret i64 %sub2
+}
+
+; 0 - umin(a, 0 - a) -> umax(a, 0 - a)
+define <4 x i32> @ASubUMinVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubUMinVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %min
+ ret <4 x i32> %sub2
+}
+
>From 69469a9ecc7bf54f5dfda5740604abaf62f70bf8 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Mon, 15 Jun 2026 17:30:16 +0100
Subject: [PATCH 03/13] Apply suggestion from @luisacicolini
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index bf21645317676..3c9694f8a4293 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2491,7 +2491,7 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
- SubUmaxSub,
+ SubUmaxSub,
SubSminSub,
SubUminSub
]>;
>From cb03294a4d8400b695dc8212bb4e04f9e7904095 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:07 +0100
Subject: [PATCH 04/13] Update llvm/include/llvm/Target/GlobalISel/Combine.td
Co-authored-by: Jay Foad <jay.foad at gmail.com>
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 3c9694f8a4293..7b967a5328687 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2445,8 +2445,8 @@ def SubUmaxSub: GICombineRule<
(apply (G_SUB $sub1, 0, $A),
(G_UMIN $root, $A, $sub1))>;
-// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
-def SubSminSub: GICombineRule<
+// (sub 0, (smin X, (sub 0, X))) --> (smax X, (sub 0, X))
+def NegSminNeg: GICombineRule<
(defs root:$root),
(match (G_SUB $sub, 0, $A),
(G_SMIN $max, $A, $sub),
>From 281d0ecb134cbae10e87ec0ddd24dca857f3fabd Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:15 +0100
Subject: [PATCH 05/13] Update llvm/include/llvm/Target/GlobalISel/Combine.td
Co-authored-by: Jay Foad <jay.foad at gmail.com>
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 7b967a5328687..6e0d390bb22b1 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2456,8 +2456,8 @@ def NegSminNeg: GICombineRule<
(apply (G_SUB $sub1, 0, $A),
(G_SMAX $root, $A, $sub1))>;
-// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
-def SubUminSub: GICombineRule<
+// (sub 0, (umin X, (sub 0, X))) --> (umax X, (sub 0, X))
+def NegUminNeg: GICombineRule<
(defs root:$root),
(match (G_SUB $sub, 0, $A),
(G_UMIN $max, $A, $sub),
>From 705b4707d18b72600c75815f686fb9b04ca0907b Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:43 +0100
Subject: [PATCH 06/13] Apply suggestion from @luisacicolini
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 6e0d390bb22b1..fca1792def8c6 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2492,8 +2492,8 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
SubUmaxSub,
- SubSminSub,
- SubUminSub
+ NegSminNeg,
+ NegUminNeg
]>;
// fold (A+(shl (0-B), C)) -> (A-(shl B, C))
>From 922e606564bab4fdd1617a6068e2ccd004a96803 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:03 +0100
Subject: [PATCH 07/13] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 717144518b97a..0a830fedf7db8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -157,7 +157,6 @@ body: |
$x0 = COPY %mul
RET_ReallyLR implicit $x0
-
...
---
name: ASubSMin
>From 330e26be342824d8277779a8f11ccfaafb2027b3 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:12 +0100
Subject: [PATCH 08/13] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 0a830fedf7db8..d2aec897a60c1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -215,7 +215,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubSMinOneUse
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
>From e0f52367d7088ece80fe5271b3b7ce92c9fc46ab Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:21 +0100
Subject: [PATCH 09/13] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index d2aec897a60c1..7a4fd9dc8c41e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -242,7 +242,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubUMin
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
>From 4adec103b62841e3c02f22420cad27f4fba95e93 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:30 +0100
Subject: [PATCH 10/13] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 7a4fd9dc8c41e..592e966133585 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -292,7 +292,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubUMinOneUse
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
>From 47250537732b9a925387a4658d842b71a23e9285 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Wed, 30 Sep 2026 11:57:59 +0100
Subject: [PATCH 11/13] add dots
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 592e966133585..967a61de9797a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -311,3 +311,4 @@ body: |
%mul:_(s64) = G_MUL %max, %sub2
$x0 = COPY %mul
RET_ReallyLR implicit $x0
+...
\ No newline at end of file
>From c8f0965a636270c01d6c82c176afbdf96666f251 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Wed, 30 Sep 2026 12:04:42 +0100
Subject: [PATCH 12/13] tmp
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 967a61de9797a..96a789a6aa4e4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
@@ -311,4 +312,4 @@ body: |
%mul:_(s64) = G_MUL %max, %sub2
$x0 = COPY %mul
RET_ReallyLR implicit $x0
-...
\ No newline at end of file
+...
>From e2ef6bb2a99d5df082f73ca5840e625b0e07fe69 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Wed, 30 Sep 2026 12:25:23 +0100
Subject: [PATCH 13/13] fix
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
index 43380fe76316f..ee2852bdba49c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 7
; RUN: llc -global-isel=0 -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -global-isel -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 96a789a6aa4e4..69b63de0ab410 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -1,5 +1,4 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 7
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
---
More information about the llvm-commits
mailing list