[llvm] AMDGPU/GlobalISel: Mark SCC clobbers on control flow pseudos dead (PR #227636)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 03:58:00 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/227636
>From 1ddb374d1c0eb9ec3094a9f04db446e12f37548d Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 29 Sep 2026 04:06:41 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Mark SCC clobbers on control flow pseudos
dead
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 10 ++--
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 11 +++-
.../AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll | 24 ++++----
...vergence-divergent-i1-used-outside-loop.ll | 26 ++++-----
.../GlobalISel/divergence-structurizer.ll | 24 ++++----
.../global-atomic-fadd.f32-no-rtn.ll | 32 +++++-----
.../GlobalISel/global-atomic-fadd.f32-rtn.ll | 24 ++++----
.../GlobalISel/global-atomic-fadd.f64.ll | 12 ++--
.../AMDGPU/GlobalISel/legalize-brcond.mir | 58 ++++++++++++-------
.../GlobalISel/llvm.amdgcn.wqm.demote.ll | 44 +++++++-------
.../codegen-prepare-addrspacecast-non-null.ll | 14 ++---
.../AMDGPU/isel-whole-wave-functions.ll | 4 +-
12 files changed, 152 insertions(+), 131 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index f06837ff13869..831f3e3e44816 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1245,9 +1245,10 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
// FIXME: Manually selecting to avoid dealing with the SReg_1 trick
// SelectionDAG uses for wave32 vs wave64.
BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
- .add(I.getOperand(0))
- .add(I.getOperand(2))
- .add(I.getOperand(3));
+ .add(I.getOperand(0))
+ .add(I.getOperand(2))
+ .add(I.getOperand(3))
+ .setOperandDead(3); // implicit-def $scc
Register DstReg = I.getOperand(0).getReg();
Register Src0Reg = I.getOperand(2).getReg();
@@ -1818,7 +1819,8 @@ bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
// SelectionDAG uses for wave32 vs wave64.
MachineBasicBlock *BB = MI.getParent();
BuildMI(*BB, &MI, MI.getDebugLoc(), TII.get(AMDGPU::SI_END_CF))
- .add(MI.getOperand(1));
+ .add(MI.getOperand(1))
+ .setOperandDead(2); // implicit-def $scc
Register Reg = MI.getOperand(1).getReg();
MI.eraseFromParent();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e759f6eb64860..4ef314ffdae4c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -8386,12 +8386,14 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
B.buildInstr(AMDGPU::SI_IF)
.addDef(NewDef)
.addUse(NewUse)
- .addMBB(UncondBrTarget);
+ .addMBB(UncondBrTarget)
+ .setOperandDead(4); // implicit-def $scc
} else {
B.buildInstr(AMDGPU::SI_ELSE)
.addDef(NewDef)
.addUse(NewUse)
- .addMBB(UncondBrTarget);
+ .addMBB(UncondBrTarget)
+ .setOperandDead(4); // implicit-def $scc
}
if (Br) {
@@ -8434,7 +8436,10 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
B.setInsertPt(B.getMBB(), BrCond->getIterator());
B.buildCopy(NewReg, Reg);
- B.buildInstr(AMDGPU::SI_LOOP).addUse(NewReg).addMBB(UncondBrTarget);
+ B.buildInstr(AMDGPU::SI_LOOP)
+ .addUse(NewReg)
+ .addMBB(UncondBrTarget)
+ .setOperandDead(3); // implicit-def $scc
if (Br)
Br->getOperand(0).setMBB(CondBrTarget);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
index f3fbf2f2f344f..5831542bead6b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
@@ -121,13 +121,13 @@ define void @atomicrmw_fmax_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.3
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.3.atomicrmw.private:
@@ -158,7 +158,7 @@ define void @atomicrmw_fmax_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: S_BRANCH %bb.2
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.5.atomicrmw.phi:
- ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: SI_RETURN
%old = atomicrmw fmax ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
ret void
@@ -183,14 +183,14 @@ define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[PHI:%[0-9]+]]:vreg_64 = PHI %19, %bb.4, [[DEF]], %bb.1
- ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.3
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.3.atomicrmw.private:
@@ -224,7 +224,7 @@ define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: successors: %bb.6(0x80000000)
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[PHI1:%[0-9]+]]:vreg_64 = PHI [[PHI]], %bb.2, [[REG_SEQUENCE2]], %bb.3
- ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.6.atomicrmw.end:
; GFX10-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
@@ -417,13 +417,13 @@ define void @atomicrmw_fmin_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.3
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.3.atomicrmw.private:
@@ -454,7 +454,7 @@ define void @atomicrmw_fmin_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: S_BRANCH %bb.2
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.5.atomicrmw.phi:
- ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: SI_RETURN
%old = atomicrmw fmin ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
ret void
@@ -479,14 +479,14 @@ define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[PHI:%[0-9]+]]:vreg_64 = PHI %19, %bb.4, [[DEF]], %bb.1
- ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.3
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.3.atomicrmw.private:
@@ -520,7 +520,7 @@ define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: successors: %bb.6(0x80000000)
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[PHI1:%[0-9]+]]:vreg_64 = PHI [[PHI]], %bb.2, [[REG_SEQUENCE2]], %bb.3
- ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.6.atomicrmw.end:
; GFX10-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
index 01e0ad2d6ea42..f18efef146c7b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
@@ -343,24 +343,24 @@ define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0
-; GFX10-NEXT: s_mov_b32 s7, 0
-; GFX10-NEXT: ; implicit-def: $sgpr6
+; GFX10-NEXT: s_mov_b32 s6, 0
+; GFX10-NEXT: ; implicit-def: $sgpr5
; GFX10-NEXT: s_branch .LBB5_2
; GFX10-NEXT: .LBB5_1: ; %Flow
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX10-NEXT: s_and_b32 s5, exec_lo, s5
-; GFX10-NEXT: s_or_b32 s7, s5, s7
-; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s7
+; GFX10-NEXT: s_or_b32 s6, s5, s6
+; GFX10-NEXT: s_or_b32 s5, s7, s8
+; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT: s_cbranch_execz .LBB5_6
; GFX10-NEXT: .LBB5_2: ; %cond.block.0
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s4, v0
; GFX10-NEXT: v_mov_b32_e32 v4, s4
-; GFX10-NEXT: s_andn2_b32 s5, s6, exec_lo
-; GFX10-NEXT: s_and_b32 s6, exec_lo, vcc_lo
-; GFX10-NEXT: s_or_b32 s6, s5, s6
-; GFX10-NEXT: s_and_saveexec_b32 s8, vcc_lo
+; GFX10-NEXT: s_andn2_b32 s7, s5, exec_lo
+; GFX10-NEXT: s_and_b32 s8, exec_lo, vcc_lo
+; GFX10-NEXT: s_and_saveexec_b32 s9, vcc_lo
; GFX10-NEXT: s_cbranch_execz .LBB5_4
; GFX10-NEXT: ; %bb.3: ; %if.block.0
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
@@ -375,10 +375,10 @@ define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace
; GFX10-NEXT: .LBB5_4: ; %loop.break.block
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s4, v1
; GFX10-NEXT: s_mov_b32 s5, exec_lo
-; GFX10-NEXT: s_and_saveexec_b32 s8, vcc_lo
+; GFX10-NEXT: s_and_saveexec_b32 s9, vcc_lo
; GFX10-NEXT: s_cbranch_execz .LBB5_1
; GFX10-NEXT: ; %bb.5: ; %loop.cond
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
@@ -386,8 +386,8 @@ define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace
; GFX10-NEXT: s_andn2_b32 s5, s5, exec_lo
; GFX10-NEXT: s_branch .LBB5_1
; GFX10-NEXT: .LBB5_6: ; %cond.block.1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s7
-; GFX10-NEXT: s_and_saveexec_b32 s4, s6
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX10-NEXT: s_and_saveexec_b32 s4, s5
; GFX10-NEXT: s_cbranch_execz .LBB5_8
; GFX10-NEXT: ; %bb.7: ; %if.block.1
; GFX10-NEXT: global_store_dword v[6:7], v4, off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
index f56b06ca2376d..623e3a0e5369c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
@@ -485,17 +485,18 @@ define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2,
; GFX10-NEXT: s_mov_b32 s0, exec_lo
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: s_and_b32 s2, s0, 1
+; GFX10-NEXT: ; implicit-def: $sgpr3
; GFX10-NEXT: s_xor_b32 s0, vcc_lo, s0
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: ; implicit-def: $sgpr2
-; GFX10-NEXT: s_cselect_b32 s3, exec_lo, 0
+; GFX10-NEXT: s_cselect_b32 s2, exec_lo, 0
; GFX10-NEXT: s_branch .LBB6_2
; GFX10-NEXT: .LBB6_1: ; %Flow2
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s7
; GFX10-NEXT: s_and_b32 s4, exec_lo, s4
; GFX10-NEXT: s_mov_b32 s0, exec_lo
; GFX10-NEXT: s_or_b32 s1, s4, s1
+; GFX10-NEXT: s_or_b32 s3, s3, s6
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_cbranch_execz .LBB6_8
; GFX10-NEXT: .LBB6_2: ; %irr.guard
@@ -510,22 +511,21 @@ define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2,
; GFX10-NEXT: s_mov_b32 s6, exec_lo
; GFX10-NEXT: s_mov_b32 s7, exec_lo
; GFX10-NEXT: s_xor_b32 s6, vcc_lo, s6
-; GFX10-NEXT: s_andn2_b32 s3, s3, exec_lo
+; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo
; GFX10-NEXT: s_or_b32 s6, s0, s6
; GFX10-NEXT: s_and_b32 s0, exec_lo, s0
; GFX10-NEXT: s_xor_b32 s6, s6, s7
; GFX10-NEXT: s_andn2_b32 s5, s5, exec_lo
; GFX10-NEXT: s_and_b32 s6, exec_lo, s6
-; GFX10-NEXT: s_or_b32 s3, s3, s0
+; GFX10-NEXT: s_or_b32 s2, s2, s0
; GFX10-NEXT: s_or_b32 s5, s5, s6
; GFX10-NEXT: ; %bb.4: ; %Flow1
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: s_andn2_b32 s0, s2, exec_lo
-; GFX10-NEXT: s_and_b32 s2, exec_lo, s3
; GFX10-NEXT: s_mov_b32 s4, exec_lo
-; GFX10-NEXT: s_or_b32 s2, s0, s2
-; GFX10-NEXT: s_and_saveexec_b32 s6, s5
+; GFX10-NEXT: s_andn2_b32 s3, s3, exec_lo
+; GFX10-NEXT: s_and_b32 s6, exec_lo, s2
+; GFX10-NEXT: s_and_saveexec_b32 s7, s5
; GFX10-NEXT: s_cbranch_execz .LBB6_1
; GFX10-NEXT: ; %bb.5: ; %.preheader
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
@@ -534,8 +534,8 @@ define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2,
; GFX10-NEXT: .LBB6_6: ; %.inner_loop
; GFX10-NEXT: ; Parent Loop BB6_2 Depth=1
; GFX10-NEXT: ; => This Inner Loop Header: Depth=2
-; GFX10-NEXT: s_and_b32 s7, exec_lo, s0
-; GFX10-NEXT: s_or_b32 s5, s7, s5
+; GFX10-NEXT: s_and_b32 s8, exec_lo, s0
+; GFX10-NEXT: s_or_b32 s5, s8, s5
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB6_6
; GFX10-NEXT: ; %bb.7: ; %Flow
@@ -545,7 +545,7 @@ define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2,
; GFX10-NEXT: s_branch .LBB6_1
; GFX10-NEXT: .LBB6_8: ; %.exit
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v3, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v3, s3
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
index cb6076191cbc9..0e6e02ae61104 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
@@ -64,7 +64,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GFX908-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64_xexec = SI_PS_LIVE
- ; GFX908-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX908-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: S_BRANCH %bb.2
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.2 (%ir-block.5):
@@ -85,7 +85,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX908-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
; GFX908-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX908-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX908-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: S_BRANCH %bb.3
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.3 (%ir-block.17):
@@ -97,10 +97,10 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: bb.4.Flow:
; GFX908-NEXT: successors: %bb.5(0x80000000)
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX908-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.5 (%ir-block.19):
- ; GFX908-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX908-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: global_atomic_fadd_f32_saddr_no_rtn_atomicrmw
@@ -113,7 +113,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64_xexec = SI_PS_LIVE
- ; GFX90A-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.2
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2 (%ir-block.5):
@@ -134,7 +134,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
; GFX90A-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3 (%ir-block.17):
@@ -146,10 +146,10 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A-NEXT: bb.4.Flow:
; GFX90A-NEXT: successors: %bb.5(0x80000000)
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.5 (%ir-block.19):
- ; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0
;
; GFX942-LABEL: name: global_atomic_fadd_f32_saddr_no_rtn_atomicrmw
@@ -162,7 +162,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64_xexec = SI_PS_LIVE
- ; GFX942-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.2
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.2 (%ir-block.5):
@@ -183,7 +183,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
; GFX942-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.3 (%ir-block.17):
@@ -195,10 +195,10 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX942-NEXT: bb.4.Flow:
; GFX942-NEXT: successors: %bb.5(0x80000000)
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.5 (%ir-block.19):
- ; GFX942-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_ENDPGM 0
;
; GFX11-LABEL: name: global_atomic_fadd_f32_saddr_no_rtn_atomicrmw
@@ -211,7 +211,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_32_xm0_xexec = SI_PS_LIVE
- ; GFX11-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[SI_PS_LIVE]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.2
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2 (%ir-block.5):
@@ -227,7 +227,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY7]], implicit $exec
; GFX11-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.3
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.3 (%ir-block.13):
@@ -239,10 +239,10 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11-NEXT: bb.4.Flow:
; GFX11-NEXT: successors: %bb.5(0x80000000)
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.5 (%ir-block.15):
- ; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
%ret = atomicrmw fadd ptr addrspace(1) %ptr, float %data syncscope("wavefront") monotonic, !amdgpu.no.fine.grained.memory !0, !atomic.ignore.denormal.mode !0
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
index 2b216e27a56d3..b4bed8f448a4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
@@ -56,7 +56,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX90A-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64_xexec = SI_PS_LIVE
- ; GFX90A-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.2
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2 (%ir-block.5):
@@ -101,7 +101,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: early-clobber %34:sreg_32 = STRICT_WWM [[V_READLANE_B32_]], implicit $exec
; GFX90A-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY18]], implicit $exec
- ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3 (%ir-block.32):
@@ -116,14 +116,14 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: successors: %bb.6(0x80000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %43, %bb.5, [[DEF]], %bb.1
- ; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.6
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.5 (%ir-block.35):
; GFX90A-NEXT: successors: %bb.4(0x80000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.3, [[DEF]], %bb.2
- ; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
; GFX90A-NEXT: early-clobber %41:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
; GFX90A-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
@@ -147,7 +147,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX942-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64_xexec = SI_PS_LIVE
- ; GFX942-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.2
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.2 (%ir-block.5):
@@ -192,7 +192,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: early-clobber %33:sreg_32 = STRICT_WWM [[V_READLANE_B32_]], implicit $exec
; GFX942-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY18]], implicit $exec
- ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.3 (%ir-block.32):
@@ -207,14 +207,14 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: successors: %bb.6(0x80000000)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %42, %bb.5, [[DEF]], %bb.1
- ; GFX942-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.6
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.5 (%ir-block.35):
; GFX942-NEXT: successors: %bb.4(0x80000000)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.3, [[DEF]], %bb.2
- ; GFX942-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
; GFX942-NEXT: early-clobber %40:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
; GFX942-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
@@ -238,7 +238,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX11-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_32_xm0_xexec = SI_PS_LIVE
- ; GFX11-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[SI_PS_LIVE]], %bb.4, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.2
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2 (%ir-block.5):
@@ -282,7 +282,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: early-clobber %33:sreg_32 = STRICT_WWM [[V_READLANE_B32_1]], implicit $exec
; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY14]], implicit $exec
- ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.3
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.3 (%ir-block.29):
@@ -297,14 +297,14 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: successors: %bb.6(0x80000000)
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %42, %bb.5, [[DEF]], %bb.1
- ; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.6
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.5 (%ir-block.32):
; GFX11-NEXT: successors: %bb.4(0x80000000)
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.3, [[DEF]], %bb.2
- ; GFX11-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
; GFX11-NEXT: early-clobber %40:vgpr_32 = STRICT_WWM [[V_WRITELANE_B32_]], implicit $exec
; GFX11-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
index 3519e0c3760b2..9e2d1072857a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
@@ -26,12 +26,12 @@ define amdgpu_ps void @global_atomic_fadd_f64_no_rtn_atomicrmw(ptr addrspace(1)
; GFX90A-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[V_ADD_F64_e64_]], %subreg.sub0_sub1, [[PHI1]], %subreg.sub2_sub3
; GFX90A-NEXT: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64_align2 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic monotonic (i64) on %ir.ptr, addrspace 1)
; GFX90A-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]], [[PHI1]], implicit $exec
- ; GFX90A-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64_xexec = SI_IF_BREAK [[V_CMP_EQ_U64_e64_]], [[PHI]], implicit-def $scc
- ; GFX90A-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64_xexec = SI_IF_BREAK [[V_CMP_EQ_U64_e64_]], [[PHI]], implicit-def dead $scc
+ ; GFX90A-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.atomicrmw.end:
- ; GFX90A-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0
;
; GFX942-LABEL: name: global_atomic_fadd_f64_no_rtn_atomicrmw
@@ -74,12 +74,12 @@ define amdgpu_ps double @global_atomic_fadd_f64_rtn_atomicrmw(ptr addrspace(1) %
; GFX90A-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[V_ADD_F64_e64_]], %subreg.sub0_sub1, [[PHI1]], %subreg.sub2_sub3
; GFX90A-NEXT: [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN:%[0-9]+]]:vreg_64_align2 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic monotonic (i64) on %ir.ptr, addrspace 1)
; GFX90A-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]], [[PHI1]], implicit $exec
- ; GFX90A-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64_xexec = SI_IF_BREAK [[V_CMP_EQ_U64_e64_]], [[PHI]], implicit-def $scc
- ; GFX90A-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64_xexec = SI_IF_BREAK [[V_CMP_EQ_U64_e64_]], [[PHI]], implicit-def dead $scc
+ ; GFX90A-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.atomicrmw.end:
- ; GFX90A-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]].sub0
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_CMPSWAP_X2_RTN]].sub1
; GFX90A-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
index b62d62a0ac24e..3462748a475b8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
@@ -17,6 +17,7 @@ body: |
; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
+ ;
; WAVE32-LABEL: name: legal_brcond_vcc
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -55,6 +56,7 @@ body: |
; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
+ ;
; WAVE32-LABEL: name: legal_brcond_sgpr_s1
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -94,6 +96,7 @@ body: |
; WAVE64-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
+ ;
; WAVE32-LABEL: name: legal_brcond_sgpr_s32
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -129,10 +132,11 @@ body: |
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
+ ;
; WAVE32-LABEL: name: brcond_si_if
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -142,7 +146,7 @@ body: |
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
@@ -170,10 +174,11 @@ body: |
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE64-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
+ ;
; WAVE32-LABEL: name: brcond_si_else
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -183,7 +188,7 @@ body: |
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE32-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[COPY2]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
@@ -217,11 +222,12 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
+ ;
; WAVE32-LABEL: name: brcond_si_loop_brcond
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -236,7 +242,7 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
@@ -278,11 +284,12 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
+ ;
; WAVE32-LABEL: name: brcond_si_loop_brcond_back
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -297,7 +304,7 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
@@ -339,10 +346,11 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
+ ;
; WAVE32-LABEL: name: brcond_si_loop_brcond_back_fallthrough
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -357,7 +365,7 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
@@ -391,11 +399,12 @@ body: |
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY3]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY3]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](s32)
+ ;
; WAVE32-LABEL: name: brcond_si_if_need_insert_terminator_point
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -406,7 +415,7 @@ body: |
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY3]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY3]](s1), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
@@ -445,11 +454,12 @@ body: |
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
+ ;
; WAVE32-LABEL: name: brcond_si_loop_need_terminator_insert_point
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -466,7 +476,7 @@ body: |
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
@@ -502,7 +512,7 @@ body: |
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
@@ -512,6 +522,7 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 1
+ ;
; WAVE32-LABEL: name: brcond_si_if_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -521,7 +532,7 @@ body: |
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
@@ -561,7 +572,7 @@ body: |
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.3
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
@@ -576,6 +587,7 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.3:
; WAVE64-NEXT: S_NOP 2
+ ;
; WAVE32-LABEL: name: brcond_si_if_br_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -585,7 +597,7 @@ body: |
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
- ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[COPY2]](s1), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.3
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
@@ -640,11 +652,12 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
+ ;
; WAVE32-LABEL: name: brcond_si_loop_brcond_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -659,7 +672,7 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
@@ -700,11 +713,12 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE64-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
+ ;
; WAVE32-LABEL: name: brcond_si_loop_brcond_br_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
@@ -719,7 +733,7 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY [[COPY2]](s64)
- ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; WAVE32-NEXT: SI_LOOP [[COPY3]](s64), %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
index 02b68822047c3..7b817e1c91eaa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
@@ -667,12 +667,10 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) {
; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: s_movk_i32 s2, 0x3c00
-; SI-NEXT: s_bfe_u32 s3, 0, 0x100000
-; SI-NEXT: s_bfe_u32 s2, s2, 0x100000
-; SI-NEXT: s_lshl_b32 s4, s3, 16
-; SI-NEXT: s_or_b32 s4, s2, s4
-; SI-NEXT: s_lshl_b32 s2, s2, 16
-; SI-NEXT: s_or_b32 s5, s3, s2
+; SI-NEXT: s_bfe_u32 s4, s2, 0x100000
+; SI-NEXT: s_bfe_u32 s5, 0, 0x100000
+; SI-NEXT: s_lshl_b32 s6, s5, 16
+; SI-NEXT: s_lshl_b32 s7, s4, 16
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
@@ -681,10 +679,12 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) {
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 .LBB6_7
; SI-NEXT: ; %bb.2: ; %.demote0
-; SI-NEXT: s_wqm_b64 s[6:7], s[0:1]
-; SI-NEXT: s_and_b64 exec, exec, s[6:7]
+; SI-NEXT: s_wqm_b64 s[8:9], s[0:1]
+; SI-NEXT: s_and_b64 exec, exec, s[8:9]
; SI-NEXT: .LBB6_3: ; %.continue0
; SI-NEXT: s_or_b64 exec, exec, s[2:3]
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_or_b32 s5, s5, s7
; SI-NEXT: s_mov_b64 s[6:7], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, v0
@@ -901,13 +901,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: s_movk_i32 s2, 0x3c00
-; SI-NEXT: s_bfe_u32 s3, 0, 0x100000
-; SI-NEXT: s_bfe_u32 s2, s2, 0x100000
-; SI-NEXT: s_lshl_b32 s4, s3, 16
-; SI-NEXT: s_or_b32 s6, s2, s4
-; SI-NEXT: s_lshl_b32 s2, s2, 16
-; SI-NEXT: s_or_b32 s7, s3, s2
-; SI-NEXT: s_mov_b32 s8, 0
+; SI-NEXT: s_bfe_u32 s4, s2, 0x100000
+; SI-NEXT: s_bfe_u32 s5, 0, 0x100000
+; SI-NEXT: s_lshl_b32 s7, s5, 16
+; SI-NEXT: s_lshl_b32 s8, s4, 16
+; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
@@ -916,23 +914,25 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 .LBB7_9
; SI-NEXT: ; %bb.2: ; %.demote0
-; SI-NEXT: s_wqm_b64 s[4:5], s[0:1]
-; SI-NEXT: s_and_b64 exec, exec, s[4:5]
+; SI-NEXT: s_wqm_b64 s[10:11], s[0:1]
+; SI-NEXT: s_and_b64 exec, exec, s[10:11]
; SI-NEXT: .LBB7_3: ; %.continue0.preheader
; SI-NEXT: s_or_b64 exec, exec, s[2:3]
+; SI-NEXT: s_or_b32 s7, s4, s7
+; SI-NEXT: s_or_b32 s8, s5, s8
; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: s_branch .LBB7_5
; SI-NEXT: .LBB7_4: ; %.continue1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_add_i32 s8, s8, 1
-; SI-NEXT: v_cmp_ge_i32_e32 vcc, s8, v1
+; SI-NEXT: s_add_i32 s6, s6, 1
+; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execz .LBB7_8
; SI-NEXT: .LBB7_5: ; %.continue0
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: s_mov_b64 s[10:11], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
; SI-NEXT: v_mov_b32_e32 v2, v0
@@ -960,8 +960,8 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index
; SI-NEXT: .LBB7_8: ; %.return
; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_and_b64 exec, exec, s[0:1]
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_mov_b32_e32 v0, s7
+; SI-NEXT: v_mov_b32_e32 v1, s8
; SI-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm
; SI-NEXT: s_endpgm
; SI-NEXT: .LBB7_9:
diff --git a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
index dbed069faef1a..3f8aa97b637bd 100644
--- a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+++ b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
@@ -351,10 +351,9 @@ define void @recursive_phis(i1 %cond, ptr addrspace(5) %ptr) {
; GISEL-ASM: ; %bb.0: ; %entry
; GISEL-ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-ASM-NEXT: v_and_b32_e32 v0, 1, v0
+; GISEL-ASM-NEXT: s_lshr_b32 s6, s32, 6
; GISEL-ASM-NEXT: s_mov_b64 s[4:5], exec
; GISEL-ASM-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-ASM-NEXT: s_lshr_b32 s6, s32, 6
-; GISEL-ASM-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-ASM-NEXT: v_mov_b32_e32 v0, s6
; GISEL-ASM-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GISEL-ASM-NEXT: ; %bb.1: ; %then
@@ -362,19 +361,20 @@ define void @recursive_phis(i1 %cond, ptr addrspace(5) %ptr) {
; GISEL-ASM-NEXT: ; %bb.2: ; %finallyendcf.split
; GISEL-ASM-NEXT: s_or_b64 exec, exec, s[6:7]
; GISEL-ASM-NEXT: s_mov_b64 s[8:9], src_private_base
-; GISEL-ASM-NEXT: s_mov_b64 s[6:7], 0
+; GISEL-ASM-NEXT: s_xor_b64 s[6:7], vcc, s[4:5]
+; GISEL-ASM-NEXT: s_mov_b64 s[4:5], 0
; GISEL-ASM-NEXT: v_mov_b32_e32 v1, s9
; GISEL-ASM-NEXT: v_mov_b32_e32 v2, 7
; GISEL-ASM-NEXT: .LBB11_3: ; %finally
; GISEL-ASM-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-ASM-NEXT: s_and_b64 s[8:9], exec, s[4:5]
-; GISEL-ASM-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
+; GISEL-ASM-NEXT: s_and_b64 s[8:9], exec, s[6:7]
+; GISEL-ASM-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
; GISEL-ASM-NEXT: flat_store_dword v[0:1], v2
; GISEL-ASM-NEXT: s_waitcnt vmcnt(0)
-; GISEL-ASM-NEXT: s_andn2_b64 exec, exec, s[6:7]
+; GISEL-ASM-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GISEL-ASM-NEXT: s_cbranch_execnz .LBB11_3
; GISEL-ASM-NEXT: ; %bb.4: ; %end
-; GISEL-ASM-NEXT: s_or_b64 exec, exec, s[6:7]
+; GISEL-ASM-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-ASM-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-ASM-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
index c90457d2b7fa0..d1a50bd3f76c6 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
@@ -100,7 +100,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: [[SI_WHOLE_WAVE_FUNC_SETUP:%[0-9]+]]:sreg_32_xm0_xexec = SI_WHOLE_WAVE_FUNC_SETUP implicit-def dead $exec, implicit $exec
; GISEL-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GISEL-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY2]], %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GISEL-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY2]], %bb.3, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GISEL-NEXT: S_BRANCH %bb.2
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: bb.2.if.then:
@@ -110,7 +110,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: bb.3.if.end:
; GISEL-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY1]], %bb.1, [[V_ADD_U32_e64_]], %bb.2
- ; GISEL-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GISEL-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def dead $scc, implicit $exec
; GISEL-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[PHI]], 0, [[COPY]], [[SI_WHOLE_WAVE_FUNC_SETUP]], implicit $exec
; GISEL-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
; GISEL-NEXT: SI_WHOLE_WAVE_FUNC_RETURN [[SI_WHOLE_WAVE_FUNC_SETUP]], implicit $vgpr0
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