[llvm] [mlir] [MLGO] Do not hardcode 33 eviction feature columns (PR #224598)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 02:49:40 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/224598
>From 7123e766b77c8a2ee8d8452d6d311a82dea525a3 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Fri, 18 Sep 2026 12:52:02 +0200
Subject: [PATCH 1/5] [MLGO] Do not hardcode 33 eviction feature columns
The number came from X86 and cuts off wider targets like AMDGPU
---
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 79 ++++++++++++++-------
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h | 17 ++---
2 files changed, 58 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index 0ed413a7707ad..cb24f82d6ceaa 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -176,10 +176,6 @@ INITIALIZE_PASS(RegAllocScoring, "regallocscoringpass",
// Common ML Advisor declarations
// ===================================
namespace {
-// Most features are as described above, so we'll reuse this vector in defining
-// them.
-static const std::vector<int64_t> PerLiveRangeShape{1, NumberOfInterferences};
-
// --------------
// Features table
// --------------
@@ -272,7 +268,8 @@ template <typename T> size_t getTotalSize(const std::vector<int64_t> &Shape) {
return Ret;
}
-void resetInputs(MLModelRunner &Runner) {
+void resetInputs(MLModelRunner &Runner,
+ const std::vector<int64_t> &PerLiveRangeShape) {
#define _RESET(TYPE, NAME, SHAPE, __) \
std::memset(Runner.getTensorUntyped(FeatureIDs::NAME), 0, \
getTotalSize<TYPE>(SHAPE));
@@ -294,7 +291,7 @@ struct LIFeatureComponents {
};
using CandidateRegList =
- std::array<std::pair<MCRegister, bool>, NumberOfInterferences>;
+ SmallVector<std::pair<MCRegister, bool>, CompiledModelNumColumns>;
using FeaturesListNormalizer =
llvm::SmallVector<float, FeatureIDs::FeatureCount>;
@@ -302,7 +299,8 @@ using FeaturesListNormalizer =
class MLEvictAdvisor : public RegAllocEvictionAdvisor {
public:
MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
- MLModelRunner *Runner, const MachineBlockFrequencyInfo &MBFI,
+ MLModelRunner *Runner, int64_t NumberOfInterferences,
+ const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops);
protected:
@@ -310,6 +308,11 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
return static_cast<const RegAllocEvictionAdvisor &>(DefaultAdvisor);
}
+ const size_t NumberOfInterferences;
+ const size_t CandidateVirtRegPos = NumberOfInterferences - 1;
+ const std::vector<int64_t> PerLiveRangeShape{
+ 1, static_cast<int64_t>(NumberOfInterferences)};
+
// The assumption is that if the Runner could not be constructed, we emit-ed
// error, and we shouldn't be asking for it here.
const MLModelRunner &getRunner() const { return *Runner; }
@@ -394,6 +397,15 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
#define _DECL_FEATURES(type, name, shape, _) \
TensorSpec::createSpec<type>(#name, shape),
+static int64_t getRequiredNumColumns(const TargetRegisterInfo &TRI,
+ const RegisterClassInfo &RegClassInfo) {
+ unsigned MaxOrder = 0;
+ for (const TargetRegisterClass &RC : TRI.regclasses())
+ if (RC.isAllocatable())
+ MaxOrder = std::max(MaxOrder, RegClassInfo.getNumAllocatableRegs(&RC));
+ return MaxOrder + 1;
+}
+
// ===================================
// Release (AOT) - specifics
// ===================================
@@ -402,9 +414,7 @@ class ReleaseModeEvictionAdvisorProvider final
: public RegAllocEvictionAdvisorProvider {
public:
ReleaseModeEvictionAdvisorProvider(LLVMContext &Ctx)
- : RegAllocEvictionAdvisorProvider(AdvisorMode::Release, Ctx) {
- InputFeatures = {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
- }
+ : RegAllocEvictionAdvisorProvider(AdvisorMode::Release, Ctx) {}
// support for isa<> and dyn_cast.
static bool classof(const RegAllocEvictionAdvisorProvider *R) {
return R->getAdvisorMode() == AdvisorMode::Release;
@@ -414,6 +424,16 @@ class ReleaseModeEvictionAdvisorProvider final
getAdvisor(const MachineFunction &MF, const RAGreedy &RA,
MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *Loops) override {
if (!Runner) {
+ NumColumns =
+ InteractiveChannelBaseName.empty()
+ ? CompiledModelNumColumns
+ : std::max<int64_t>(
+ CompiledModelNumColumns,
+ getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo(),
+ RA.getRegClassInfo()));
+ const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
+ const std::vector<TensorSpec> InputFeatures{
+ RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
Runner = createReleaseModeModelRunner<CompiledModelType,
HaveMLIRLoweringRegAlloc>(
MF.getFunction().getContext(), InputFeatures, DecisionName,
@@ -422,13 +442,13 @@ class ReleaseModeEvictionAdvisorProvider final
}
assert(MBFI && Loops &&
"Invalid provider state: must have analysis available");
- return std::make_unique<MLEvictAdvisor>(MF, RA, Runner.get(), *MBFI,
- *Loops);
+ return std::make_unique<MLEvictAdvisor>(MF, RA, Runner.get(), NumColumns,
+ *MBFI, *Loops);
}
private:
- std::vector<TensorSpec> InputFeatures;
std::unique_ptr<MLModelRunner> Runner;
+ int64_t NumColumns = CompiledModelNumColumns;
};
class ReleaseModeEvictionAdvisorAnalysisLegacy final
@@ -479,7 +499,8 @@ class DevelopmentModeEvictAdvisor : public MLEvictAdvisor {
MLModelRunner *Runner,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops, Logger *Log)
- : MLEvictAdvisor(MF, RA, Runner, MBFI, Loops), Log(Log) {}
+ : MLEvictAdvisor(MF, RA, Runner, CompiledModelNumColumns, MBFI, Loops),
+ Log(Log) {}
private:
int64_t tryFindEvictionCandidatePosition(
@@ -495,6 +516,7 @@ class DevelopmentModeEvictionAdvisorProvider final
public:
DevelopmentModeEvictionAdvisorProvider(LLVMContext &Ctx)
: RegAllocEvictionAdvisorProvider(AdvisorMode::Development, Ctx) {
+ const std::vector<int64_t> PerLiveRangeShape{1, CompiledModelNumColumns};
InputFeatures = {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
TrainingInputFeatures = {
RA_EVICT_FEATURES_LIST(_DECL_TRAIN_FEATURES)
@@ -622,9 +644,11 @@ float MLEvictAdvisor::getInitialQueueSize(const MachineFunction &MF) {
MLEvictAdvisor::MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
MLModelRunner *Runner,
+ int64_t NumberOfInterferences,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops)
- : RegAllocEvictionAdvisor(MF, RA), DefaultAdvisor(MF, RA),
+ : RegAllocEvictionAdvisor(MF, RA),
+ NumberOfInterferences(NumberOfInterferences), DefaultAdvisor(MF, RA),
Runner(std::move(Runner)), MBFI(MBFI), Loops(Loops),
InitialQSize(MLEvictAdvisor::getInitialQueueSize(MF)) {
assert(this->Runner);
@@ -643,7 +667,7 @@ int64_t MLEvictAdvisor::tryFindEvictionCandidatePosition(
const SmallVirtRegSet &) const {
int64_t Ret = Runner->evaluate<int64_t>();
assert(Ret >= 0);
- assert(Ret <= CandidateVirtRegPos);
+ assert(static_cast<size_t>(Ret) <= CandidateVirtRegPos);
return Ret;
}
@@ -665,7 +689,7 @@ bool MLEvictAdvisor::loadInterferenceFeatures(
// The cascade tracking is the same as in the default advisor
unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
- SmallVector<const LiveInterval *, MaxInterferences> InterferingIntervals;
+ SmallVector<const LiveInterval *, 32> InterferingIntervals;
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// Different from the default heuristic, we don't make any assumptions
@@ -744,13 +768,12 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
size_t Available = 0;
// Make sure we don't have leftover partial state from an attempt where we
// had no available candidates and bailed out early.
- resetInputs(*Runner);
+ resetInputs(*Runner, PerLiveRangeShape);
// Track the index->register mapping because AllocationOrder doesn't do that
// and we'd have to scan it.
// Also track their mask, to write asserts/debug.
- CandidateRegList Regs;
- Regs.fill({0, false});
+ CandidateRegList Regs(NumberOfInterferences);
// Track the largest value of features seen during this eviction session. We
// only normalize (some of) the float features, but it's just simpler to
@@ -764,9 +787,11 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
// reset all the features to 0) Use Pos to capture the column we load
// features at - in AllocationOrder order.
size_t Pos = 0;
- SmallVector<LRStartEndInfo, NumberOfInterferences> LRPosInfo;
- for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E;
- ++I, ++Pos) {
+ SmallVector<LRStartEndInfo, CompiledModelNumColumns> LRPosInfo;
+ // The order can outrun the tensor width (fixed-width precompiled model,
+ // duplicated hints), so drop the tail rather than write out of bounds.
+ for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit);
+ I != E && Pos < CandidateVirtRegPos; ++I, ++Pos) {
MCRegister PhysReg = *I;
assert(!Regs[Pos].second);
assert(PhysReg);
@@ -802,9 +827,10 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
++FeatureIndex) {
if (DoNotNormalize.test(FeatureIndex))
continue;
- for (size_t Pos = 0; Pos < NumberOfInterferences; ++Pos) {
- Runner->getTensor<float>(FeatureIndex)[Pos] /= Largest[FeatureIndex];
- }
+ float *Tensor = Runner->getTensor<float>(FeatureIndex);
+ for (size_t Pos = 0; Pos < ValidPosLimit; ++Pos)
+ Tensor[Pos] /= Largest[FeatureIndex];
+ Tensor[CandidateVirtRegPos] /= Largest[FeatureIndex];
}
*Runner->getTensor<float>(FeatureIDs::progress) =
static_cast<float>(RA.getQueueSize()) / InitialQSize;
@@ -821,7 +847,6 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
return MCRegister::NoRegister;
}
assert(CandidatePos < ValidPosLimit);
- (void)ValidPosLimit;
// Update information about how many times the virtual registers being
// evicted have been evicted so that we can prevent the model from evicting
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
index 6674d07dad0f6..5d7be4e67d88f 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
@@ -33,20 +33,15 @@ struct LRStartEndInfo {
size_t Pos = 0;
};
-// This is the maximum number of interfererring ranges. That's the number of
-// distinct AllocationOrder values, which comes from MCRegisterClass::RegsSize.
-// For X86, that's 32.
-// TODO: find a way to get this, statically, in a programmatic way.
-static const int64_t MaxInterferences = 32;
-
// Logically, we can think of the feature set given to the evaluator as a 2D
// matrix. The rows are the features (see next). The columns correspond to the
// interferences. We treat the candidate virt reg as an 'interference', too, as
// its feature set is the same as that of the interferring ranges. So we'll have
-// MaxInterferences + 1 columns and by convention, we will use the last column
-// for the virt reg seeking allocation.
-static const int64_t CandidateVirtRegPos = MaxInterferences;
-static const int64_t NumberOfInterferences = CandidateVirtRegPos + 1;
+// one column per allocation order slot, plus one, and by convention, we will
+// use the last column for the virt reg seeking allocation.
+// The advisor computes the column count per target. Changing this constant
+// requires regenerating the precompiled test models.
+static const int64_t CompiledModelNumColumns = 33;
// The number of instructions that a specific live range might have is variable,
// but we're passing in a single matrix of instructions and tensorflow saved
@@ -64,7 +59,7 @@ static const int ModelMaxSupportedInstructionCount = 300;
static const std::vector<int64_t> InstructionsShape{
1, ModelMaxSupportedInstructionCount};
static const std::vector<int64_t> InstructionsMappingShape{
- 1, NumberOfInterferences, ModelMaxSupportedInstructionCount};
+ 1, CompiledModelNumColumns, ModelMaxSupportedInstructionCount};
// When extracting mappings between MBBs and individual instructions, we create
// a vector of MBB frequencies, currently of size 100, which was a value
>From ccd4535ca9a8512264a90fc79a3c362d6755d2b3 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 21 Sep 2026 07:38:35 +0200
Subject: [PATCH 2/5] some fixes & improvements
---
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 43 +++++++++----------
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h | 5 ++-
.../CodeGen/MLRegAlloc/interactive-mode.ll | 4 +-
3 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index cb24f82d6ceaa..1362ce68b113a 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -38,7 +38,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
-#include <array>
#include <bitset>
#include <memory>
@@ -261,15 +260,14 @@ enum FeatureIDs {
// various phys regs won't be available. It's easier (maintenance-wise) to
// bulk-reset the state of the evaluator each time we are about to use it
// again.
-template <typename T> size_t getTotalSize(const std::vector<int64_t> &Shape) {
+template <typename T> size_t getTotalSize(ArrayRef<int64_t> Shape) {
size_t Ret = sizeof(T);
for (const auto V : Shape)
Ret *= V;
return Ret;
}
-void resetInputs(MLModelRunner &Runner,
- const std::vector<int64_t> &PerLiveRangeShape) {
+void resetInputs(MLModelRunner &Runner, ArrayRef<int64_t> PerLiveRangeShape) {
#define _RESET(TYPE, NAME, SHAPE, __) \
std::memset(Runner.getTensorUntyped(FeatureIDs::NAME), 0, \
getTotalSize<TYPE>(SHAPE));
@@ -290,6 +288,8 @@ struct LIFeatureComponents {
bool IsRemat = false;
};
+static constexpr unsigned ExpectedMaxInterferingIntervals = 32;
+
using CandidateRegList =
SmallVector<std::pair<MCRegister, bool>, CompiledModelNumColumns>;
using FeaturesListNormalizer =
@@ -299,7 +299,7 @@ using FeaturesListNormalizer =
class MLEvictAdvisor : public RegAllocEvictionAdvisor {
public:
MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
- MLModelRunner *Runner, int64_t NumberOfInterferences,
+ MLModelRunner *Runner, int64_t NumColumns,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops);
@@ -308,10 +308,10 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
return static_cast<const RegAllocEvictionAdvisor &>(DefaultAdvisor);
}
- const size_t NumberOfInterferences;
- const size_t CandidateVirtRegPos = NumberOfInterferences - 1;
- const std::vector<int64_t> PerLiveRangeShape{
- 1, static_cast<int64_t>(NumberOfInterferences)};
+ const size_t NumColumns;
+ const size_t CandidateVirtRegPos = NumColumns - 1;
+ const SmallVector<int64_t, 2> PerLiveRangeShape{
+ 1, static_cast<int64_t>(NumColumns)};
// The assumption is that if the Runner could not be constructed, we emit-ed
// error, and we shouldn't be asking for it here.
@@ -427,10 +427,8 @@ class ReleaseModeEvictionAdvisorProvider final
NumColumns =
InteractiveChannelBaseName.empty()
? CompiledModelNumColumns
- : std::max<int64_t>(
- CompiledModelNumColumns,
- getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo(),
- RA.getRegClassInfo()));
+ : getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo(),
+ RA.getRegClassInfo());
const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
const std::vector<TensorSpec> InputFeatures{
RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
@@ -643,14 +641,12 @@ float MLEvictAdvisor::getInitialQueueSize(const MachineFunction &MF) {
}
MLEvictAdvisor::MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
- MLModelRunner *Runner,
- int64_t NumberOfInterferences,
+ MLModelRunner *Runner, int64_t NumColumns,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops)
- : RegAllocEvictionAdvisor(MF, RA),
- NumberOfInterferences(NumberOfInterferences), DefaultAdvisor(MF, RA),
- Runner(std::move(Runner)), MBFI(MBFI), Loops(Loops),
- InitialQSize(MLEvictAdvisor::getInitialQueueSize(MF)) {
+ : RegAllocEvictionAdvisor(MF, RA), NumColumns(NumColumns),
+ DefaultAdvisor(MF, RA), Runner(std::move(Runner)), MBFI(MBFI),
+ Loops(Loops), InitialQSize(MLEvictAdvisor::getInitialQueueSize(MF)) {
assert(this->Runner);
Runner->switchContext(MF.getName());
DoNotNormalize.set(FeatureIDs::mask);
@@ -689,7 +685,8 @@ bool MLEvictAdvisor::loadInterferenceFeatures(
// The cascade tracking is the same as in the default advisor
unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
- SmallVector<const LiveInterval *, 32> InterferingIntervals;
+ SmallVector<const LiveInterval *, ExpectedMaxInterferingIntervals>
+ InterferingIntervals;
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// Different from the default heuristic, we don't make any assumptions
@@ -773,7 +770,7 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
// Track the index->register mapping because AllocationOrder doesn't do that
// and we'd have to scan it.
// Also track their mask, to write asserts/debug.
- CandidateRegList Regs(NumberOfInterferences);
+ CandidateRegList Regs(NumColumns);
// Track the largest value of features seen during this eviction session. We
// only normalize (some of) the float features, but it's just simpler to
@@ -828,9 +825,8 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
if (DoNotNormalize.test(FeatureIndex))
continue;
float *Tensor = Runner->getTensor<float>(FeatureIndex);
- for (size_t Pos = 0; Pos < ValidPosLimit; ++Pos)
+ for (size_t Pos = 0; Pos < NumColumns; ++Pos)
Tensor[Pos] /= Largest[FeatureIndex];
- Tensor[CandidateVirtRegPos] /= Largest[FeatureIndex];
}
*Runner->getTensor<float>(FeatureIDs::progress) =
static_cast<float>(RA.getQueueSize()) / InitialQSize;
@@ -847,6 +843,7 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
return MCRegister::NoRegister;
}
assert(CandidatePos < ValidPosLimit);
+ (void)ValidPosLimit;
// Update information about how many times the virtual registers being
// evicted have been evicted so that we can prevent the model from evicting
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
index 5d7be4e67d88f..5215f486efb44 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
@@ -39,8 +39,9 @@ struct LRStartEndInfo {
// its feature set is the same as that of the interferring ranges. So we'll have
// one column per allocation order slot, plus one, and by convention, we will
// use the last column for the virt reg seeking allocation.
-// The advisor computes the column count per target. Changing this constant
-// requires regenerating the precompiled test models.
+// The AOT and reference models bake this width in and do not expose it, so
+// changing it requires regenerating them. The interactive channel derives its
+// own width from the target instead.
static const int64_t CompiledModelNumColumns = 33;
// The number of instructions that a specific live range might have is variable,
diff --git a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
index 82088c80882c3..f6302bfb08a57 100644
--- a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
+++ b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
@@ -13,9 +13,9 @@
;; expected one - the index of the first legal register
; CHECK: context: SyFgets
; CHECK-NEXT: observation: 0
-; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
+; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,1
; CHECK: observation: 1
-; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
+; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,1
; CHECK: context: SyFgetsCopy
; CHECK-NEXT: observation: 0
>From 0f075ccc37a6fe2ad6117b13b1f724e3c605c227 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 22 Sep 2026 18:18:56 +0200
Subject: [PATCH 3/5] part 1
---
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 46 ++++++++-------------
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index 1362ce68b113a..63bf01c3282a4 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -260,19 +260,9 @@ enum FeatureIDs {
// various phys regs won't be available. It's easier (maintenance-wise) to
// bulk-reset the state of the evaluator each time we are about to use it
// again.
-template <typename T> size_t getTotalSize(ArrayRef<int64_t> Shape) {
- size_t Ret = sizeof(T);
- for (const auto V : Shape)
- Ret *= V;
- return Ret;
-}
-
-void resetInputs(MLModelRunner &Runner, ArrayRef<int64_t> PerLiveRangeShape) {
-#define _RESET(TYPE, NAME, SHAPE, __) \
- std::memset(Runner.getTensorUntyped(FeatureIDs::NAME), 0, \
- getTotalSize<TYPE>(SHAPE));
- RA_EVICT_FEATURES_LIST(_RESET)
-#undef _RESET
+void resetInputs(MLModelRunner &Runner, ArrayRef<TensorSpec> InputFeatures) {
+ for (auto [I, Spec] : enumerate(InputFeatures))
+ std::memset(Runner.getTensorUntyped(I), 0, Spec.getTotalTensorBufferSize());
}
// Per-live interval components that get aggregated into the feature values
@@ -288,8 +278,6 @@ struct LIFeatureComponents {
bool IsRemat = false;
};
-static constexpr unsigned ExpectedMaxInterferingIntervals = 32;
-
using CandidateRegList =
SmallVector<std::pair<MCRegister, bool>, CompiledModelNumColumns>;
using FeaturesListNormalizer =
@@ -299,7 +287,7 @@ using FeaturesListNormalizer =
class MLEvictAdvisor : public RegAllocEvictionAdvisor {
public:
MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
- MLModelRunner *Runner, int64_t NumColumns,
+ MLModelRunner *Runner, ArrayRef<TensorSpec> InputFeatures,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops);
@@ -308,10 +296,9 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
return static_cast<const RegAllocEvictionAdvisor &>(DefaultAdvisor);
}
+ const ArrayRef<TensorSpec> InputFeatures;
const size_t NumColumns;
const size_t CandidateVirtRegPos = NumColumns - 1;
- const SmallVector<int64_t, 2> PerLiveRangeShape{
- 1, static_cast<int64_t>(NumColumns)};
// The assumption is that if the Runner could not be constructed, we emit-ed
// error, and we shouldn't be asking for it here.
@@ -430,8 +417,7 @@ class ReleaseModeEvictionAdvisorProvider final
: getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo(),
RA.getRegClassInfo());
const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
- const std::vector<TensorSpec> InputFeatures{
- RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
+ InputFeatures = {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
Runner = createReleaseModeModelRunner<CompiledModelType,
HaveMLIRLoweringRegAlloc>(
MF.getFunction().getContext(), InputFeatures, DecisionName,
@@ -440,11 +426,12 @@ class ReleaseModeEvictionAdvisorProvider final
}
assert(MBFI && Loops &&
"Invalid provider state: must have analysis available");
- return std::make_unique<MLEvictAdvisor>(MF, RA, Runner.get(), NumColumns,
+ return std::make_unique<MLEvictAdvisor>(MF, RA, Runner.get(), InputFeatures,
*MBFI, *Loops);
}
private:
+ std::vector<TensorSpec> InputFeatures;
std::unique_ptr<MLModelRunner> Runner;
int64_t NumColumns = CompiledModelNumColumns;
};
@@ -495,10 +482,10 @@ class DevelopmentModeEvictAdvisor : public MLEvictAdvisor {
public:
DevelopmentModeEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
MLModelRunner *Runner,
+ ArrayRef<TensorSpec> InputFeatures,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops, Logger *Log)
- : MLEvictAdvisor(MF, RA, Runner, CompiledModelNumColumns, MBFI, Loops),
- Log(Log) {}
+ : MLEvictAdvisor(MF, RA, Runner, InputFeatures, MBFI, Loops), Log(Log) {}
private:
int64_t tryFindEvictionCandidatePosition(
@@ -587,7 +574,7 @@ class DevelopmentModeEvictionAdvisorProvider final
assert(MBFI && Loops &&
"Invalid provider state: must have analysis available");
return std::make_unique<DevelopmentModeEvictAdvisor>(
- MF, RA, Runner.get(), *MBFI, *Loops, Log.get());
+ MF, RA, Runner.get(), InputFeatures, *MBFI, *Loops, Log.get());
}
private:
@@ -641,10 +628,12 @@ float MLEvictAdvisor::getInitialQueueSize(const MachineFunction &MF) {
}
MLEvictAdvisor::MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
- MLModelRunner *Runner, int64_t NumColumns,
+ MLModelRunner *Runner,
+ ArrayRef<TensorSpec> InputFeatures,
const MachineBlockFrequencyInfo &MBFI,
const MachineLoopInfo &Loops)
- : RegAllocEvictionAdvisor(MF, RA), NumColumns(NumColumns),
+ : RegAllocEvictionAdvisor(MF, RA), InputFeatures(InputFeatures),
+ NumColumns(InputFeatures[FeatureIDs::mask].shape()[1]),
DefaultAdvisor(MF, RA), Runner(std::move(Runner)), MBFI(MBFI),
Loops(Loops), InitialQSize(MLEvictAdvisor::getInitialQueueSize(MF)) {
assert(this->Runner);
@@ -685,8 +674,7 @@ bool MLEvictAdvisor::loadInterferenceFeatures(
// The cascade tracking is the same as in the default advisor
unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
- SmallVector<const LiveInterval *, ExpectedMaxInterferingIntervals>
- InterferingIntervals;
+ SmallVector<const LiveInterval *, 32> InterferingIntervals;
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// Different from the default heuristic, we don't make any assumptions
@@ -765,7 +753,7 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
size_t Available = 0;
// Make sure we don't have leftover partial state from an attempt where we
// had no available candidates and bailed out early.
- resetInputs(*Runner, PerLiveRangeShape);
+ resetInputs(*Runner, InputFeatures);
// Track the index->register mapping because AllocationOrder doesn't do that
// and we'd have to scan it.
>From 21a86cbe6a32d54a3765c4b4075e243d51afac76 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 29 Sep 2026 12:29:58 +0200
Subject: [PATCH 4/5] Refuse a compiled model of the wrong size and use the
default advisor
---
.../llvm/Analysis/ReleaseModeModelRunner.h | 23 +-
llvm/include/llvm/Analysis/Utils/MLGOUtils.h | 7 +-
llvm/lib/Analysis/MLInlineAdvisor.cpp | 1 +
.../gen-regalloc-eviction-test-model.py | 3 +-
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 188 +++--
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h | 17 +-
.../MLRegAlloc/Inputs/reference-log-noml.txt | 744 +++++++++---------
.../CodeGen/MLRegAlloc/dev-mode-logging.ll | 4 +-
.../CodeGen/MLRegAlloc/interactive-mode.ll | 4 +-
llvm/unittests/Analysis/MLGOUtilsTest.cpp | 3 +
llvm/unittests/Analysis/MLModelRunnerTest.cpp | 36 +
.../regalloc-eviction-test-model-tosa.mlir | 6 +-
12 files changed, 565 insertions(+), 471 deletions(-)
diff --git a/llvm/include/llvm/Analysis/ReleaseModeModelRunner.h b/llvm/include/llvm/Analysis/ReleaseModeModelRunner.h
index ff423a9155b14..993c86378dab4 100644
--- a/llvm/include/llvm/Analysis/ReleaseModeModelRunner.h
+++ b/llvm/include/llvm/Analysis/ReleaseModeModelRunner.h
@@ -108,6 +108,10 @@ class ReleaseModeModelRunner final : public MLModelRunner {
~ReleaseModeModelRunner() override = default;
+ /// Whether every requested TensorSpec matched the shape the compiled model
+ /// was built for. If false, the caller is expected to fall back.
+ bool isValid() const { return Valid; }
+
static bool classof(const MLModelRunner *R) {
return R->getKind() == MLModelRunner::Kind::Release;
}
@@ -122,8 +126,21 @@ class ReleaseModeModelRunner final : public MLModelRunner {
CompiledModel->LookupArgIndex((Prefix + Spec.name()).str());
void *Buffer = nullptr;
InputIsPresent = Index >= 0;
- if (InputIsPresent)
- Buffer = CompiledModel->arg_data(Index);
+ if (InputIsPresent) {
+ const int ModelSize = CompiledModel->arg_size(Index);
+ if (ModelSize >= 0 &&
+ static_cast<size_t>(ModelSize) == Spec.getTotalTensorBufferSize()) {
+ Buffer = CompiledModel->arg_data(Index);
+ } else if (Valid) {
+ // Buffer stays null, so setUpBufferForTensor gives us a scratch one.
+ // One bad shape usually mismatches every tensor, so report only once.
+ Valid = false;
+ Ctx.emitError("The compiled model expects " + Twine(ModelSize) +
+ " bytes for input '" + Spec.name() + "', but " +
+ Twine(Spec.getTotalTensorBufferSize()) +
+ " were requested.");
+ }
+ }
setUpBufferForTensor(Pos, Spec, Buffer);
}
@@ -133,6 +150,7 @@ class ReleaseModeModelRunner final : public MLModelRunner {
}
int32_t ResultIndex = -1;
+ bool Valid = true;
std::unique_ptr<TGen> CompiledModel;
};
@@ -151,6 +169,7 @@ class NoopSavedModelImpl final {
void Run() { llvm_unreachable(NOOP_MODEL_ERRMSG); }
void *result_data(int) { llvm_unreachable(NOOP_MODEL_ERRMSG); }
void *arg_data(int) { llvm_unreachable(NOOP_MODEL_ERRMSG); }
+ int arg_size(int) { llvm_unreachable(NOOP_MODEL_ERRMSG); }
#undef NOOP_MODEL_ERRMSG
};
diff --git a/llvm/include/llvm/Analysis/Utils/MLGOUtils.h b/llvm/include/llvm/Analysis/Utils/MLGOUtils.h
index 6bd69d26ae8a5..2010d2512934a 100644
--- a/llvm/include/llvm/Analysis/Utils/MLGOUtils.h
+++ b/llvm/include/llvm/Analysis/Utils/MLGOUtils.h
@@ -72,8 +72,13 @@ std::unique_ptr<MLModelRunner> createReleaseModeModelRunner(
if constexpr (HaveMLIRLowering) {
return CreateEmitCModelRunner(Ctx, InputFeatures);
} else {
- return std::make_unique<ReleaseModeModelRunner<CompiledModelType>>(
+ auto Runner = std::make_unique<ReleaseModeModelRunner<CompiledModelType>>(
Ctx, InputFeatures, DecisionName, Options);
+ // Shapes the model was compiled for do not match the requested ones. The
+ // error is already reported, so let the caller fall back.
+ if (!Runner->isValid())
+ return nullptr;
+ return Runner;
}
}
diff --git a/llvm/lib/Analysis/MLInlineAdvisor.cpp b/llvm/lib/Analysis/MLInlineAdvisor.cpp
index fd0e4b152bcc2..27c8d20f0c46a 100644
--- a/llvm/lib/Analysis/MLInlineAdvisor.cpp
+++ b/llvm/lib/Analysis/MLInlineAdvisor.cpp
@@ -252,6 +252,7 @@ MLInlineAdvisor::MLInlineAdvisor(
ModelRunner = GetModelRunner(getFeatureMap());
if (!ModelRunner) {
M.getContext().emitError("Could not create model runner");
+ ForceStop = true;
return;
}
ModelRunner->switchContext("");
diff --git a/llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py b/llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py
index 5af2fb2878b5b..f47b7cfbfc4c1 100644
--- a/llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py
+++ b/llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py
@@ -24,7 +24,8 @@
]
"""
PER_REGISTER_FEATURE_LIST = ["mask"]
-NUM_REGISTERS = 33
+# Must match getRequiredNumColumns() for the target the tests run on (X86).
+NUM_REGISTERS = 37
def get_input_signature():
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index 63bf01c3282a4..f1c3e6112f912 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -278,8 +278,11 @@ struct LIFeatureComponents {
bool IsRemat = false;
};
+// Inline capacity hint only, the real width is target-derived.
+static constexpr unsigned ExpectedMaxColumns = 40;
+
using CandidateRegList =
- SmallVector<std::pair<MCRegister, bool>, CompiledModelNumColumns>;
+ SmallVector<std::pair<MCRegister, bool>, ExpectedMaxColumns>;
using FeaturesListNormalizer =
llvm::SmallVector<float, FeatureIDs::FeatureCount>;
@@ -296,6 +299,7 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
return static_cast<const RegAllocEvictionAdvisor &>(DefaultAdvisor);
}
+ // By convention the last column holds the virt reg seeking allocation.
const ArrayRef<TensorSpec> InputFeatures;
const size_t NumColumns;
const size_t CandidateVirtRegPos = NumColumns - 1;
@@ -366,6 +370,9 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
mutable DenseMap<unsigned, unsigned> VirtRegEvictionCounts;
+ // Reset per eviction attempt rather than reallocated.
+ mutable CandidateRegList Regs;
+
void onEviction(Register RegBeingEvicted) const {
// If we cannot find the virtual register in the map, we just assume it has
// not been evicted before and thus has a value of zero (which is what the
@@ -384,13 +391,22 @@ class MLEvictAdvisor : public RegAllocEvictionAdvisor {
#define _DECL_FEATURES(type, name, shape, _) \
TensorSpec::createSpec<type>(#name, shape),
-static int64_t getRequiredNumColumns(const TargetRegisterInfo &TRI,
- const RegisterClassInfo &RegClassInfo) {
- unsigned MaxOrder = 0;
+// Widest allocation order across all register classes, plus the candidate. A
+// runner fixes its tensor shapes once, so this has to be a target-static bound
+// rather than the per-function allocatable count.
+static int64_t getRequiredNumColumns(const TargetRegisterInfo &TRI) {
+ unsigned MaxRegs = 0;
for (const TargetRegisterClass &RC : TRI.regclasses())
if (RC.isAllocatable())
- MaxOrder = std::max(MaxOrder, RegClassInfo.getNumAllocatableRegs(&RC));
- return MaxOrder + 1;
+ MaxRegs = std::max(MaxRegs, RC.getNumRegs());
+ return MaxRegs + 1;
+}
+
+// RA_EVICT_FEATURES_LIST expands the bare name PerLiveRangeShape, so the local
+// below is what gives the specs their width.
+static std::vector<TensorSpec> getInputFeatures(int64_t NumColumns) {
+ const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
+ return {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
}
// ===================================
@@ -410,30 +426,36 @@ class ReleaseModeEvictionAdvisorProvider final
std::unique_ptr<RegAllocEvictionAdvisor>
getAdvisor(const MachineFunction &MF, const RAGreedy &RA,
MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *Loops) override {
- if (!Runner) {
- NumColumns =
- InteractiveChannelBaseName.empty()
- ? CompiledModelNumColumns
- : getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo(),
- RA.getRegClassInfo());
- const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
- InputFeatures = {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
- Runner = createReleaseModeModelRunner<CompiledModelType,
- HaveMLIRLoweringRegAlloc>(
- MF.getFunction().getContext(), InputFeatures, DecisionName,
- InteractiveChannelBaseName, DecisionSpec,
- createMLGORegAllocModelRunner);
- }
+ initializeOnce(MF);
assert(MBFI && Loops &&
"Invalid provider state: must have analysis available");
+ // RAGreedy cannot cope with a null advisor, and the reason we have no
+ // runner has already been reported.
+ if (!Runner)
+ return std::make_unique<DefaultEvictionAdvisor>(MF, RA);
return std::make_unique<MLEvictAdvisor>(MF, RA, Runner.get(), InputFeatures,
*MBFI, *Loops);
}
private:
+ // Deferred: the tensor width is target-derived, and the target is only
+ // reachable from a MachineFunction.
+ void initializeOnce(const MachineFunction &MF) {
+ if (Initialized)
+ return;
+ Initialized = true;
+ InputFeatures = getInputFeatures(
+ getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo()));
+ Runner = createReleaseModeModelRunner<CompiledModelType,
+ HaveMLIRLoweringRegAlloc>(
+ MF.getFunction().getContext(), InputFeatures, DecisionName,
+ InteractiveChannelBaseName, DecisionSpec,
+ createMLGORegAllocModelRunner);
+ }
+
std::vector<TensorSpec> InputFeatures;
std::unique_ptr<MLModelRunner> Runner;
- int64_t NumColumns = CompiledModelNumColumns;
+ bool Initialized = false;
};
class ReleaseModeEvictionAdvisorAnalysisLegacy final
@@ -478,6 +500,18 @@ static const TensorSpec Reward = TensorSpec::createSpec<float>("reward", {1});
#define _DECL_TRAIN_FEATURES(type, name, shape, _) \
TensorSpec::createSpec<type>(std::string("action_") + #name, shape),
+static bool isDevModeRequested() {
+ return !ModelUnderTraining.empty() || !TrainingLog.empty();
+}
+
+static std::vector<TensorSpec> getTrainingInputFeatures(int64_t NumColumns) {
+ const std::vector<int64_t> PerLiveRangeShape{1, NumColumns};
+ return {RA_EVICT_FEATURES_LIST(_DECL_TRAIN_FEATURES)
+ TensorSpec::createSpec<float>("action_discount", {1}),
+ TensorSpec::createSpec<int32_t>("action_step_type", {1}),
+ TensorSpec::createSpec<float>("action_reward", {1})};
+}
+
class DevelopmentModeEvictAdvisor : public MLEvictAdvisor {
public:
DevelopmentModeEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
@@ -501,46 +535,9 @@ class DevelopmentModeEvictionAdvisorProvider final
public:
DevelopmentModeEvictionAdvisorProvider(LLVMContext &Ctx)
: RegAllocEvictionAdvisorProvider(AdvisorMode::Development, Ctx) {
- const std::vector<int64_t> PerLiveRangeShape{1, CompiledModelNumColumns};
- InputFeatures = {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)};
- TrainingInputFeatures = {
- RA_EVICT_FEATURES_LIST(_DECL_TRAIN_FEATURES)
- TensorSpec::createSpec<float>("action_discount", {1}),
- TensorSpec::createSpec<int32_t>("action_step_type", {1}),
- TensorSpec::createSpec<float>("action_reward", {1})};
- if (ModelUnderTraining.empty() && TrainingLog.empty()) {
+ if (!isDevModeRequested())
Ctx.emitError("Regalloc development mode should be requested with at "
"least logging enabled and/or a training model");
- return;
- }
- if (ModelUnderTraining.empty())
- Runner = std::make_unique<NoInferenceModelRunner>(Ctx, InputFeatures);
- else
- Runner = ModelUnderTrainingRunner::createAndEnsureValid(
- Ctx, ModelUnderTraining, DecisionName, TrainingInputFeatures);
- if (!Runner) {
- Ctx.emitError("Regalloc: could not set up the model runner");
- return;
- }
- if (TrainingLog.empty())
- return;
- std::error_code EC;
- auto OS = std::make_unique<raw_fd_ostream>(TrainingLog, EC);
- if (EC) {
- Ctx.emitError(EC.message() + ":" + TrainingLog);
- return;
- }
- std::vector<TensorSpec> LFS = InputFeatures;
- if (auto *MUTR = dyn_cast<ModelUnderTrainingRunner>(Runner.get()))
- append_range(LFS, MUTR->extraOutputsForLoggingSpecs());
- // We always log the output; in particular, if we're not evaluating, we
- // don't have an output spec json file. That's why we handle the
- // 'normal' output separately.
- LFS.push_back(DecisionSpec);
-
- Log = std::make_unique<Logger>(std::move(OS), LFS, Reward,
- /*IncludeReward*/ true);
- return;
}
// support for isa<> and dyn_cast.
@@ -567,20 +564,64 @@ class DevelopmentModeEvictionAdvisorProvider final
std::unique_ptr<RegAllocEvictionAdvisor>
getAdvisor(const MachineFunction &MF, const RAGreedy &RA,
MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *Loops) override {
+ initializeOnce(MF);
+ assert(MBFI && Loops &&
+ "Invalid provider state: must have analysis available");
+ // RAGreedy cannot cope with a null advisor, and the reason we have no
+ // runner has already been reported.
if (!Runner)
- return nullptr;
+ return std::make_unique<DefaultEvictionAdvisor>(MF, RA);
if (Log)
Log->switchContext(MF.getName());
- assert(MBFI && Loops &&
- "Invalid provider state: must have analysis available");
return std::make_unique<DevelopmentModeEvictAdvisor>(
MF, RA, Runner.get(), InputFeatures, *MBFI, *Loops, Log.get());
}
private:
- std::vector<TensorSpec> InputFeatures;
- std::vector<TensorSpec> TrainingInputFeatures;
+ // Deferred: the tensor width is target-derived, and the target is only
+ // reachable from a MachineFunction.
+ void initializeOnce(const MachineFunction &MF) {
+ if (Initialized)
+ return;
+ Initialized = true;
+ if (!isDevModeRequested())
+ return;
+ const int64_t NumColumns =
+ getRequiredNumColumns(*MF.getSubtarget().getRegisterInfo());
+ InputFeatures = getInputFeatures(NumColumns);
+ const std::vector<TensorSpec> TrainingInputFeatures =
+ getTrainingInputFeatures(NumColumns);
+ if (ModelUnderTraining.empty())
+ Runner = std::make_unique<NoInferenceModelRunner>(Ctx, InputFeatures);
+ else
+ Runner = ModelUnderTrainingRunner::createAndEnsureValid(
+ Ctx, ModelUnderTraining, DecisionName, TrainingInputFeatures);
+ if (!Runner) {
+ Ctx.emitError("Regalloc: could not set up the model runner");
+ return;
+ }
+ if (TrainingLog.empty())
+ return;
+ std::error_code EC;
+ auto OS = std::make_unique<raw_fd_ostream>(TrainingLog, EC);
+ if (EC) {
+ Ctx.emitError(EC.message() + ":" + TrainingLog);
+ return;
+ }
+ std::vector<TensorSpec> LFS = InputFeatures;
+ if (auto *MUTR = dyn_cast<ModelUnderTrainingRunner>(Runner.get()))
+ append_range(LFS, MUTR->extraOutputsForLoggingSpecs());
+ // We always log the output; in particular, if we're not evaluating, we
+ // don't have an output spec json file. That's why we handle the
+ // 'normal' output separately.
+ LFS.push_back(DecisionSpec);
+ Log = std::make_unique<Logger>(std::move(OS), LFS, Reward,
+ /*IncludeReward*/ true);
+ }
+
+ std::vector<TensorSpec> InputFeatures;
+ bool Initialized = false;
std::unique_ptr<MLModelRunner> Runner;
std::unique_ptr<Logger> Log;
};
@@ -758,7 +799,7 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
// Track the index->register mapping because AllocationOrder doesn't do that
// and we'd have to scan it.
// Also track their mask, to write asserts/debug.
- CandidateRegList Regs(NumColumns);
+ Regs.assign(NumColumns, {MCRegister(), false});
// Track the largest value of features seen during this eviction session. We
// only normalize (some of) the float features, but it's just simpler to
@@ -772,9 +813,10 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
// reset all the features to 0) Use Pos to capture the column we load
// features at - in AllocationOrder order.
size_t Pos = 0;
- SmallVector<LRStartEndInfo, CompiledModelNumColumns> LRPosInfo;
- // The order can outrun the tensor width (fixed-width precompiled model,
- // duplicated hints), so drop the tail rather than write out of bounds.
+ SmallVector<LRStartEndInfo, ExpectedMaxColumns> LRPosInfo;
+ // Hints are iterated ahead of the order proper, so the Pos bound is what
+ // keeps a target that hints outside its own class from writing past the
+ // tensor.
for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit);
I != E && Pos < CandidateVirtRegPos; ++I, ++Pos) {
MCRegister PhysReg = *I;
@@ -812,9 +854,11 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
++FeatureIndex) {
if (DoNotNormalize.test(FeatureIndex))
continue;
+ // Skip the columns past ValidPosLimit: never written, so still 0.
float *Tensor = Runner->getTensor<float>(FeatureIndex);
- for (size_t Pos = 0; Pos < NumColumns; ++Pos)
- Tensor[Pos] /= Largest[FeatureIndex];
+ for (size_t P = 0; P < ValidPosLimit; ++P)
+ Tensor[P] /= Largest[FeatureIndex];
+ Tensor[CandidateVirtRegPos] /= Largest[FeatureIndex];
}
*Runner->getTensor<float>(FeatureIDs::progress) =
static_cast<float>(RA.getQueueSize()) / InitialQSize;
@@ -831,7 +875,6 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
return MCRegister::NoRegister;
}
assert(CandidatePos < ValidPosLimit);
- (void)ValidPosLimit;
// Update information about how many times the virtual registers being
// evicted have been evicted so that we can prevent the model from evicting
@@ -1017,8 +1060,9 @@ int64_t DevelopmentModeEvictAdvisor::tryFindEvictionCandidatePosition(
if (!PhysReg)
Ret = CandidateVirtRegPos;
else
+ // Same bound as the feature-loading loop in tryFindEvictionCandidate.
for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit);
- I != E; ++I, ++Ret)
+ I != E && static_cast<size_t>(Ret) < CandidateVirtRegPos; ++I, ++Ret)
if (*I == PhysReg)
break;
}
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
index 5215f486efb44..d98ed4594510d 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.h
@@ -33,17 +33,6 @@ struct LRStartEndInfo {
size_t Pos = 0;
};
-// Logically, we can think of the feature set given to the evaluator as a 2D
-// matrix. The rows are the features (see next). The columns correspond to the
-// interferences. We treat the candidate virt reg as an 'interference', too, as
-// its feature set is the same as that of the interferring ranges. So we'll have
-// one column per allocation order slot, plus one, and by convention, we will
-// use the last column for the virt reg seeking allocation.
-// The AOT and reference models bake this width in and do not expose it, so
-// changing it requires regenerating them. The interactive channel derives its
-// own width from the target instead.
-static const int64_t CompiledModelNumColumns = 33;
-
// The number of instructions that a specific live range might have is variable,
// but we're passing in a single matrix of instructions and tensorflow saved
// models only support a fixed input size, so we have to cap the number of
@@ -54,13 +43,9 @@ static const int ModelMaxSupportedInstructionCount = 300;
// When extracting per-instruction features, the advisor will currently create
// a vector of size ModelMaxSupportedInstructionCount to hold the opcodes of the
-// instructions relevant to the eviction problem, and a NumberOfInterferences *
-// ModelMaxSupportedInstructionCount matrix that maps LRs to the instructions
-// that they span.
+// instructions relevant to the eviction problem.
static const std::vector<int64_t> InstructionsShape{
1, ModelMaxSupportedInstructionCount};
-static const std::vector<int64_t> InstructionsMappingShape{
- 1, CompiledModelNumColumns, ModelMaxSupportedInstructionCount};
// When extracting mappings between MBBs and individual instructions, we create
// a vector of MBB frequencies, currently of size 100, which was a value
diff --git a/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt b/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
index 37bb0c79d7c63..5fb5e7aca1556 100644
--- a/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
+++ b/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
@@ -1,433 +1,433 @@
context: SyFgets
observation: 0
-mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
-is_free: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-nr_urgent: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0
-nr_broken_hints: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1.0
-is_hint: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-is_local: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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observation: 5
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progress: 0.7777777910232544
index_to_evict: 14
reward: 0.0
observation: 12
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reward: 0.0
observation: 13
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+hint_weights_by_max: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1.0,0.07419288158416748,0.9258071184158325,0.0,0.0,0.8734684586524963,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.02473096176981926
+start_bb_freq_by_max: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.35764437913894653,0.35764437913894653,0.35764437913894653,0.35764437913894653,0.7152887582778931,1.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.7152887582778931
+end_bb_freq_by_max: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.6365708112716675,0.6365708112716675,0.3333333432674408,0.6365708112716675,0.6365708112716675,1.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.6365708112716675
+hottest_bb_freq_by_max: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.2813863754272461,0.2631579041481018,0.27892643213272095,1.0,0.27892643213272095,0.2631579041481018,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.02235277369618416
+liverange_size: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1.0,0.9680746793746948,0.5854616761207581,0.8521611094474792,0.9228880405426025,0.326129674911499,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.9887033104896545
+use_def_density: 0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.33175867795944214,0.06907084584236145,0.7714304327964783,0.374875545501709,0.7819314002990723,1.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.007078035734593868
+max_stage: 0,0,0,0,0,0,0,0,0,4,4,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4
+min_stage: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4
progress: 0.0833333358168602
-index_to_evict: 32
+index_to_evict: 36
reward: 37.60835647583008
diff --git a/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll b/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
index 23ff76df50847..caa44b485ca07 100644
--- a/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
+++ b/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
@@ -38,13 +38,13 @@
; CHECK-TWO-FCTS: context: SyFgets
; CHECK-TWO-FCTS-NEXT: observation: 0
-; CHECK-TWO-FCTS-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
+; CHECK-TWO-FCTS-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
; CHECK-TWO-FCTS: index_to_evict: 11
; CHECK-TWO-FCTS: observation: 17
; CHECK-TWO-FCTS: reward: 37.60
; CHECK-TWO-FCTS: context: SyFgetsCopy
; CHECK-TWO-FCTS-NEXT: observation: 0
-; CHECK-TWO-FCTS-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
+; CHECK-TWO-FCTS-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
; CHECK-TWO-FCTS: index_to_evict: 11
; CHECK-TWO-FCTS: observation: 17
; CHECK-TWO-FCTS: reward: 37.60
diff --git a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
index f6302bfb08a57..e07a1621b09fa 100644
--- a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
+++ b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
@@ -13,9 +13,9 @@
;; expected one - the index of the first legal register
; CHECK: context: SyFgets
; CHECK-NEXT: observation: 0
-; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,1
+; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
; CHECK: observation: 1
-; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,1
+; CHECK-NEXT: mask: 0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
; CHECK: context: SyFgetsCopy
; CHECK-NEXT: observation: 0
diff --git a/llvm/unittests/Analysis/MLGOUtilsTest.cpp b/llvm/unittests/Analysis/MLGOUtilsTest.cpp
index 34e2e1a71b3c9..a9ecc5bee2c48 100644
--- a/llvm/unittests/Analysis/MLGOUtilsTest.cpp
+++ b/llvm/unittests/Analysis/MLGOUtilsTest.cpp
@@ -46,6 +46,9 @@ class MockAOTModel final {
return nullptr;
}
}
+ int arg_size(int Index) {
+ return (Index == 0 || Index == 1) ? sizeof(int64_t) : 0;
+ }
};
class MockEmitCModel1 final {
diff --git a/llvm/unittests/Analysis/MLModelRunnerTest.cpp b/llvm/unittests/Analysis/MLModelRunnerTest.cpp
index 5179d673cfa97..b537b11ee6d3f 100644
--- a/llvm/unittests/Analysis/MLModelRunnerTest.cpp
+++ b/llvm/unittests/Analysis/MLModelRunnerTest.cpp
@@ -69,6 +69,9 @@ class MockAOTModelBase {
return nullptr;
}
}
+ virtual int arg_size(int Index) {
+ return (Index == 0 || Index == 1) ? sizeof(int64_t) : 0;
+ }
};
class AdditionAOTModel final : public MockAOTModelBase {
@@ -119,6 +122,11 @@ class ComposedAOTModel final {
return Selector;
return getModel()->arg_data(Index);
}
+ int arg_size(int Index) {
+ if (Index == 2)
+ return sizeof(Selector);
+ return getModel()->arg_size(Index);
+ }
void *result_data(int RIndex) { return getModel()->result_data(RIndex); }
void Run() { getModel()->Run(); }
};
@@ -210,6 +218,15 @@ TEST(ReleaseModeRunner, ExtraFeaturesOutOfOrder) {
}
namespace {
+struct CountingDiagnosticHandler : public DiagnosticHandler {
+ unsigned NumErrors = 0;
+ bool handleDiagnostics(const DiagnosticInfo &DI) override {
+ if (DI.getSeverity() == DS_Error)
+ ++NumErrors;
+ return true;
+ }
+};
+
struct AbortOnErrorDiagnosticHandler : public DiagnosticHandler {
bool handleDiagnostics(const DiagnosticInfo &DI) override {
DiagnosticPrinterRawOStream DP(errs());
@@ -223,6 +240,25 @@ struct AbortOnErrorDiagnosticHandler : public DiagnosticHandler {
};
} // namespace
+// A spec wider than what the model was compiled for must not be given the model
+// buffer. One error is reported for the whole runner, not one per tensor.
+TEST(ReleaseModeRunner, ShapeMismatch) {
+ LLVMContext Ctx;
+ auto Handler = std::make_unique<CountingDiagnosticHandler>();
+ auto *HandlerPtr = Handler.get();
+ Ctx.setDiagnosticHandler(std::move(Handler));
+ std::vector<TensorSpec> Inputs{TensorSpec::createSpec<int64_t>("a", {4}),
+ TensorSpec::createSpec<int64_t>("b", {4})};
+ ReleaseModeModelRunner<AdditionAOTModel> Evaluator(Ctx, Inputs, "",
+ makeOptions());
+ EXPECT_FALSE(Evaluator.isValid());
+ EXPECT_EQ(HandlerPtr->NumErrors, 1u);
+ // The scratch buffers are sized after the requested specs.
+ for (int64_t I = 0; I < 4; ++I)
+ Evaluator.getTensor<int64_t>(0)[I] = I;
+ EXPECT_EQ(Evaluator.getTensor<int64_t>(0)[3], 3);
+}
+
// We expect an error to be reported early if the user tried to specify a model
// selector, but the model in fact doesn't support that.
TEST(ReleaseModelRunner, ModelSelectorNoInputFeaturePresent) {
diff --git a/mlir/test/Integration/Dialect/EmitC/regalloc-eviction-test-model-tosa.mlir b/mlir/test/Integration/Dialect/EmitC/regalloc-eviction-test-model-tosa.mlir
index f9828f67121e5..05b65e0f00f08 100644
--- a/mlir/test/Integration/Dialect/EmitC/regalloc-eviction-test-model-tosa.mlir
+++ b/mlir/test/Integration/Dialect/EmitC/regalloc-eviction-test-model-tosa.mlir
@@ -64,9 +64,9 @@
// CHECK: conditional
// CHECK: assign
module attributes {tf_saved_model.semantics, tfl.description = "MLIR Converted.", tfl.schema_version = 3 : i32} {
- func.func @mock_model(%arg0: tensor<33xi64> {tf_saved_model.index_path = ["mask"]}) -> (tensor<i64> {tf_saved_model.index_path = ["index_to_evict"]}) attributes {tf.entry_function = {inputs = "action_mask:0", outputs = "StatefulPartitionedCall:0"}, tf_saved_model.exported_names = ["action"]} {
- %0 = tosa.cast %arg0 : (tensor<33xi64>) -> tensor<33xi32>
- %1 = tosa.argmax %0 {axis = 0 : i32} : (tensor<33xi32>) -> tensor<i64>
+ func.func @mock_model(%arg0: tensor<37xi64> {tf_saved_model.index_path = ["mask"]}) -> (tensor<i64> {tf_saved_model.index_path = ["index_to_evict"]}) attributes {tf.entry_function = {inputs = "action_mask:0", outputs = "StatefulPartitionedCall:0"}, tf_saved_model.exported_names = ["action"]} {
+ %0 = tosa.cast %arg0 : (tensor<37xi64>) -> tensor<37xi32>
+ %1 = tosa.argmax %0 {axis = 0 : i32} : (tensor<37xi32>) -> tensor<i64>
return %1 : tensor<i64>
}
}
>From 21cd000e9613ab3dfa88aa8001ba5bf7a637d9c1 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 30 Sep 2026 11:49:22 +0200
Subject: [PATCH 5/5] NumColumns
---
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index f1c3e6112f912..9bf91c84615b5 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -854,11 +854,9 @@ MCRegister MLEvictAdvisor::tryFindEvictionCandidate(
++FeatureIndex) {
if (DoNotNormalize.test(FeatureIndex))
continue;
- // Skip the columns past ValidPosLimit: never written, so still 0.
float *Tensor = Runner->getTensor<float>(FeatureIndex);
- for (size_t P = 0; P < ValidPosLimit; ++P)
+ for (size_t P = 0; P < NumColumns; ++P)
Tensor[P] /= Largest[FeatureIndex];
- Tensor[CandidateVirtRegPos] /= Largest[FeatureIndex];
}
*Runner->getTensor<float>(FeatureIDs::progress) =
static_cast<float>(RA.getQueueSize()) / InitialQSize;
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